Behavioral Architecture Reference

Processes
set_mem_ctr_i_del_proc	( clk_i_dom )
set_mem_ctr_o_del_proc	( clk_o_dom )
i_ctr_proc	( clk_i_dom )
o_ctr_proc	( clk_o_dom )

Components
block_mem

Signals
set_mem_ctr_i_r	std_logic
set_mem_ctr_o_r	std_logic
ctr_i	unsigned ( 2 downto 0 )
ctr_o	unsigned ( 2 downto 0 )
ctr_i_next	unsigned ( 2 downto 0 )
ctr_o_next	unsigned ( 2 downto 0 )
ena	STD_LOGIC
wea	STD_LOGIC_VECTOR ( 0 downto 0 )
addra	STD_LOGIC_VECTOR ( 2 downto 0 )
dina	STD_LOGIC_VECTOR ( numbits - 1 downto 0 )
doutb	STD_LOGIC_VECTOR ( numbits - 1 downto 0 )
rstb	STD_LOGIC
enb	STD_LOGIC
addrb	STD_LOGIC_VECTOR ( 2 downto 0 )

Instantiations
block_mem_i	block_mem

Detailed Description

Definition at line 45 of file mini_fifo.vhd.

Member Function Documentation

i_ctr_proc (   clk_i_dom   )

Process

Definition at line 112 of file mini_fifo.vhd.

o_ctr_proc (   clk_o_dom   )

Process

Definition at line 125 of file mini_fifo.vhd.

set_mem_ctr_i_del_proc (   clk_i_dom   )

Process

Definition at line 96 of file mini_fifo.vhd.

set_mem_ctr_o_del_proc (   clk_o_dom   )

Process

Definition at line 104 of file mini_fifo.vhd.

Member Data Documentation

addra STD_LOGIC_VECTOR ( 2 downto 0 )

Signal

Definition at line 69 of file mini_fifo.vhd.

addrb STD_LOGIC_VECTOR ( 2 downto 0 )

Signal

Definition at line 76 of file mini_fifo.vhd.

block_mem

Component

Definition at line 79 of file mini_fifo.vhd.

block_mem_i block_mem

Instantiation

Definition at line 157 of file mini_fifo.vhd.

ctr_i unsigned ( 2 downto 0 )

Signal

Definition at line 60 of file mini_fifo.vhd.

ctr_i_next unsigned ( 2 downto 0 )

Signal

Definition at line 62 of file mini_fifo.vhd.

ctr_o unsigned ( 2 downto 0 )

Signal

Definition at line 61 of file mini_fifo.vhd.

ctr_o_next unsigned ( 2 downto 0 )

Signal

Definition at line 63 of file mini_fifo.vhd.

dina STD_LOGIC_VECTOR ( numbits - 1 downto 0 )

Signal

Definition at line 70 of file mini_fifo.vhd.

doutb STD_LOGIC_VECTOR ( numbits - 1 downto 0 )

Signal

Definition at line 72 of file mini_fifo.vhd.

ena STD_LOGIC

Signal

Definition at line 67 of file mini_fifo.vhd.

enb STD_LOGIC

Signal

Definition at line 75 of file mini_fifo.vhd.

rstb STD_LOGIC

Signal

Definition at line 74 of file mini_fifo.vhd.

set_mem_ctr_i_r std_logic

Signal

Definition at line 55 of file mini_fifo.vhd.

set_mem_ctr_o_r std_logic

Signal

Definition at line 55 of file mini_fifo.vhd.

wea STD_LOGIC_VECTOR ( 0 downto 0 )

Signal

Definition at line 68 of file mini_fifo.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/mini_fifo.vhd