Behavioral Architecture Reference

Processes
PROCESS_1	( clk80 )

Components
PARITY_CALC	<Entity PARITY_CALC>

Signals
PDATA_24	std_logic_vector ( 23 downto 0 )
NDATA_24	std_logic_vector ( 23 downto 0 )
P_temp_reg	std_logic_vector ( numbitsinchan - 1 downto 0 )
N_temp_reg	std_logic_vector ( numbitsinchan - 1 downto 0 )
parP	std_logic
parN	std_logic
parP_odd_err	std_logic
parN_odd_err	std_logic
parP_odd_err_reg	std_logic
parN_odd_err_reg	std_logic

Attributes
keep	string
keep	parP_odd_err , parN_odd_err , parP_odd_err_reg , parN_odd_err_reg : signal is " TRUE "

Instantiations
pcalcp	PARITY_CALC <Entity PARITY_CALC>
pcalcn	PARITY_CALC <Entity PARITY_CALC>

Detailed Description

Definition at line 36 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

Member Function Documentation

PROCESS_1

(

clk80

)

Definition at line 115 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

Member Data Documentation

keep string

Attribute

Definition at line 38 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

keep parP_odd_err , parN_odd_err , parP_odd_err_reg , parN_odd_err_reg : signal is " TRUE "

Attribute

Definition at line 77 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

N_temp_reg std_logic_vector ( numbitsinchan - 1 downto 0 )

Signal

Definition at line 55 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

NDATA_24 std_logic_vector ( 23 downto 0 )

Signal

Definition at line 40 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

P_temp_reg std_logic_vector ( numbitsinchan - 1 downto 0 )

Signal

Definition at line 44 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

PARITY_CALC

Component

Definition at line 79 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

parN std_logic

Signal

Definition at line 60 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

parN_odd_err std_logic

Signal

Definition at line 63 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

parN_odd_err_reg std_logic

Signal

Definition at line 66 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

parP std_logic

Signal

Definition at line 60 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

parP_odd_err std_logic

Signal

Definition at line 63 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

parP_odd_err_reg std_logic

Signal

Definition at line 66 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

pcalcn PARITY_CALC

Instantiation

Definition at line 109 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

pcalcp PARITY_CALC

Instantiation

Definition at line 108 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

PDATA_24 std_logic_vector ( 23 downto 0 )

Signal

Definition at line 40 of file BUF_2X24_AT_80_TO_1X96_AT_40.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/BUF_2X24_AT_80_TO_1X96_AT_40.vhd