Behavioral Architecture Reference

Processes
PROCESS_2	( delayed_cable_clock_buffered )

Signals
delayed_ddr_data_in	std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )
delayed_cable_clock	std_logic
delayed_cable_clock_buffered	std_logic
PDATA	std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )
NDATA	std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )
i_pll_locked	std_logic
parity_P	std_logic
parity_N	std_logic
parity_P_tmp	std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )
parity_N_tmp	std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )

Instantiations
bufr_inst	bufr
iddr_inst	iddr

Detailed Description

Definition at line 40 of file CMX_cable_clocked_80Mbps_input_module.vhd.

Member Function Documentation

PROCESS_2

(

delayed_cable_clock_buffered

)

Definition at line 135 of file CMX_cable_clocked_80Mbps_input_module.vhd.

Member Data Documentation

bufr_inst bufr

Instantiation

Definition at line 97 of file CMX_cable_clocked_80Mbps_input_module.vhd.

delayed_cable_clock std_logic

Signal

Definition at line 48 of file CMX_cable_clocked_80Mbps_input_module.vhd.

delayed_cable_clock_buffered std_logic

Signal

Definition at line 49 of file CMX_cable_clocked_80Mbps_input_module.vhd.

delayed_ddr_data_in std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )

Signal

Definition at line 44 of file CMX_cable_clocked_80Mbps_input_module.vhd.

i_pll_locked std_logic

Signal

Definition at line 53 of file CMX_cable_clocked_80Mbps_input_module.vhd.

iddr_inst iddr

Instantiation

Definition at line 117 of file CMX_cable_clocked_80Mbps_input_module.vhd.

NDATA std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )

Signal

Definition at line 51 of file CMX_cable_clocked_80Mbps_input_module.vhd.

parity_N std_logic

Signal

Definition at line 56 of file CMX_cable_clocked_80Mbps_input_module.vhd.

parity_N_tmp std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )

Signal

Definition at line 58 of file CMX_cable_clocked_80Mbps_input_module.vhd.

parity_P std_logic

Signal

Definition at line 55 of file CMX_cable_clocked_80Mbps_input_module.vhd.

parity_P_tmp std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )

Signal

Definition at line 57 of file CMX_cable_clocked_80Mbps_input_module.vhd.

PDATA std_logic_vector ( numbits_in_cable_connector - 1 downto 0 )

Signal

Definition at line 51 of file CMX_cable_clocked_80Mbps_input_module.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_cable_clocked_80Mbps_input_module.vhd