CMX_cable_clocked_80Mbps_input_module Entity Reference

Inheritance diagram for CMX_cable_clocked_80Mbps_input_module:

Entities
Behavioral	architecture

Libraries
IEEE
UNISIM
work

Use Clauses
IEEE.STD_LOGIC_1164.all
IEEE.NUMERIC_STD.all
UNISIM.VComponents.all
work.CMXpackage.all

Generics
numbits_in_cable_connector	integer

Ports
data	out std_logic_vector ( ( numbits_in_cable_connector * 2 ) - 1 downto 0 )
parity_error	out std_logic
forwarded_clock	out std_logic
ddr_data_in	in std_logic_vector ( numbits_in_cable_connector downto 0 )
buf_clk40	in std_logic
buf_clk200	in std_logic
pll_locked	in std_logic
del_array	in cable_del_array_type ( numbits_in_cable_connector downto 0 )
upload_delays	in std_logic

Detailed Description

Definition at line 22 of file CMX_cable_clocked_80Mbps_input_module.vhd.

Member Data Documentation

buf_clk200 in std_logic

Port

Definition at line 31 of file CMX_cable_clocked_80Mbps_input_module.vhd.

buf_clk40 in std_logic

Port

Definition at line 30 of file CMX_cable_clocked_80Mbps_input_module.vhd.

data out std_logic_vector ( ( numbits_in_cable_connector * 2 ) - 1 downto 0 )

Port

Definition at line 26 of file CMX_cable_clocked_80Mbps_input_module.vhd.

ddr_data_in in std_logic_vector ( numbits_in_cable_connector downto 0 )

Port

Definition at line 29 of file CMX_cable_clocked_80Mbps_input_module.vhd.

del_array in cable_del_array_type ( numbits_in_cable_connector downto 0 )

Port

Definition at line 33 of file CMX_cable_clocked_80Mbps_input_module.vhd.

forwarded_clock out std_logic

Port

Definition at line 28 of file CMX_cable_clocked_80Mbps_input_module.vhd.

IEEE

Library

Definition at line 11 of file CMX_cable_clocked_80Mbps_input_module.vhd.

IEEE.NUMERIC_STD.all

Package

Definition at line 13 of file CMX_cable_clocked_80Mbps_input_module.vhd.

IEEE.STD_LOGIC_1164.all

Package

Definition at line 12 of file CMX_cable_clocked_80Mbps_input_module.vhd.

numbits_in_cable_connector integer

Generic

Definition at line 24 of file CMX_cable_clocked_80Mbps_input_module.vhd.

parity_error out std_logic

Port

Definition at line 27 of file CMX_cable_clocked_80Mbps_input_module.vhd.

pll_locked in std_logic

Port

Definition at line 32 of file CMX_cable_clocked_80Mbps_input_module.vhd.

UNISIM

Library

Definition at line 15 of file CMX_cable_clocked_80Mbps_input_module.vhd.

UNISIM.VComponents.all

Package

Definition at line 16 of file CMX_cable_clocked_80Mbps_input_module.vhd.

upload_delays in std_logic

Port

Definition at line 34 of file CMX_cable_clocked_80Mbps_input_module.vhd.

work

Library

Definition at line 18 of file CMX_cable_clocked_80Mbps_input_module.vhd.

work.CMXpackage.all

Package

Definition at line 19 of file CMX_cable_clocked_80Mbps_input_module.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_cable_clocked_80Mbps_input_module.vhd