CMX_input_module_spy_mem_control_FSM.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;

entity CMX_input_module_spy_mem_control_FSM is
  generic( 
    ADDR_REG_RW_INPUT_SPY_MEM_X_WORD    : integer := 0;
    ADDR_REG_RW_INPUT_SPY_MEM_X_CONTROL : integer := 0;
    ADDR_REG_RO_INPUT_SPY_MEM_X_STATUS  : integer := 0
    );
  port (
    clk      : in std_logic;
    
    ncs      : in     std_logic;        --vme ports
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;
    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic;

    mode_control : out std_logic_vector(3 downto 0);  --controls the mode of
                                                      --running; modes can be
                                                      --CONST_DPR_CONTROL_SPY,
                                                      --CONST_DPR_CONTROL_PLAYBACK,
                                                      --CONST_DPR_CONTROL_VERIFY
                                                      --forwarded form the
                                                      --control register
                                                      --will be interpreted by
                                                      --the outside
                                                      --input_module to
                                                      --determine the data flow

    --memory steering ports
    ena      : out std_logic;
    wea      : out std_logic;
    addra    : out std_logic_vector(7 DOWNTO 0);
    
    mem_select_address : out std_logic_vector(3 downto 0);  --
    
    dina     : out std_logic_vector(95 DOWNTO 0);
    douta    : in  std_logic_vector(95 DOWNTO 0);

    --this should be used to inhibit enb web when memory is being written to or
    --read from vme on port a, high->inhibit, low->mode_control operation
    port_b_master_inhibit : out std_logic);
  
end CMX_input_module_spy_mem_control_FSM;

architecture multi_seg of CMX_input_module_spy_mem_control_FSM is

  --FSM states
  type state_spy_mem_control_type is (s_standby,  --the normal running mode, ihibit is
                                                  --released, no reads or writes from vme
                                      s_inhibit_init,  --after r/w request we
                                                       --need to raise the
                                                       --inhibit for 2 cycles
                                                       --so it can be propagated to
                                                       --the port B domain
                                      s_wait_for_vme_write,  -- write has been
                                                             -- requested, FSM waits
                                                             -- for data writes from VME
                                      s_writing_ram,  --all data words have been
                                                      --written to VME, uploading to RAM
                                      s_reading_ram,  --read has been requested,
                                                      --reading RAM
                                      s_wait_for_vme_read   --data has been read from
                                                            --RAM and presented to VME,
                                                            --waiting for SW to read it
                                                            --all out from VME.
                                      );
  signal state_reg, state_next : state_spy_mem_control_type;

  signal wea_sig,ena_sig : std_logic;
  signal dina_sig : std_logic_vector(95 downto 0);

  
  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  
  signal data_vme_from_below  : arr_16(7 downto 0);
  signal bus_drive_from_below : std_logic_vector(7 downto 0);
 
  
  component vme_outreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk         : in  std_logic;
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0);
      read_detect : out std_logic);
  end component vme_outreg_notri;

  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;


  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;

  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;
  
  
  
  --component vme_outreg
  --  generic (
  --    ia_vme : integer;
  --    width  : integer);
  --  port (
  --    clk         : in  std_logic;
  --    ncs         : in  std_logic;
  --    rd_nwr      : in  std_logic;
  --    ds          : in  std_logic;
  --    addr_vme    : in  std_logic_vector (15 downto 0);
  --    data_vme    : out std_logic_vector (15 downto 0);
  --    data_to_vme : in  std_logic_vector (width-1 downto 0);
  --    read_detect : out std_logic);
  --end component;
  --
  --component vme_inreg
  --  generic (
  --    ia_vme : integer;
  --    width  : integer);
  --  port (
  --    clk           : in    std_logic;
  --    ncs           : in    std_logic;
  --    rd_nwr        : in    std_logic;
  --    ds            : in    std_logic;
  --    addr_vme      : in    std_logic_vector (15 downto 0);
  --    data_vme      : inout std_logic_vector (15 downto 0);
  --    data_from_vme : out   std_logic_vector (width-1 downto 0);
  --    data_to_vme   : in    std_logic_vector (width-1 downto 0);
  --    read_detect   : out   std_logic;
  --    write_detect  : out   std_logic);
  --end component;

  --six sets of signals for the data registers
  signal data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD : arr_16(5 downto 0);
  signal data_to_vme_REG_RW_INPUT_SPY_MEM_X_WORD   : arr_16(5 downto 0);
  signal read_detect_REG_RW_INPUT_SPY_MEM_X_WORD   : std_logic_vector(5 downto 0);
  signal write_detect_REG_RW_INPUT_SPY_MEM_X_WORD  : std_logic_vector(5 downto 0);

  --control register signals
  signal data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL : std_logic_vector (15 downto 0);
  signal data_to_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL   : std_logic_vector (15 downto 0);
  signal read_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL   : std_logic;
  signal write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL  : std_logic;
  
  signal data_to_vme_REG_RO_INPUT_SPY_MEM_X_STATUS : std_logic_vector (15 downto 0);
  --signal read_detect_REG_RO_INPUT_SPY_MEM_X_STATUS : std_logic;

  signal status_summary: std_logic_vector(3 downto 0);  --included as part of
                                                        --the status register

  signal global_addr_counter: unsigned(12 downto 0); --counter specifying the
                                                     --memory that will be
                                                     --written to (upper 4
                                                     --bits) and the address
                                                     --(lower 8 bits)

  signal global_addr_counter_next: unsigned(12 downto 0);

  signal inhibit_init_counter: unsigned(0 downto 0);

  signal op_request: std_logic;         --bit signalling operation is requested
                                          --taken from 
  signal rw_request: std_logic;         --0 for read, 1 for write
                                        --

  signal port_b_master_inhibit_sig : std_logic;
  
  --component chipscope_icon_u2_c1
  --  port (
  --    CONTROL0 : inout std_logic_vector(35 downto 0));
  --end component;
  --
  --signal CONTROL0 : std_logic_vector(35 downto 0);
  --
  --component chipscope_ila_CMX_input_module_spy_mem_control_FSM
  --  port (
  --    CONTROL : inout std_logic_vector(35 downto 0);
  --    CLK     : in    std_logic;
  --    DATA    : in    std_logic_vector(260 downto 0);
  --    TRIG0   : in    std_logic_vector(15 downto 0));
  --end component;
  --
  --
  --signal DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM    : std_logic_vector(260 downto 0);
  --signal TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM   : std_logic_vector(15 downto 0);
  
begin  -- multi_seg

  
  
  --instantiate VME registers

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_from_below,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_from_below);
  
  ena<=ena_sig;
  wea<=wea_sig;
  dina<=dina_sig;

  port_b_master_inhibit<=port_b_master_inhibit_sig;
  
  vme_data_word_reg_gen: for word_i in 0 to 5 generate

    vme_inreg_REG_RW_INPUT_SPY_MEM_X_WORD: vme_inreg_notri
      generic map (
        ia_vme  => ADDR_REG_RW_INPUT_SPY_MEM_X_WORD+(2*word_i),
        width   => 16)
      port map (
        clk            => clk,
        ncs            => ncs,
        rd_nwr         => rd_nwr,
        ds             => ds,
        addr_vme       => addr_vme,
        data_vme_in    =>     data_vme_in,
        data_vme_out   =>     data_vme_from_below (word_i),
        bus_drive      =>     bus_drive_from_below (word_i),
        data_from_vme  => data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(word_i),
        data_to_vme    => data_to_vme_REG_RW_INPUT_SPY_MEM_X_WORD(word_i),
        read_detect    => read_detect_REG_RW_INPUT_SPY_MEM_X_WORD(word_i),
        write_detect   => write_detect_REG_RW_INPUT_SPY_MEM_X_WORD(word_i));


    --connect the output from RAM to VME for reading by SW
    data_to_vme_REG_RW_INPUT_SPY_MEM_X_WORD(word_i) <= douta( (word_i+1)*16 - 1 downto word_i*16);

  end generate vme_data_word_reg_gen;

  vme_inreg_REG_RW_INPUT_SPY_MEM_X_CONTROL: vme_inreg_notri
    generic map (
      ia_vme  => ADDR_REG_RW_INPUT_SPY_MEM_X_CONTROL ,
      width   => 16)
    port map (
      clk            => clk,
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    =>     data_vme_in ,
      data_vme_out   =>     data_vme_from_below (6),
      bus_drive      =>     bus_drive_from_below (6),
      data_from_vme  => data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL,
      data_to_vme    => data_to_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL,
      read_detect    => read_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL,
      write_detect   => write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL);
  

  vme_outreg_REG_RO_INPUT_SPY_MEM_X_STATUS: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_INPUT_SPY_MEM_X_STATUS ,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme   =>     data_vme_from_below(7),
      bus_drive      =>     bus_drive_from_below (7),
      data_to_vme  => data_to_vme_REG_RO_INPUT_SPY_MEM_X_STATUS);
      --read_detect => read_detect_REG_RO_INPUT_SPY_MEM_X_STATUS);


  --klm edit out --we always write/read in the same order
  --global_addr_counter_next<=global_addr_counter+1;

  --interpretation of portions of VME registers and connection to output ports
  data_to_vme_REG_RO_INPUT_SPY_MEM_X_STATUS<=status_summary&std_logic_vector(global_addr_counter(11 downto 0));
  mem_select_address<=std_logic_vector(global_addr_counter(11 downto 8));
  addra<=std_logic_vector(global_addr_counter(7 downto 0));
  
  mode_control<=data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL(3 downto 0);
  op_request<=data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL(4);
  rw_request<=data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL(5);

  --for the control register data to read is simply the data written 
  data_to_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL<=data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL;
  
  --data to/from vme is connected to data from/to RAM
  dina_sig<=data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(5) & data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(4) &
         data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(3) & data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(2) &
         data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(1) & data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD(0);
  --data_to_vme... was constructed in the generate loop above
  
  --update state on clock edge
  process (clk)
  begin  -- process
    if rising_edge(clk) then
      --if state_next=s_writing_ram or (state_next=s_wait_for_vme_read and state_reg=s_reading_ram) then
      --  if global_addr_counter=to_unsigned(256*numactchan,13) then
      --    global_addr_counter<=to_unsigned(0,13);
      --  else
      --    global_addr_counter<=global_addr_counter_next;
      --  end if;
      --else
      --  global_addr_counter<=global_addr_counter;--to_unsigned(0,13);
      --end if;
      state_reg<=state_next;
      -- start klm mod
      global_addr_counter<=global_addr_counter_next;
    end if;
  end process;


  --next state logic
  process (state_reg,op_request,rw_request,write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL,read_detect_REG_RW_INPUT_SPY_MEM_X_WORD(5),write_detect_REG_RW_INPUT_SPY_MEM_X_WORD(5),global_addr_counter)
  begin
    -- default values
    global_addr_counter_next<=to_unsigned(0,13);
    port_b_master_inhibit_sig<='0';
    ena_sig<='0';
    wea_sig<='0';
    --addra<=(others=>'0');
    --global_addr_counter<=(others=>'0');
    status_summary<=(others=>'0');
    
    case state_reg is
      when s_standby =>
        status_summary<=CONST_DPR_STATUS_NORMAL&'0';
        port_b_master_inhibit_sig<='0';
        if ( write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL='1' and op_request='1') then
          state_next<=s_inhibit_init;
          port_b_master_inhibit_sig<='1';
        else
          state_next<=s_standby;
        end if;
      when s_inhibit_init =>
        port_b_master_inhibit_sig<='1';
        status_summary<=CONST_DPR_STATUS_WAIT_INHIBIT&'0';
        if ( rw_request='1') then
          state_next<=s_wait_for_vme_write;
        else
          state_next<=s_reading_ram;                                      
        end if;
      when s_wait_for_vme_write =>
        port_b_master_inhibit_sig<='1';
        status_summary<=CONST_DPR_STATUS_WRITE&'0';
        if(write_detect_REG_RW_INPUT_SPY_MEM_X_WORD(5)='1') then
          state_next<=s_writing_ram;
          global_addr_counter_next<=global_addr_counter+1;  --end klm edit
          ena_sig<='1';
          wea_sig<='1';
        else
          state_next<=s_wait_for_vme_write;
          global_addr_counter_next<=global_addr_counter;
        end if;
      when s_writing_ram =>
        port_b_master_inhibit_sig<='1';
        status_summary<=CONST_DPR_STATUS_WAIT_WRITE&'0';
        if global_addr_counter=to_unsigned(256*numactchan,13) then
          global_addr_counter_next<=to_unsigned(0,13);
          state_next<=s_standby;
        else
          state_next<=s_wait_for_vme_write;
          global_addr_counter_next<=global_addr_counter;
        end if;
      when s_reading_ram =>
        port_b_master_inhibit_sig<='1';
        status_summary<=CONST_DPR_STATUS_WAIT_READ&'0';
        ena_sig<='1';
        global_addr_counter_next<=global_addr_counter;
        state_next<=s_wait_for_vme_read;
      when s_wait_for_vme_read =>
        port_b_master_inhibit_sig<='1';
        status_summary<=CONST_DPR_STATUS_READ&'0';
        if read_detect_REG_RW_INPUT_SPY_MEM_X_WORD(5)='1' then
          if global_addr_counter=to_unsigned(256*numactchan-1,13) then
            state_next<=s_standby;
          else
            global_addr_counter_next<=global_addr_counter+1;
            state_next<=s_reading_ram;
          end if;
        else
          global_addr_counter_next<=global_addr_counter;
          state_next<=s_wait_for_vme_read;
        end if;
      when others =>
        state_next<=s_standby;
    end case;
    
  end process;

--  --Moore output
--  process (state_reg)
--  begin
--    counter_enable<='0';
--    case state_reg is
--      when s_counter_running =>
--        counter_enable<='1';
--      when s_counter_stopped =>
--        counter_enable<='0';
--      when others => null;
--    end case;
--  end process;
--


  --chipscope_ila_CMX_input_module_spy_mem_control_FSM_inst: chipscope_ila_CMX_input_module_spy_mem_control_FSM
  --  port map (
  --    CONTROL => CONTROL0,
  --    CLK     => clk,
  --    DATA    => DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM,
  --    TRIG0   => TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM);
  --
  --
  --chipscope_icon_u2_c1_inst: chipscope_icon_u2_c1
  --  port map (
  --    CONTROL0 => CONTROL0);
  --
  --TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM(0)<=op_request;
  --TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM(1)<=rw_request;
  --TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM(2)<=write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL;  
  --TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM(8 downto 3)<=read_detect_REG_RW_INPUT_SPY_MEM_X_WORD;
  --TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM(14 downto 9)<=write_detect_REG_RW_INPUT_SPY_MEM_X_WORD;
  --TRIG0_chipscope_ila_CMX_input_module_spy_mem_control_FSM(15)<=ds;
  --
  --
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(0)<=op_request;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(1)<=rw_request;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(2)<=write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL;  
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(8 downto 3)<=read_detect_REG_RW_INPUT_SPY_MEM_X_WORD;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(14 downto 9)<=write_detect_REG_RW_INPUT_SPY_MEM_X_WORD;    
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(27 downto 15)<=std_logic_vector(global_addr_counter);
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(31 downto 28)<=status_summary;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(32)<=ena_sig;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(33)<=wea_sig;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(129 downto 34)<=douta;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(225 downto 130)<=dina_sig;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(226)<=ds;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(227)<=rd_nwr;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(243 downto 228)<=addr_vme;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(259 downto 244)<=data_vme;
  --DATA_chipscope_ila_CMX_input_module_spy_mem_control_FSM(260)<=port_b_master_inhibit_sig;
  
  
  
  
  
    
end multi_seg;