multi_seg Architecture Reference

Processes
PROCESS_43	( clk )
PROCESS_44	( state_reg , op_request , rw_request , write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL , read_detect_REG_RW_INPUT_SPY_MEM_X_WORD ( 5 ) , write_detect_REG_RW_INPUT_SPY_MEM_X_WORD ( 5 ) , global_addr_counter )

Components
vme_local_switch	<Entity vme_local_switch>
vme_outreg_notri	<Entity vme_outreg_notri>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>

Types
state_spy_mem_control_type	( s_standby , s_inhibit_init , s_wait_for_vme_write , s_writing_ram , s_reading_ram , s_wait_for_vme_read )

Signals
state_reg	state_spy_mem_control_type
state_next	state_spy_mem_control_type
wea_sig	std_logic
ena_sig	std_logic
dina_sig	std_logic_vector ( 95 downto 0 )
data_vme_from_below	arr_16 ( 7 downto 0 )
bus_drive_from_below	std_logic_vector ( 7 downto 0 )
data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD	arr_16 ( 5 downto 0 )
data_to_vme_REG_RW_INPUT_SPY_MEM_X_WORD	arr_16 ( 5 downto 0 )
read_detect_REG_RW_INPUT_SPY_MEM_X_WORD	std_logic_vector ( 5 downto 0 )
write_detect_REG_RW_INPUT_SPY_MEM_X_WORD	std_logic_vector ( 5 downto 0 )
data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL	std_logic_vector ( 15 downto 0 )
read_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL	std_logic
write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL	std_logic
data_to_vme_REG_RO_INPUT_SPY_MEM_X_STATUS	std_logic_vector ( 15 downto 0 )
status_summary	std_logic_vector ( 3 downto 0 )
global_addr_counter	unsigned ( 12 downto 0 )
global_addr_counter_next	unsigned ( 12 downto 0 )
inhibit_init_counter	unsigned ( 0 downto 0 )
op_request	std_logic
rw_request	std_logic
port_b_master_inhibit_sig	std_logic

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_inreg_reg_rw_input_spy_mem_x_word	vme_inreg_notri <Entity vme_inreg_notri>
vme_inreg_reg_rw_input_spy_mem_x_control	vme_inreg_notri <Entity vme_inreg_notri>
vme_outreg_reg_ro_input_spy_mem_x_status	vme_outreg_notri_async <Entity vme_outreg_notri_async>

Detailed Description

Definition at line 61 of file CMX_input_module_spy_mem_control_FSM.vhd.

Member Function Documentation

PROCESS_43

(

clk

)

Definition at line 358 of file CMX_input_module_spy_mem_control_FSM.vhd.

PROCESS_44 (   state_reg ,   op_request ,   rw_request ,   write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL ,   read_detect_REG_RW_INPUT_SPY_MEM_X_WORD ( 5 ) ,   write_detect_REG_RW_INPUT_SPY_MEM_X_WORD ( 5 ) ,   global_addr_counter   )

Process

Definition at line 378 of file CMX_input_module_spy_mem_control_FSM.vhd.

Member Data Documentation

bus_drive_from_below std_logic_vector ( 7 downto 0 )

Signal

Definition at line 99 of file CMX_input_module_spy_mem_control_FSM.vhd.

data_from_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL std_logic_vector ( 15 downto 0 )

Signal

Definition at line 209 of file CMX_input_module_spy_mem_control_FSM.vhd.

data_from_vme_REG_RW_INPUT_SPY_MEM_X_WORD arr_16 ( 5 downto 0 )

Signal

Definition at line 203 of file CMX_input_module_spy_mem_control_FSM.vhd.

data_to_vme_REG_RO_INPUT_SPY_MEM_X_STATUS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 214 of file CMX_input_module_spy_mem_control_FSM.vhd.

data_to_vme_REG_RW_INPUT_SPY_MEM_X_CONTROL std_logic_vector ( 15 downto 0 )

Signal

Definition at line 210 of file CMX_input_module_spy_mem_control_FSM.vhd.

data_to_vme_REG_RW_INPUT_SPY_MEM_X_WORD arr_16 ( 5 downto 0 )

Signal

Definition at line 204 of file CMX_input_module_spy_mem_control_FSM.vhd.

data_vme_from_below arr_16 ( 7 downto 0 )

Signal

Definition at line 98 of file CMX_input_module_spy_mem_control_FSM.vhd.

dina_sig std_logic_vector ( 95 downto 0 )

Signal

Definition at line 86 of file CMX_input_module_spy_mem_control_FSM.vhd.

ena_sig std_logic

Signal

Definition at line 85 of file CMX_input_module_spy_mem_control_FSM.vhd.

global_addr_counter unsigned ( 12 downto 0 )

Signal

Definition at line 220 of file CMX_input_module_spy_mem_control_FSM.vhd.

global_addr_counter_next unsigned ( 12 downto 0 )

Signal

Definition at line 226 of file CMX_input_module_spy_mem_control_FSM.vhd.

inhibit_init_counter unsigned ( 0 downto 0 )

Signal

Definition at line 228 of file CMX_input_module_spy_mem_control_FSM.vhd.

op_request std_logic

Signal

Definition at line 230 of file CMX_input_module_spy_mem_control_FSM.vhd.

port_b_master_inhibit_sig std_logic

Signal

Definition at line 235 of file CMX_input_module_spy_mem_control_FSM.vhd.

read_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL std_logic

Signal

Definition at line 211 of file CMX_input_module_spy_mem_control_FSM.vhd.

read_detect_REG_RW_INPUT_SPY_MEM_X_WORD std_logic_vector ( 5 downto 0 )

Signal

Definition at line 205 of file CMX_input_module_spy_mem_control_FSM.vhd.

rw_request std_logic

Signal

Definition at line 232 of file CMX_input_module_spy_mem_control_FSM.vhd.

state_next state_spy_mem_control_type

Signal

Definition at line 83 of file CMX_input_module_spy_mem_control_FSM.vhd.

state_reg state_spy_mem_control_type

Signal

Definition at line 83 of file CMX_input_module_spy_mem_control_FSM.vhd.

state_spy_mem_control_type ( s_standby , s_inhibit_init , s_wait_for_vme_write , s_writing_ram , s_reading_ram , s_wait_for_vme_read )

Type

Definition at line 64 of file CMX_input_module_spy_mem_control_FSM.vhd.

status_summary std_logic_vector ( 3 downto 0 )

Signal

Definition at line 217 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_inreg_notri

Component

Definition at line 133 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_inreg_notri_async

Component

Definition at line 152 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_inreg_reg_rw_input_spy_mem_x_control vme_inreg_notri

Instantiation

Definition at line 302 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_inreg_reg_rw_input_spy_mem_x_word vme_inreg_notri

Instantiation

Definition at line 278 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_local_switch

Component

Definition at line 89 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_local_switch_inst vme_local_switch

Instantiation

Definition at line 263 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_outreg_notri

Component

Definition at line 102 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_outreg_notri_async

Component

Definition at line 118 of file CMX_input_module_spy_mem_control_FSM.vhd.

vme_outreg_reg_ro_input_spy_mem_x_status vme_outreg_notri_async

Instantiation

Definition at line 321 of file CMX_input_module_spy_mem_control_FSM.vhd.

wea_sig std_logic

Signal

Definition at line 85 of file CMX_input_module_spy_mem_control_FSM.vhd.

write_detect_REG_RW_INPUT_SPY_MEM_X_CONTROL std_logic

Signal

Definition at line 212 of file CMX_input_module_spy_mem_control_FSM.vhd.

write_detect_REG_RW_INPUT_SPY_MEM_X_WORD std_logic_vector ( 5 downto 0 )

Signal

Definition at line 206 of file CMX_input_module_spy_mem_control_FSM.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_input_module_spy_mem_control_FSM.vhd