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CMX_input_module.vhd
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1 ----------------------------------------------------------------------------------
13 ----------------------------------------------------------------------------------
14 library IEEE;
15 use IEEE.STD_LOGIC_1164.ALL;
16 use IEEE.NUMERIC_STD.ALL;
17 
18 library UNISIM;
19 use UNISIM.VComponents.all;
20 
21 library work;
22 use work.CMXpackage.all;
23 use work.CMX_VME_defs.all;
24 
25 entity CMX_input_module is
26  port (
27  P : in mat_var (numactchan-1 downto 0);
28  buf_clk40 : in std_logic; -- global 40 MHz clock
29  buf_clk40_m180o : in std_logic; -- same inverted
30  buf_clk200 : in std_logic; -- global 200 MHz clock for iodelay calibration
31  pll_locked : in std_logic; -- is the main MMCM locked?
32 
33  ODATA : out arr_4Xword (numactchan-1 downto 0); -- 96 bit buses
34  -- at 40MHz
35  ODATA_first_half : out arr_2Xword(numactchan -1 downto 0); --
36 
37  --signals parity error on any of the inputs; comes out one tick later than
38  --'physics' data
39  PAR_ERROR_total : out std_logic;
40 
41  counter_enable_out: out std_logic_vector(numactchan-1 downto 0);
42  counter_values: out std_logic_vector(numactchan-1 downto 0);
43 
44  del_register: in del_register_type;
45  upload_delays: in std_logic;
46 
47  --auto quiet in case of parity error
48  quiet : in std_logic;
49 
50  --BC reset
51  start_playback : in std_logic;
52 
53  --inhibit signal for writing to the spy memories
54  spy_write_inhibit : in std_logic;
55 
56  --VME control:
57  ncs : in std_logic;
58  rd_nwr : in std_logic;
59  ds : in std_logic;
60  addr_vme : in std_logic_vector (15 downto 0);
61  data_vme_in : in std_logic_vector (15 downto 0);
62  data_vme_out : out std_logic_vector (15 downto 0);
63  bus_drive : out std_logic
64  );
65 
66 end CMX_input_module;
67 
68 architecture Behavioral of CMX_input_module is
69 
70 
71  signal DATA24: arr_word (numactchan-1 downto 0); -- 24 bit data for
72  -- 16 channels each
73  signal DELAYED_DATA24 : arr_word (numactchan-1 downto 0); -- data after delay
74  signal DELAYED_DATA24_reg : arr_word (numactchan-1 downto 0); -- input
75  -- register to
76  -- be packed
77  -- into IOB
78 
79  signal ODATA_sig : arr_4Xword (numactchan-1 downto 0); -- 96 bit
80  -- buses
81  -- (after masking)
82  signal ODATA_unmasked_sig : arr_4Xword (numactchan-1 downto 0); -- 96 bit buses
83  signal ODATA_sig_r_SYSTEM : arr_4Xword (numactchan-1 downto 0); --same but
84  --registered with system
85  --clock for comparison
86  --with captured data
87  signal ODATA_sig_rr_SYSTEM : arr_4Xword (numactchan-1 downto 0); --same but
88 
89  signal ODATA_first_half_sig : arr_2Xword (numactchan-1 downto 0); --first 48
90  --bits
91  --(after masking)
92  signal ODATA_first_half_unmasked_sig : arr_2Xword (numactchan-1 downto 0);
93 
94  --first half of the data registered on the inverted clock
95  signal ODATA_first_half_sig_r_mSYSTEM : arr_2Xword(numactchan-1 downto 0);
96 
97  signal ch_quiet : std_logic_vector(numactchan-1 downto 0);
98 
99  signal PAR_ERROR_sig : std_logic_vector(numactchan-1 downto 0); --this is
100  --after masking
101  signal PAR_ERROR_sig_r_SYSTEM_ORed : std_logic;
102 
103  signal PAR_ERROR_unmasked_sig : std_logic_vector(numactchan-1 downto 0);
104  signal PAR_ERROR_sig_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
105  signal PAR_ERROR_sig_rr_SYSTEM : std_logic_vector(numactchan-1 downto 0);
106 
107 
108  signal event_counter : unsigned(31 downto 0);
109  signal event_counter_s : signed(31 downto 0);
110  signal event_counter_next : unsigned(31 downto 0);
111 
112 
113  signal par_err_counter : arr_ctr_32bit(numactchan-1 downto 0);
114  signal par_err_counter_next : arr_ctr_32bit(numactchan-1 downto 0);
115 
116  signal backplane_events_counter : arr_ctr_32bit(numactchan-1 downto 0);
117  signal backplane_events_counter_s : arr_sig_32bit(numactchan-1 downto 0);
118  signal backplane_events_counter_next : arr_ctr_32bit(numactchan-1 downto 0);
119 
120  signal clock_diff_counter : arr_sig_32bit(numactchan-1 downto 0);
121  signal clock_diff_duration_counter : arr_ctr_32bit(numactchan-1 downto 0);
122  signal clock_diff_counter_ratchet_up : arr_sig_32bit(numactchan-1 downto 0);
123  signal clock_diff_counter_ratchet_down : arr_sig_32bit(numactchan-1 downto 0);
124 
125  signal counter_reset, counter_reset_unstretched: std_logic;
126  component Stretch_10 is
127  port (
128  unstretched_IN : in std_logic;
129  stretched_OUT : out std_logic;
130  clk : in std_logic);
131  end component Stretch_10;
132 
133  signal counter_reset_r_SYSTEM,counter_reset_rr_SYSTEM,counter_reset_rr_SYSTEM_r_SOURCE,counter_reset_rr_SYSTEM_rr_SOURCE: std_logic_vector(numactchan-1 downto 0);
134 
135  --component vme_outreg
136  -- generic (
137  -- ia_vme : integer;
138  -- width : integer);
139  -- port (
140  -- clk : in std_logic;
141  -- addr_vme : in std_logic_vector (15 downto 0);
142  -- ncs : in std_logic;
143  -- rd_nwr : in std_logic;
144  -- ds : in std_logic;
145  -- data_to_vme : in std_logic_vector (width-1 downto 0);
146  -- read_detect : out std_logic;
147  -- data_vme : out std_logic_vector (15 downto 0));
148  --end component;
149  --
150  --component vme_outreg_notri is
151  -- generic (
152  -- ia_vme : integer;
153  -- width : integer);
154  -- port (
155  -- clk : in std_logic;
156  -- ncs : in std_logic;
157  -- rd_nwr : in std_logic;
158  -- ds : in std_logic;
159  -- addr_vme : in std_logic_vector (15 downto 0);
160  -- data_vme : out std_logic_vector (15 downto 0);
161  -- bus_drive : out std_logic;
162  -- data_to_vme : in std_logic_vector (width-1 downto 0);
163  -- read_detect : out std_logic);
164  --end component vme_outreg_notri;
165 
166  component vme_outreg_notri_async is
167  generic (
168  ia_vme : integer;
169  width : integer);
170  port (
171  ncs : in std_logic;
172  rd_nwr : in std_logic;
173  ds : in std_logic;
174  addr_vme : in std_logic_vector (15 downto 0);
175  data_vme : out std_logic_vector (15 downto 0);
176  bus_drive : out std_logic;
177  data_to_vme : in std_logic_vector (width-1 downto 0));
178  end component vme_outreg_notri_async;
179 
180 
181  component vme_inreg_notri is
182  generic (
183  ia_vme : integer;
184  width : integer);
185  port (
186  clk : in std_logic;
187  ncs : in std_logic;
188  rd_nwr : in std_logic;
189  ds : in std_logic;
190  addr_vme : in std_logic_vector (15 downto 0);
191  data_vme_in : in std_logic_vector (15 downto 0);
192  data_vme_out : out std_logic_vector (15 downto 0);
193  bus_drive : out std_logic;
194  data_from_vme : out std_logic_vector (width-1 downto 0);
195  data_to_vme : in std_logic_vector (width-1 downto 0);
196  read_detect : out std_logic;
197  write_detect : out std_logic);
198  end component vme_inreg_notri;
199 
200  component vme_inreg_notri_async is
201  generic (
202  ia_vme : integer;
203  width : integer);
204  port (
205  ncs : in std_logic;
206  rd_nwr : in std_logic;
207  ds : in std_logic;
208  addr_vme : in std_logic_vector (15 downto 0);
209  data_vme_in : in std_logic_vector (15 downto 0);
210  data_vme_out : out std_logic_vector (15 downto 0);
211  bus_drive : out std_logic;
212  data_from_vme : out std_logic_vector (width-1 downto 0);
213  data_to_vme : in std_logic_vector (width-1 downto 0));
214  end component vme_inreg_notri_async;
215 
216  --component vme_inreg
217  -- generic (
218  -- ia_vme : integer;
219  -- width : integer);
220  -- port (
221  -- clk : in std_logic;
222  -- ncs : in std_logic;
223  -- rd_nwr : in std_logic;
224  -- ds : in std_logic;
225  -- data_from_vme : out std_logic_vector (width-1 downto 0);
226  -- data_to_vme : in std_logic_vector (width-1 downto 0);
227  -- addr_vme : in std_logic_vector (15 downto 0);
228  -- read_detect : out std_logic;
229  -- write_detect : out std_logic;
230  -- data_vme : inout std_logic_vector (15 downto 0));
231  --end component;
232 
233  signal data_from_vme_REG_RW_COUNTER_RESET : std_logic_vector (15 downto 0); --actual value is
234  --ignored but
235  --supplied for sw check
236  signal data_to_vme_REG_RW_COUNTER_RESET : std_logic_vector (15 downto 0);
237 
238  signal data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE : std_logic_vector (15 downto 0);
239 
240  --component vme_inreg_async
241  -- generic (
242  -- ia_vme : integer;
243  -- width : integer);
244  -- port (
245  -- ncs : in std_logic;
246  -- rd_nwr : in std_logic;
247  -- ds : in std_logic;
248  -- addr_vme : in std_logic_vector (15 downto 0);
249  -- data_vme : inout std_logic_vector (15 downto 0);
250  -- data_from_vme : out std_logic_vector (width-1 downto 0);
251  -- data_to_vme : in std_logic_vector (width-1 downto 0));
252  --end component;
253 
254  signal data_from_vme_REG_RW_INPUT_MOD_RESET : std_logic_vector(15 downto 0);
255  signal data_to_vme_REG_RW_INPUT_MOD_RESET : std_logic_vector(15 downto 0);
256 
257  signal data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK: std_logic_vector(15 downto 0);
258  signal data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK: std_logic_vector(15 downto 0);
259 
260  signal channel_mask : std_logic_vector(numactchan-1 downto 0);
261 
262  signal vme_reset_B : std_logic;
263 
264  signal any_reset_B : std_logic;
265 
266  --signal ODATA_reg40 : arr_4Xword (numactchan-1 downto 0); -- 96 bit buses
267  -- synced to
268  -- global 40
269  -- MHz clock
270  signal PDATA : arr_word (numactchan-1 downto 0); --DDR data
271  signal NDATA : arr_word (numactchan-1 downto 0);
272 
273  signal PDATA_r_SOURCE : arr_word (numactchan-1 downto 0); --DDR data
274  signal NDATA_r_SOURCE : arr_word (numactchan-1 downto 0);
275 
276 
277  signal CLKPAR: STD_LOGIC_VECTOR (numactchan-1 downto 0); -- 16 clock
278  -- lines with
279  -- encoded clock
280  -- parity bit
281  signal DELAYED_CLKPAR: STD_LOGIC_VECTOR (numactchan-1 downto 0); --after iodelay
282  signal CLKPARB: STD_LOGIC_VECTOR (numactchan-1 downto 0); -- same buffered
283  -- locally (BUFR)
284  -- or globally
285  signal CLKPAR_DATA: STD_LOGIC_VECTOR (numactchan-1 downto 0); --if buffering
286  --is local
287  --this is
288  --clkparb if
289  --global this
290  --is DELAYED...
291 
292 
293 
294 
295  signal i_pll_locked: std_logic;
296 
297 
298  signal counter_enable : std_logic_vector(numactchan - 1 downto 0);
299  signal any_reset_B_s1, any_reset_B_synced : std_logic_vector(numactchan-1 downto 0);
300  signal any_reset_B_synced_r_SOURCE, any_reset_B_synced_rr_SOURCE : std_logic_vector(numactchan-1 downto 0);
301 
302  signal cyclecounter : arr_ctr_1bit(numactchan - 1 downto 0);
303  signal cyclecounter_next : arr_ctr_1bit(numactchan - 1 downto 0);
304 
305  signal clock_detect_counter : arr_ctr_16bit(numactchan-1 downto 0);
306  signal clock_detect_counter_next : arr_ctr_16bit(numactchan-1 downto 0);
307 
308 
309  component CMX_data_delay
310  port (
311  DATA24: in arr_word (numactchan-1 downto 0);
312  CLKPAR: in std_logic_vector(numactchan - 1 downto 0);
313  REF_CLK_200: in std_logic;
314  REF_CLK_READY: in std_logic;
315  CLK_40: in std_logic;
316  del_register: in del_register_type; --input from VME holding 5 bit delay
317  --for every data and clkpar signal of
318  --every channel
319  upload_delays: in std_logic; --needs to be pulsed high for the
320  --upload of the registers into the
321  --iodelay instances
322 
323 
324  IDELAYCTRL_RDY: out std_logic_vector(num_IDELAYCTRL-1 downto 0);
325  DELAYED_DATA24: out arr_word (numactchan-1 downto 0);
326  DELAYED_CLKPAR: out std_logic_vector(numactchan - 1 downto 0);
327  --VME control:
328  ncs : in std_logic;
329  rd_nwr : in std_logic;
330  ds : in std_logic;
331  addr_vme : in std_logic_vector (15 downto 0);
332  data_vme_in : in std_logic_vector (15 downto 0);
333  data_vme_out : out std_logic_vector (15 downto 0);
334  bus_drive : out std_logic
335  );
336  end component;
337 
338 
339 
340 
341  component BUF_2X24_AT_80_TO_1X96_AT_40
342  port (
343  PDATA, NDATA : in std_logic_vector(numbitsinchan - 1 downto 0);
344  ODATA : out std_logic_vector((numbitsinchan*4)-1 downto 0);
345  ODATA_first_half : out std_logic_vector((numbitsinchan*2)-1 downto 0);
346  clk80 : in std_logic;
347  cyclecounter : in unsigned(0 downto 0);
348  counter_enable : in std_logic;
349  PAR_ERROR : out std_logic);
350  end component;
351 
352  --component CMX_input_module_state_FSM
353  -- port (
354  -- clk, rst : in std_logic;
355  -- pdata, ndata : in std_logic_vector(numbitsinchan-1 downto 0);
356  -- counter_enable: out std_logic);
357  --end component;
358 
359  component DEBOUNCE_10
360  port (
361  SWITCH_IN : in std_logic;
362  SWITCH_OUT : out std_logic;
363  clk : in std_logic);
364  end component;
365 
366 
367 
368 
369  --memory controller
370  component CMX_generic_spy_mem_control_FSM is
371  generic (
372  ADDR_REG_RW_GENERIC_SPY_MEM_WORD : integer;
373  ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL : integer;
374  ADDR_REG_RO_GENERIC_SPY_MEM_STATUS : integer;
375  num_external_RAMS : positive);
376  port (
377  clk : in std_logic;
378  ncs : in std_logic;
379  rd_nwr : in std_logic;
380  ds : in std_logic;
381  addr_vme : in std_logic_vector (15 downto 0);
382  data_vme_in : in std_logic_vector (15 downto 0);
383  data_vme_out : out std_logic_vector (15 downto 0);
384  bus_drive : out std_logic;
385  mode_control : out std_logic_vector(3 downto 0);
386  ena : out std_logic;
387  wea : out std_logic;
388  addra : out std_logic_vector(7 DOWNTO 0);
389  mem_select_address : out std_logic_vector(addr_port_width(num_external_RAMS)-1 downto 0);
390  dina : out std_logic_vector;
391  douta : in std_logic_vector;
392  port_b_master_inhibit : out std_logic);
393  end component CMX_generic_spy_mem_control_FSM;
394  --component CMX_input_module_spy_mem_control_FSM
395  -- generic (
396  -- ADDR_REG_RW_INPUT_SPY_MEM_X_WORD : integer;
397  -- ADDR_REG_RW_INPUT_SPY_MEM_X_CONTROL : integer;
398  -- ADDR_REG_RO_INPUT_SPY_MEM_X_STATUS : integer);
399  -- port (
400  -- clk : in std_logic;
401  -- ncs : in std_logic;
402  -- rd_nwr : in std_logic;
403  -- ds : in std_logic;
404  -- addr_vme : in std_logic_vector (15 downto 0);
405  -- data_vme_in : in std_logic_vector (15 downto 0);
406  -- data_vme_out : out std_logic_vector (15 downto 0);
407  -- bus_drive : out std_logic;
408  -- mode_control : out std_logic_vector(3 downto 0);
409  -- ena : out std_logic;
410  -- wea : out std_logic;
411  -- addra : out std_logic_vector(7 DOWNTO 0);
412  -- mem_select_address : out std_logic_vector(3 downto 0);
413  -- dina : out std_logic_vector(95 DOWNTO 0);
414  -- douta : in std_logic_vector(95 DOWNTO 0);
415  -- port_b_master_inhibit : out std_logic);
416  --end component;
417 
418 
419 
420  --signals for the source spy memory controllers
421  signal mode_control_SPY_SOURCE : std_logic_vector(3 downto 0);
422  signal ena_SPY_SOURCE : std_logic;
423  signal wea_SPY_SOURCE : std_logic;
424  signal addra_SPY_SOURCE : std_logic_vector(7 DOWNTO 0);
425  signal mem_select_address_SPY_SOURCE : std_logic_vector(3 downto 0);
426  signal dina_SPY_SOURCE : std_logic_vector(95 DOWNTO 0);
427  signal douta_SPY_SOURCE : std_logic_vector(95 DOWNTO 0);
428  signal port_b_master_inhibit_SPY_SOURCE : std_logic;
429 
430  signal port_b_master_inhibit_SPY_SOURCE_split : std_logic_vector(numactchan-1 downto 0);
431  signal port_b_master_inhibit_SPY_SOURCE_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
432  signal port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE : std_logic_vector(numactchan-1 downto 0);
433  signal port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE : std_logic_vector(numactchan-1 downto 0);
434 
435 
436  --Xilinx IP DPR (BRAM) with port widths configured correctly for the source
437  --side (80 Mbps) memories
438  component blk_mem_A8x96_B9x48
439  port (
440  clka : IN STD_LOGIC;
441  ena : IN STD_LOGIC;
442  wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
443  addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
444  dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
445  douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
446  clkb : IN STD_LOGIC;
447  enb : IN STD_LOGIC;
448  web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
449  addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
450  dinb : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
451  doutb : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
452  end component;
453 
454  --signals for individual source spy memories
455  signal ena_SPY_SOURCE_individual : std_logic_vector(numactchan-1 downto 0);
456  signal wea_SPY_SOURCE_individual : arr_1(numactchan-1 downto 0);
457 
458 
459  signal douta_SPY_SOURCE_individual : arr_96(numactchan-1 downto 0);
460  signal clkb_SPY_SOURCE_individual : std_logic_vector(numactchan-1 downto 0);
461 
462  --these are a function of the mode control word
463  signal enb_SPY_SOURCE : STD_LOGIC;
464  signal web_SPY_SOURCE : STD_LOGIC;
465 
466  --registered in the source domain to aid timing
467  signal enb_SPY_SOURCE_split : std_logic_vector(numactchan-1 downto 0);
468  signal enb_SPY_SOURCE_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
469  signal enb_SPY_SOURCE_rr_SYSTEM : std_logic_vector(numactchan-1 downto 0);
470  signal enb_SPY_SOURCE_r_SOURCE : std_logic_vector(numactchan-1 downto 0);
471  signal enb_SPY_SOURCE_rr_SOURCE : std_logic_vector(numactchan-1 downto 0);
472 
473  signal web_SPY_SOURCE_split : std_logic_vector(numactchan-1 downto 0);
474  signal web_SPY_SOURCE_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
475  signal web_SPY_SOURCE_rr_SYSTEM : std_logic_vector(numactchan-1 downto 0);
476  signal web_SPY_SOURCE_r_SOURCE : std_logic_vector(numactchan-1 downto 0);
477  signal web_SPY_SOURCE_rr_SOURCE : std_logic_vector(numactchan-1 downto 0);
478 
479 
480  signal spy_write_inhibit_r_SYSTEM_r_SOURCE : std_logic_vector(numactchan-1 downto 0);
481  signal spy_write_inhibit_r_SYSTEM_rr_SOURCE : std_logic_vector(numactchan-1 downto 0);
482 
483 
484  --these are a function of the mode control word
485  signal enb_SPY_SOURCE_individual : std_logic_vector(numactchan-1 downto 0);
486  signal web_SPY_SOURCE_individual : arr_1(numactchan-1 downto 0);
487 
488 
489 
490  --and these individual again
491  signal addrb_SPY_SOURCE_individual : arr_9(numactchan-1 downto 0);
492  signal dinb_SPY_SOURCE_individual : arr_48(numactchan-1 downto 0);
493  signal doutb_SPY_SOURCE_individual : arr_48(numactchan-1 downto 0);
494 
495  --signal doutb_SPY_SOURCE_individual_r_SOURCE : arr_48(numactchan-1 downto 0);
496 
497  signal addrb_SPY_SOURCE_counter: arr_ctr_9bit(numactchan-1 downto 0);
498 
499 
500  --double registered reset signal in the source clock domain to avoid metastability
501  signal start_playback_r_SYSTEM_r_SOURCE: std_logic_vector(numactchan-1 downto 0);
502  signal start_playback_r_SYSTEM_rr_SOURCE: std_logic_vector(numactchan-1 downto 0);
503 
504  signal data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS: arr_16(numactchan-1 downto 0);
505  signal data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS: arr_16(numactchan-1 downto 0);
506 
507 
508  --signals for the system spy memory controllers
509  signal mode_control_SPY_SYSTEM : std_logic_vector(3 downto 0);
510  signal ena_SPY_SYSTEM : std_logic;
511  signal wea_SPY_SYSTEM : std_logic;
512  signal addra_SPY_SYSTEM : std_logic_vector(7 DOWNTO 0);
513  signal mem_select_address_SPY_SYSTEM : std_logic_vector(3 downto 0);
514  signal dina_SPY_SYSTEM : std_logic_vector(95 DOWNTO 0);
515  signal douta_SPY_SYSTEM : std_logic_vector(95 DOWNTO 0);
516  signal port_b_master_inhibit_SPY_SYSTEM : std_logic;
517 
518  signal port_b_master_inhibit_SPY_SYSTEM_split : std_logic_vector(numactchan-1 downto 0);
519  signal port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
520 
521 
522  component blk_mem_A8x96_B8x96 is
523  port (
524  clka : IN STD_LOGIC;
525  ena : IN STD_LOGIC;
526  wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
527  addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
528  dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
529  douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
530  clkb : IN STD_LOGIC;
531  enb : IN STD_LOGIC;
532  web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
533  addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
534  dinb : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
535  doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0));
536  end component blk_mem_A8x96_B8x96;
537 
538 
539 
540  --signals for individual system spy memories
541  signal ena_SPY_SYSTEM_individual : std_logic_vector(numactchan-1 downto 0);
542  signal wea_SPY_SYSTEM_individual : arr_1(numactchan-1 downto 0);
543 
544 
545  signal douta_SPY_SYSTEM_individual : arr_96(numactchan-1 downto 0);
546  signal clkb_SPY_SYSTEM_individual : std_logic_vector(numactchan-1 downto 0);
547 
548  --these are a function of the mode control word
549  signal enb_SPY_SYSTEM : STD_LOGIC;
550  signal web_SPY_SYSTEM : STD_LOGIC;
551 
552  --registered in the system domain to aid timing
553  signal enb_SPY_SYSTEM_split : std_logic_vector(numactchan-1 downto 0);
554  signal enb_SPY_SYSTEM_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
555 
556  signal web_SPY_SYSTEM_split : std_logic_vector(numactchan-1 downto 0);
557  signal web_SPY_SYSTEM_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
558 
559  signal spy_write_inhibit_r_SYSTEM : std_logic_vector(numactchan-1 downto 0);
560  signal spy_write_inhibit_rr_SYSTEM : std_logic_vector(numactchan-1 downto 0);
561 
562  --these are a function of the mode control word
563  signal enb_SPY_SYSTEM_individual : std_logic_vector(numactchan-1 downto 0);
564  signal web_SPY_SYSTEM_individual : arr_1(numactchan-1 downto 0);
565 
566 
567 
568  --and these individual again
569  signal addrb_SPY_SYSTEM_individual : arr_8(numactchan-1 downto 0);
570  signal dinb_SPY_SYSTEM_individual : arr_96(numactchan-1 downto 0);
571  signal doutb_SPY_SYSTEM_individual : arr_4Xword(numactchan-1 downto 0);
572 
573  --WTF 20150204 push the mux before the last flip-flop
574  --signal doutb_SPY_SYSTEM_individual_r_SYSTEM : arr_4Xword(numactchan-1 downto 0);
575  --signal doutb_SPY_SYSTEM_individual_r_mSYSTEM : arr_4Xword(numactchan-1 downto 0);
576 
577  signal addrb_SPY_SYSTEM_counter: arr_ctr_8bit(numactchan-1 downto 0);
578 
579 
580  --registered locally to aid timing closure
581 
582  signal start_playback_r_SYSTEM: std_logic_vector(numactchan-1 downto 0);
583  signal start_playback_rr_SYSTEM: std_logic_vector(numactchan-1 downto 0);
584 
585 
586  signal data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS: std_logic_vector(15 downto 0);
587  signal data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS: std_logic_vector(15 downto 0);
588 
589 
590  --component chipscope_icon_u1_c1 is
591  -- port (
592  -- CONTROL0 : inout std_logic_vector(35 downto 0));
593  --end component chipscope_icon_u1_c1;
594  --signal CONTROL0 : std_logic_vector(35 downto 0);
595  --
596  --component chipscope_ila_inputmod_systemSPY_logic is
597  -- port (
598  -- CONTROL : inout std_logic_vector(35 downto 0);
599  -- CLK : in std_logic;
600  -- DATA : in std_logic_vector(490 downto 0);
601  -- TRIG0 : in std_logic_vector(27 downto 0));
602  --end component chipscope_ila_inputmod_systemSPY_logic;
603  --
604  --signal data_ila : std_logic_vector(490 downto 0);
605  --signal trig_ila : std_logic_vector(27 downto 0);
606 
607 -- component chipscope_icon_input_module_u3_c2
608 -- port (
609 -- CONTROL0 : inout std_logic_vector(35 downto 0);
610 -- CONTROL1 : inout std_logic_vector(35 downto 0));
611 -- end component;
612 --
613 -- signal CONTROLBUS : arr_36(numactchan-1 downto 0);
614 --
615 --
616 -- component chipscope_ila_input_module
617 -- port (
618 -- CONTROL : inout std_logic_vector(35 downto 0);
619 -- CLK : in std_logic;
620 -- DATA : in std_logic_vector(46 downto 0);
621 -- TRIG0 : in std_logic_vector(2 downto 0));
622 -- end component;
623 --
624 -- signal DATA_chipscope_ila_input_module : arr_47(numactchan-1 downto 0);
625 -- signal TRIG0_chipscope_ila_input_module : arr_3(numactchan-1 downto 0);
626 
627  --error checking signals for the source side spy memories
628  signal bit_error_detect: arr_48(numactchan-1 downto 0);
629  signal bit_error_latch: arr_24(numactchan-1 downto 0);
630 
631  signal bit_error_counter: arr_ctr_32bit(numactchan-1 downto 0);
632  signal bit_error_counter_next: arr_ctr_32bit(numactchan-1 downto 0);
633 
634  signal data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0 : arr_16(numactchan-1 downto 0);
635  signal data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1 : arr_16(numactchan-1 downto 0);
636 
637 
638  --error checking signals for the system side spy memories
639  signal bit_error_detect_system: arr_96(numactchan-1 downto 0);
640  signal bit_error_latch_system: arr_24(numactchan-1 downto 0);
641 
642  signal bit_error_counter_system: arr_ctr_32bit(numactchan-1 downto 0);
643  signal bit_error_counter_system_next: arr_ctr_32bit(numactchan-1 downto 0);
644 
645  signal data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0 : arr_16(numactchan-1 downto 0);
646  signal data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1 : arr_16(numactchan-1 downto 0);
647 
648  component or_all is
649  generic (
650  numbits : integer);
651  port (
652  DATA : in std_logic_vector(numbits - 1 downto 0);
653  or_all : out std_logic);
654  end component or_all;
655 
656  component vme_local_switch is
657  port (
658  data_vme_up : out std_logic_vector (15 downto 0);
659  data_vme_from_below : in arr_16;
660  bus_drive_up : out std_logic;
661  bus_drive_from_below : in std_logic_vector);
662  end component vme_local_switch;
663 
664 
665  signal data_vme_from_below : arr_16(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*numactchan-1 downto 0);
666  signal bus_drive_from_below : std_logic_vector(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*numactchan-1 downto 0);
667 
668 
669  attribute keep : string;
670  --prevent SRL
671  attribute keep of enb_SPY_SOURCE_r_SOURCE, web_SPY_SOURCE_r_SOURCE, enb_SPY_SOURCE_split, web_SPY_SOURCE_split, enb_SPY_SOURCE_rr_SOURCE, web_SPY_SOURCE_rr_SOURCE, enb_SPY_SOURCE_r_SYSTEM, web_SPY_SOURCE_r_SYSTEM, enb_SPY_SOURCE_rr_SYSTEM, web_SPY_SOURCE_rr_SYSTEM, port_b_master_inhibit_SPY_SOURCE_split, port_b_master_inhibit_SPY_SOURCE_r_SYSTEM, port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE, port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE,counter_reset_r_SYSTEM,counter_reset_rr_SYSTEM,counter_reset_rr_SYSTEM_r_SOURCE, any_reset_B_synced_r_SOURCE, any_reset_B_synced_rr_SOURCE, ODATA_sig_r_SYSTEM : signal is "TRUE";
672 
673 begin
674 
675 
676 -- chipscope_icon_input_module_u3_c2_inst: chipscope_icon_input_module_u3_c2
677 -- port map (
678 -- CONTROL0 => CONTROLBUS(0),
679 -- CONTROL1 => CONTROLBUS(1));
680 --
681 -- chipscope_ila_gen : for channel in 0 to numactchan - 1
682 -- generate
683 -- chipscope_ila_input_module_inst: chipscope_ila_input_module
684 -- port map (
685 -- CONTROL => CONTROLBUS(channel),
686 -- CLK => CLKPARB(channel),
687 -- DATA => DATA_chipscope_ila_input_module(channel),
688 -- TRIG0 => TRIG0_chipscope_ila_input_module(channel));
689 --
690 -- TRIG0_chipscope_ila_input_module(channel)(0)<=pll_locked;
691 -- TRIG0_chipscope_ila_input_module(channel)(1)<=counter_enable(channel);
692 -- TRIG0_chipscope_ila_input_module(channel)(2)<=PAR_ERROR_sig(channel);
693 --
694 -- DATA_chipscope_ila_input_module(channel)(0)<=pll_locked;
695 -- DATA_chipscope_ila_input_module(channel)(1)<=pll_locked_s1(channel);
696 -- DATA_chipscope_ila_input_module(channel)(2)<=counter_enable(channel);
697 -- DATA_chipscope_ila_input_module(channel)(3)<=PAR_ERROR_sig(channel);
698 -- DATA_chipscope_ila_input_module(channel)(4 downto 4)<=std_logic_vector(cyclecounter(channel));
699 -- DATA_chipscope_ila_input_module(channel)(11 downto 5)<=PDATA(channel);
700 -- DATA_chipscope_ila_input_module(channel)(18 downto 12)<=NDATA(channel);
701 -- DATA_chipscope_ila_input_module(channel)(46 downto 19)<=ODATA_sig(channel);
702 --
703 -- end generate chipscope_ila_gen;
704 --
705  --BUFG_inst : BUFG
706  -- port map (
707  -- O => buf_clk40_sig, -- 1-bit output: Clock buffer output
708  -- I => clk40 -- 1-bit input: Clock buffer input
709  -- );
710 
711  --buf_clk40<=buf_clk40_sig;
712 
713  --connect the 24 data bits of each 25 bit bundle to DATA24
714  --and the clock/parity lines
715 
716  i_pll_locked<= not pll_locked;
717 
718 
719  vme_local_switch_inst: entity work.vme_local_switch
720  port map (
721  data_vme_up => data_vme_out,
722  data_vme_from_below => data_vme_from_below,
723  bus_drive_up => bus_drive,
724  bus_drive_from_below => bus_drive_from_below);
725 
726  busgen : for channel in 0 to numactchan - 1
727  generate
728  --DATA24(channel)(23 downto 0) <= P(channel)(24 downto 1);
729  --CLKPAR(channel) <= P(channel)(0);
730  DATA24(channel)(numbitsinchan-1 downto 0) <= P(channel)(numbitsinchan-1 downto 0);
731  CLKPAR(channel) <= P(channel)(numbitsinchan);
732  end generate busgen;
733 
734 
735 
736  --delay module
737  --implements iodelay modules and calibration circuit
738  Inst_CMX_data_delay: CMX_data_delay
739  port map (
740  DATA24 => DATA24,
741  CLKPAR => CLKPAR,
742  REF_CLK_200 => buf_clk200,
743  REF_CLK_READY => pll_locked,
744  CLK_40 => buf_clk40,
745  del_register => del_register,
746  upload_delays => upload_delays,
747  IDELAYCTRL_RDY => open,
748  DELAYED_DATA24 => DELAYED_DATA24,
749  DELAYED_CLKPAR => DELAYED_CLKPAR,
750  ncs => ncs,
751  rd_nwr => rd_nwr,
752  ds => ds,
753  addr_vme => addr_vme,
754  data_vme_in => data_vme_in ,
755  data_vme_out => data_vme_from_below (0),
756  bus_drive => bus_drive_from_below (0)
757  );
758 
759 
760  --generate regional buffers for clock distribution
761  buf_gen: for channel in 0 to numactchan -1
762  generate
763  BUFR_inst : BUFR
764  generic map (
765  BUFR_DIVIDE => "BYPASS", -- Values: "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
766  SIM_DEVICE => "VIRTEX6" -- Must be set to "VIRTEX6"
767  )
768  port map (
769  O => CLKPARB(channel),
770  CE => '1',
771  CLR => '0',
772  I => DELAYED_CLKPAR(channel)
773  );
774 
775  end generate buf_gen;
776 
777 
778 
779 
780  --now connect to IDDR
781  iddrgen: for channel in numactchan - 1 downto 0 generate
782  bitgen: for bitnum in 0 to (numbitsinchan-1) generate
783 
784  IDDR_inst : IDDR
785  generic map (
786  DDR_CLK_EDGE => "OPPOSITE_EDGE", --"SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE", "SAME_EDGE"
787  -- or "SAME_EDGE_PIPELINED"
788  INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
789  INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
790  SRTYPE => "SYNC" ) -- Set/Reset type: "SYNC" or "ASYNC"
791  port map (
792  Q1 => PDATA(channel)(bitnum), -- 1-bit output for positive edge of clock
793  Q2 => NDATA(channel)(bitnum), -- 1-bit output for negative edge of clock
794  C => CLKPARB(channel), -- 1-bit clock input
795  CE => '1', -- 1-bit clock enable input
796  D => DELAYED_DATA24(channel)(bitnum), -- 1-bit DDR data input
797  R => i_pll_locked, -- 1-bit reset
798  S => '0' -- 1-bit set
799  );
800  end generate bitgen;
801  end generate iddrgen;
802 
803 
804  --now connect to the BUF2X24_AT80_TO_1X96_AT_40
805  --to get a 96 bit wide 40MHz bus of data
806  widebusgen: for channel in numactchan-1 downto 0 generate
807  BUF_INST: BUF_2X24_AT_80_TO_1X96_AT_40
808  port map (
809  PDATA => PDATA(channel),
810  NDATA => NDATA(channel),
811  ODATA => ODATA_unmasked_sig(channel),
812  ODATA_first_half => ODATA_first_half_unmasked_sig (channel),
813  PAR_ERROR => PAR_ERROR_unmasked_sig(channel),
814  clk80 => CLKPARB(channel),
815  cyclecounter =>cyclecounter(channel),
816  counter_enable =>counter_enable(channel)
817  );
818  PAR_ERROR_sig(channel)<=PAR_ERROR_unmasked_sig(channel) when channel_mask(channel)='0' else '0';
819  --PAR_ERROR(channel)<=PAR_ERROR_sig(channel);
820 
821  ch_quiet(channel)<= '1' when channel_mask(channel)='1' or (quiet='1' and PAR_ERROR_unmasked_sig(channel)='1') else '0';
822 
823  ODATA_sig(channel)<=ODATA_unmasked_sig(channel) when ch_quiet(channel)/='1' else x"800000800000800000800000";
824  ODATA_first_half_sig(channel)<=ODATA_first_half_unmasked_sig(channel) when ch_quiet(channel)/='1' else x"800000800000";
825 
826  --WTF 20150204 push the mux before the last flip-flop
827  --process(buf_clk40)
828  --begin
829  -- if rising_edge(buf_clk40) then
830  -- doutb_SPY_SYSTEM_individual_r_SYSTEM(channel)<=doutb_SPY_SYSTEM_individual(channel);
831  -- end if;
832  --end process;
833 
834  process(buf_clk40_m180o)
835  begin
836  if rising_edge(buf_clk40_m180o) then
837  --WTF 20150204 push the mux before the last flip-flop
838  if mode_control_SPY_SYSTEM /= CONST_DPR_CONTROL_PLAYBACK then
839  ODATA_first_half(channel)<=ODATA_first_half_sig(channel);
840  else
841  ODATA_first_half(channel)<=doutb_SPY_SYSTEM_individual(channel)(2*numbitsinchan-1 downto 0);
842  end if;
843  --WTF 20150204 push the mux before the last flip-flop
844  --doutb_SPY_SYSTEM_individual_r_mSYSTEM(channel)<=doutb_SPY_SYSTEM_individual(channel);
845  --ODATA_first_half_sig_r_mSYSTEM(channel)<=ODATA_first_half_sig(channel);
846  end if;
847  end process;
848 
849  --connect output signals
850  --WTF 20150204 push the mux before the last flip-flop
851  --PAR_ERROR_play(channel)<=PAR_ERROR_sig_r_SYSTEM(channel) when mode_control_SPY_SYSTEM /= CONST_DPR_CONTROL_PLAYBACK else '0';
852  --WTF 20150204 push the mux before the last flip-flop
853  --ODATA(channel)<=ODATA_sig_r_SYSTEM(channel) when mode_control_SPY_SYSTEM /= CONST_DPR_CONTROL_PLAYBACK else doutb_SPY_SYSTEM_individual_r_SYSTEM(channel);
854  --WTF 20150204 push the mux before the last flip-flop
855  --ODATA_first_half(channel)<=ODATA_first_half_sig_r_mSYSTEM(channel) when mode_control_SPY_SYSTEM /= CONST_DPR_CONTROL_PLAYBACK else doutb_SPY_SYSTEM_individual_r_mSYSTEM(channel)(2*numbitsinchan-1 downto 0);
856 
857 
858  end generate widebusgen;
859 
860 
861 
862  or_PAR: or_all
863  generic map(
864  numbits => numactchan)
865  port map (
866  DATA =>PAR_ERROR_sig_r_SYSTEM,
867  or_all =>PAR_ERROR_sig_r_SYSTEM_ORed
868  );
869 
870  --channel mask register
871  vme_inreg_async_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK: vme_inreg_notri_async
872  generic map (
873  ia_vme => ADDR_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK,
874  width => 16)
875  port map (
876  ncs => ncs,
877  rd_nwr => rd_nwr,
878  ds => ds,
879  addr_vme => addr_vme,
880  data_vme_in => data_vme_in ,
881  data_vme_out => data_vme_from_below (1),
882  bus_drive => bus_drive_from_below (1),
883  data_from_vme => data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK,
884  data_to_vme => data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK);
885 
886  data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK<=data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK;
887  channel_mask(numactchan-1 downto 0)<=data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK(numactchan-1 downto 0);
888 
889 
890  --generation of event and parity error counters
891 
892  vme_inreg_REG_RW_COUNTER_RESET: vme_inreg_notri
893  generic map (
894  ia_vme => ADDR_REG_RW_COUNTER_RESET ,
895  width => 16)
896  port map (
897  clk => buf_clk40 ,
898  ncs => ncs,
899  rd_nwr => rd_nwr,
900  ds => ds,
901  data_from_vme => data_from_vme_REG_RW_COUNTER_RESET,
902  data_to_vme => data_to_vme_REG_RW_COUNTER_RESET,
903  addr_vme => addr_vme,
904  read_detect => open,
905  write_detect => counter_reset_unstretched ,
906  data_vme_in => data_vme_in ,
907  data_vme_out => data_vme_from_below (2),
908  bus_drive => bus_drive_from_below (2));
909 
910  data_to_vme_REG_RW_COUNTER_RESET<=data_from_vme_REG_RW_COUNTER_RESET;
911 
912  Stretch_10_counter_reset : Stretch_10
913  port map (
914  unstretched_IN => counter_reset_unstretched ,
915  stretched_OUT => counter_reset,
916  clk => buf_clk40 );
917 
918  vme_outreg_REG_RO_EV_COUNTER_0: vme_outreg_notri_async
919  generic map (
920  ia_vme => ADDR_REG_RO_EV_COUNTER,
921  width => 16)
922  port map (
923  addr_vme => addr_vme,
924  ncs => ncs,
925  rd_nwr => rd_nwr,
926  ds => ds,
927  data_to_vme => std_logic_vector(event_counter(15 downto 0)),
928  data_vme => data_vme_from_below (3),
929  bus_drive => bus_drive_from_below (3)
930  );
931 
932  vme_outreg_REG_RO_EV_COUNTER_1: vme_outreg_notri_async
933  generic map (
934  ia_vme => ADDR_REG_RO_EV_COUNTER+2 ,
935  width => 16)
936  port map (
937  addr_vme => addr_vme,
938  ncs => ncs,
939  rd_nwr => rd_nwr,
940  ds => ds,
941  data_to_vme => std_logic_vector(event_counter(31 downto 16)),
942  data_vme => data_vme_from_below (4),
943  bus_drive => bus_drive_from_below (4)
944  );
945 
946 
947  event_counter_next<=event_counter+1;
948  process(buf_clk40)
949  begin
950  if rising_edge(buf_clk40) then
951  if counter_reset_rr_SYSTEM(0) /= '1' then
952  if event_counter /= max_ctr32 then
953  event_counter<=event_counter_next;
954  else
955  event_counter<=max_ctr32;
956  end if;
957  else
958  event_counter<=to_unsigned(0,32);
959  end if;
960  end if;
961  end process;
962 
963 
964  countergen: for channel in numactchan-1 downto 0 generate
965 
966  vme_outreg_REG_RO_PARITY_ERROR_COUNTER_0: vme_outreg_notri_async
967  generic map (
968  ia_vme => ADDR_REG_RO_PARITY_ERROR_COUNTER+4*channel,
969  width => 16)
970  port map (
971  addr_vme => addr_vme,
972  ncs => ncs,
973  rd_nwr => rd_nwr,
974  ds => ds,
975  data_to_vme => std_logic_vector(par_err_counter(channel)(15 downto 0)),
976  data_vme => data_vme_from_below(5+2*channel),
977  bus_drive => bus_drive_from_below (5+2*channel)
978  );
979 
980 
981  vme_outreg_REG_RO_PARITY_ERROR_COUNTER_1: vme_outreg_notri_async
982  generic map (
983  ia_vme => ADDR_REG_RO_PARITY_ERROR_COUNTER+4*channel+2,
984  width => 16)
985  port map (
986  addr_vme => addr_vme,
987  ncs => ncs,
988  rd_nwr => rd_nwr,
989  ds => ds,
990  data_to_vme => std_logic_vector(par_err_counter(channel)(31 downto 16)),
991  data_vme => data_vme_from_below(5+2*channel+1),
992  bus_drive => bus_drive_from_below (5+2*channel+1)
993  );
994 
995  par_err_counter_next(channel)<=par_err_counter(channel)+1;
996  process(buf_clk40)
997  begin
998  if rising_edge(buf_clk40) then
999 
1000  if counter_reset /= '1' then
1001  if par_err_counter(channel) /= max_ctr32 then
1002  if PAR_ERROR_sig_rr_SYSTEM(channel) = '1' then
1003  par_err_counter(channel)<=par_err_counter_next(channel);
1004  end if;
1005  else
1006  par_err_counter(channel)<=max_ctr32;
1007  end if;
1008  else
1009  par_err_counter(channel)<=to_unsigned(0,32);
1010  PAR_ERROR_sig_rr_SYSTEM(channel)<='0';
1011  --PAR_ERROR_sig_r_SYSTEM(channel)<='0';
1012  end if;
1013 
1014  PAR_ERROR_sig_rr_SYSTEM(channel)<=PAR_ERROR_sig_r_SYSTEM(channel);
1015  --PAR_ERROR_sig_r_SYSTEM(channel)<=PAR_ERROR_sig(channel);
1016 
1017  end if;
1018  end process;
1019 
1020  end generate countergen;
1021 
1022 
1023  --process (buf_clk40)
1024  --begin
1025  -- if rising_edge(buf_clk40) then
1026  -- ODATA_reg40<=ODATA_sig;
1027  -- end if;
1028  --end process;
1029 --
1030 -- word0gen: for channel in numactchan-1 downto 0 generate
1031 -- --ODATA_WORD0(channel)<=ODATA_reg40(channel)(4*numbitsinchan-1 downto 3*numbitsinchan);
1032 -- ODATA_WORD0(channel)<=ODATA_sig(channel)(4*numbitsinchan-1 downto 3*numbitsinchan);
1033 -- end generate word0gen;
1034 
1035  --ODATA<=ODATA_reg40;
1036  --ODATA<=ODATA_sig when mode_control_SPY_SYSTEM /= CONST_DPR_CONTROL_PLAYBACK else doutb_SPY_SYSTEM_individual;
1037 
1038 
1039 
1040 
1041 
1042 
1043  counter_enable_out<=counter_enable;
1044 
1045 
1046  vme_inreg_async_REG_RW_INPUT_MOD_RESET: vme_inreg_notri_async
1047  generic map (
1048  ia_vme => ADDR_REG_RW_INPUT_MOD_RESET ,
1049  width => 16)
1050  port map (
1051  ncs => ncs,
1052  rd_nwr => rd_nwr,
1053  ds => ds,
1054  addr_vme => addr_vme,
1055  data_vme_in => data_vme_in ,
1056  data_vme_out => data_vme_from_below (6+2*numactchan-1),
1057  bus_drive => bus_drive_from_below (6+2*numactchan-1),
1058  data_from_vme => data_from_vme_REG_RW_INPUT_MOD_RESET,
1059  data_to_vme => data_to_vme_REG_RW_INPUT_MOD_RESET);
1060 
1061 
1062 
1063  vme_reset_B<= not data_from_vme_REG_RW_INPUT_MOD_RESET(0);
1064 
1065  data_to_vme_REG_RW_INPUT_MOD_RESET<=data_from_vme_REG_RW_INPUT_MOD_RESET;
1066 
1067  any_reset_B<=pll_locked and vme_reset_B;
1068 
1069 
1070 
1071 
1072  vme_outreg_REG_RO_INPUT_MOD_COUNTER_ENABLE: vme_outreg_notri_async
1073  generic map (
1074  ia_vme => ADDR_REG_RO_INPUT_MOD_COUNTER_ENABLE,
1075  width => 16)
1076  port map (
1077  addr_vme => addr_vme,
1078  ncs => ncs,
1079  rd_nwr => rd_nwr,
1080  ds => ds,
1081  data_to_vme => data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE,
1082  data_vme => data_vme_from_below(7+2*numactchan-1),
1083  bus_drive => bus_drive_from_below (7+2*numactchan-1));
1084 
1085  data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE(numactchan-1 downto 0)<=counter_enable(numactchan-1 downto 0);
1086 
1087  gen_Pad_vme_COUNTER_ENABLE: if numactchan<16 generate
1088  data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE(15 downto numactchan)<=(others=>'0');
1089  end generate gen_Pad_vme_COUNTER_ENABLE;
1090 
1091  genCOUNTER: for channel in 0 to numactchan - 1 generate
1092 
1093  --CMX_input_module_state_FSM_inst: CMX_input_module_state_FSM
1094  -- port map (
1095  -- clk => CLKPARB(channel),
1096  -- rst => rst_rx_debounced(channel),
1097  -- pdata => PDATA(channel),
1098  -- ndata => NDATA(channel),
1099  -- counter_enable => counter_enable(channel));
1100 
1101 
1102  --process to sync the pll locked signal to the clk_slow
1103  process (buf_clk40, any_reset_B)
1104  begin -- process
1105  if any_reset_B = '0' then
1106  any_reset_B_s1(channel)<='0';
1107  any_reset_B_synced(channel)<='0';
1108  elsif rising_edge(buf_clk40) then
1109  any_reset_B_synced(channel)<=any_reset_B_s1(channel);
1110  any_reset_B_s1(channel)<='1';
1111  end if;
1112  end process;
1113 
1114 
1115  --pcount: process (buf_clk40, pll_locked)
1116  --begin
1117  -- if pll_locked='0' then
1118  -- cyclecounter(channel)<=to_unsigned(1,1);
1119  --
1120  -- else
1121  -- if rising_edge(buf_clk40) then
1122  -- cyclecounter(channel)<=to_unsigned(1,1);
1123  -- elsif falling_edge(buf_clk40) then
1124  -- cyclecounter(channel)<=to_unsigned(0,1);
1125  -- -- if counter_enable(channel)='0' then
1126  -- -- counter_enable(channel)<='1';
1127  -- -- end if;
1128  -- end if;
1129  -- end if;
1130  --
1131  --end process pcount;
1132 
1133  counter_enable(channel)<=any_reset_B_synced_rr_SOURCE(channel);
1134 
1135 
1136  --this counter will be used for CE to input registers
1137  cyclecounter_next(channel)<=cyclecounter(channel)+1;
1138  pcount: process (CLKPARB(channel))
1139  begin
1140  if rising_edge(CLKPARB(channel)) then
1141  if counter_enable(channel)='0' then
1142  cyclecounter(channel)<=to_unsigned(1,1);
1143  else
1144  cyclecounter(channel)<=cyclecounter_next(channel);
1145  end if;
1146  end if;
1147  end process pcount;
1148 
1149  process (CLKPARB(channel),any_reset_B)
1150  begin
1151  if any_reset_B/='1' then
1152  any_reset_B_synced_rr_SOURCE(channel)<='0';
1153  any_reset_B_synced_r_SOURCE(channel) <='0';
1154  elsif rising_edge(CLKPARB(channel)) then
1155  any_reset_B_synced_rr_SOURCE(channel)<=any_reset_B_synced_r_SOURCE(channel);
1156  any_reset_B_synced_r_SOURCE(channel)<=any_reset_B_synced(channel);
1157  end if;
1158  end process;
1159 
1160  counter_values(channel)<=cyclecounter(channel)(0);
1161 
1162  end generate genCOUNTER;
1163 
1164 
1165 
1166  --spy memory control (for 'SOURCE' memories)
1167 
1168  CMX_input_module_spy_mem_control_FSM_inst: CMX_generic_spy_mem_control_FSM
1169  generic map (
1170  ADDR_REG_RW_GENERIC_SPY_MEM_WORD => ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_WORD,
1171  ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL => ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_CONTROL,
1172  ADDR_REG_RO_GENERIC_SPY_MEM_STATUS => ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_STATUS ,
1173  num_external_RAMS => numactchan)
1174  port map (
1175  clk => buf_clk40,
1176  ncs => ncs,
1177  rd_nwr => rd_nwr,
1178  ds => ds,
1179  addr_vme => addr_vme,
1180  data_vme_in => data_vme_in,
1181  data_vme_out => data_vme_from_below(8+2*numactchan-1),
1182  bus_drive => bus_drive_from_below(8+2*numactchan-1),
1183  mode_control => mode_control_SPY_SOURCE ,
1184  ena => ena_SPY_SOURCE,
1185  wea => wea_SPY_SOURCE,
1186  addra => addra_SPY_SOURCE ,
1187  mem_select_address => mem_select_address_SPY_SOURCE ,
1188  dina => dina_SPY_SOURCE,
1189  douta => douta_SPY_SOURCE ,
1190  port_b_master_inhibit => port_b_master_inhibit_SPY_SOURCE );
1191 
1192 
1193  --- --this will generate a 16:1 multiplexer with mem_select_... acting as the
1194  --- --select signal
1195  --- douta_SPY_SOURCE<=douta_SPY_SOURCE_individual(to_integer(unsigned(mem_select_address_SPY_SOURCE)));
1196 
1197 
1198  gen_source_spy: for i_mem_source in 0 to numactchan-1 generate
1199 
1200  --process to generate a local registers for the inhibit signal
1201  process(CLKPARB(i_mem_source),pll_locked)
1202  begin
1203  if pll_locked /='1' then
1204  spy_write_inhibit_r_SYSTEM_r_SOURCE(i_mem_source)<='0';
1205  else
1206  if rising_edge(CLKPARB(i_mem_source)) then
1207  spy_write_inhibit_r_SYSTEM_r_SOURCE(i_mem_source)<=spy_write_inhibit_r_SYSTEM(i_mem_source);
1208  end if;
1209  end if;
1210  end process;
1211  process(CLKPARB(i_mem_source))
1212  begin
1213  if rising_edge(CLKPARB(i_mem_source)) then
1214  spy_write_inhibit_r_SYSTEM_rr_SOURCE(i_mem_source)<=spy_write_inhibit_r_SYSTEM_r_SOURCE(i_mem_source);
1215  end if;
1216  end process;
1217 
1218  blk_mem_A8x96_B9x48_SPY_SOURCE: blk_mem_A8x96_B9x48
1219  port map (
1220  clka => buf_clk40,
1221  ena => ena_SPY_SOURCE_individual (i_mem_source),
1222  wea => wea_SPY_SOURCE_individual (i_mem_source),
1223  addra => addra_SPY_SOURCE ,
1224  dina => dina_SPY_SOURCE ,
1225  douta => douta_SPY_SOURCE_individual (i_mem_source),
1226  clkb => clkb_SPY_SOURCE_individual (i_mem_source),
1227  enb => enb_SPY_SOURCE_individual (i_mem_source),
1228  web => web_SPY_SOURCE_individual (i_mem_source),
1229  addrb => addrb_SPY_SOURCE_individual (i_mem_source),
1230  dinb => dinb_SPY_SOURCE_individual (i_mem_source),
1231  doutb => doutb_SPY_SOURCE_individual (i_mem_source));
1232 
1233  -- select the control signals based on the value of the mem_select_address_SPY_SOURCE
1234  ena_SPY_SOURCE_individual(i_mem_source) <= ena_SPY_SOURCE when mem_select_address_SPY_SOURCE
1235  =std_logic_vector(to_unsigned(i_mem_source,4)) else '0';
1236 
1237  wea_SPY_SOURCE_individual(i_mem_source)(0) <= wea_SPY_SOURCE when mem_select_address_SPY_SOURCE
1238  =std_logic_vector(to_unsigned(i_mem_source,4)) else '0';
1239 
1240  --this should generate a wide multiplexer with douta_SPY_SOURCE as output
1241  --and the douta_SPY_SOURCE_individual's as inputs
1242  douta_SPY_SOURCE<=douta_SPY_SOURCE_individual(i_mem_source) when mem_select_address_SPY_SOURCE
1243  =std_logic_vector(to_unsigned(i_mem_source,4)) else (others=>'Z');
1244 
1245 
1246  dinb_SPY_SOURCE_individual(i_mem_source)<=NDATA(i_mem_source) & PDATA(i_mem_source);
1247  clkb_SPY_SOURCE_individual(i_mem_source)<=CLKPARB(i_mem_source);
1248  addrb_SPY_SOURCE_individual(i_mem_source)<=std_logic_vector(addrb_SPY_SOURCE_counter(i_mem_source));
1249 
1250 
1251 
1252  vme_inreg_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS: vme_inreg_notri_async
1253  generic map (
1254  ia_vme => ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS+2*i_mem_source,
1255  width =>16)
1256  port map (
1257  ncs => ncs,
1258  rd_nwr => rd_nwr,
1259  ds => ds,
1260  addr_vme => addr_vme,
1261  data_vme_in => data_vme_in,
1262  data_vme_out => data_vme_from_below (9+2*numactchan-1+5*i_mem_source),
1263  bus_drive => bus_drive_from_below(9+2*numactchan-1+5*i_mem_source),
1264  data_from_vme => data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS(i_mem_source),
1265  data_to_vme => data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS(i_mem_source));
1266  data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS(i_mem_source)<=data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS(i_mem_source);
1267 
1268  --synchronisation of the start playback signal to the source domain
1269  process(CLKPARB(i_mem_source), pll_locked)
1270  begin
1271  if pll_locked/='1' then
1272  start_playback_r_SYSTEM_r_SOURCE(i_mem_source)<='0';
1273  else
1274  if rising_edge(CLKPARB(i_mem_source)) then
1275  start_playback_r_SYSTEM_r_SOURCE(i_mem_source)<=start_playback_r_SYSTEM(i_mem_source);
1276  end if;
1277  end if;
1278  end process;
1279 
1280  spy_source_addr_proc: process(CLKPARB(i_mem_source))
1281  begin
1282  if rising_edge(CLKPARB(i_mem_source)) then
1283  --synchronisation of the start playback signal to the source domain
1284  start_playback_r_SYSTEM_rr_SOURCE(i_mem_source)<=start_playback_r_SYSTEM_r_SOURCE(i_mem_source);
1285  if start_playback_r_SYSTEM_rr_SOURCE(i_mem_source)='0' then
1286  addrb_SPY_SOURCE_counter(i_mem_source)<=addrb_SPY_SOURCE_counter(i_mem_source)+1;
1287  else
1288  addrb_SPY_SOURCE_counter(i_mem_source)<=unsigned(
1289  data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS(i_mem_source)(8 downto 0));
1290  end if;
1291 
1292  port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE(i_mem_source)<=port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE(i_mem_source);
1293  port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE(i_mem_source)<=port_b_master_inhibit_SPY_SOURCE_r_SYSTEM(i_mem_source);
1294  web_SPY_SOURCE_rr_SOURCE(i_mem_source)<=web_SPY_SOURCE_r_SOURCE(i_mem_source);
1295  web_SPY_SOURCE_r_SOURCE(i_mem_source)<=web_SPY_SOURCE_rr_SYSTEM(i_mem_source);
1296  enb_SPY_SOURCE_rr_SOURCE(i_mem_source)<=enb_SPY_SOURCE_r_SOURCE(i_mem_source);
1297  enb_SPY_SOURCE_r_SOURCE(i_mem_source)<=enb_SPY_SOURCE_rr_SYSTEM(i_mem_source);
1298 
1299 
1300  end if;
1301  end process;
1302 
1303  --create local registers for the master inhibit to aid timing closure
1304  local_buf_master_inhibit: process(buf_clk40,pll_locked)
1305  begin
1306  if pll_locked='0' then
1307  port_b_master_inhibit_SPY_SOURCE_r_SYSTEM(i_mem_source)<='1';
1308  web_SPY_SOURCE_rr_SYSTEM(i_mem_source)<='0';
1309  enb_SPY_SOURCE_rr_SYSTEM(i_mem_source)<='0';
1310  web_SPY_SOURCE_r_SYSTEM(i_mem_source)<='0';
1311  enb_SPY_SOURCE_r_SYSTEM(i_mem_source)<='0';
1312  elsif rising_edge(buf_clk40) then
1313  port_b_master_inhibit_SPY_SOURCE_r_SYSTEM(i_mem_source)<=port_b_master_inhibit_SPY_SOURCE_split(i_mem_source);
1314  web_SPY_SOURCE_rr_SYSTEM(i_mem_source)<=web_SPY_SOURCE_r_SYSTEM(i_mem_source);
1315  enb_SPY_SOURCE_rr_SYSTEM(i_mem_source)<=enb_SPY_SOURCE_r_SYSTEM(i_mem_source);
1316  web_SPY_SOURCE_r_SYSTEM(i_mem_source)<=web_SPY_SOURCE_split(i_mem_source);
1317  enb_SPY_SOURCE_r_SYSTEM(i_mem_source)<=enb_SPY_SOURCE_split(i_mem_source);
1318  end if;
1319  end process local_buf_master_inhibit;
1320 
1321  web_SPY_SOURCE_individual(i_mem_source)(0)<=web_SPY_SOURCE_rr_SOURCE(i_mem_source) and (not port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE(i_mem_source)) and (not spy_write_inhibit_r_SYSTEM_rr_SOURCE(i_mem_source));
1322  enb_SPY_SOURCE_individual(i_mem_source)<=enb_SPY_SOURCE_rr_SOURCE(i_mem_source) and (not port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE(i_mem_source));
1323 
1324  port_b_master_inhibit_SPY_SOURCE_split(i_mem_source)<=port_b_master_inhibit_SPY_SOURCE;
1325  enb_SPY_SOURCE_split(i_mem_source)<=enb_SPY_SOURCE;
1326  web_SPY_SOURCE_split(i_mem_source)<=web_SPY_SOURCE;
1327 
1328  --this will make an error detection register that in turn will be used to
1329  --generate a latch; also an no-error run length counter is made in this process
1330  error_detect_process: process(CLKPARB(i_mem_source))
1331  begin
1332  if rising_edge(CLKPARB(i_mem_source)) then
1333  if counter_reset_rr_SYSTEM_rr_SOURCE(i_mem_source)/='1' then
1334  if bit_error_latch(i_mem_source)/=x"000000" or std_logic_vector(bit_error_counter(i_mem_source))=x"ffffffff" then --bit_error_detect(i_mem_source)/=x"000000000000" or bit_error_counter(i_mem_source)/=to_unsigned(0,32) or std_logic_vector(bit_error_counter(i_mem_source))=x"ffffffff" then
1335  bit_error_counter_next(i_mem_source)<=bit_error_counter(i_mem_source);
1336  else
1337  bit_error_counter_next(i_mem_source)<=bit_error_counter(i_mem_source)+1;
1338  end if;
1339  else
1340  bit_error_counter_next(i_mem_source)<=to_unsigned(0,32);
1341  end if;
1342 
1343 
1344  bit_error_counter(i_mem_source)<=bit_error_counter_next(i_mem_source);
1345  bit_error_detect(i_mem_source)<=doutb_SPY_SOURCE_individual(i_mem_source) xor (NDATA_r_SOURCE(i_mem_source) & PDATA_r_SOURCE(i_mem_source));
1346 
1347  PDATA_r_SOURCE(i_mem_source)<=PDATA(i_mem_source);
1348  NDATA_r_SOURCE(i_mem_source)<=NDATA(i_mem_source);
1349  --doutb_SPY_SOURCE_individual_r_SOURCE(i_mem_source)<=doutb_SPY_SOURCE_individual(i_mem_source);
1350 
1351  end if;
1352  end process error_detect_process;
1353 
1354  --double register in the source domain
1355  process(CLKPARB(i_mem_source))
1356  begin
1357  if rising_edge(CLKPARB(i_mem_source)) then
1358  counter_reset_rr_SYSTEM_rr_SOURCE(i_mem_source)<=counter_reset_rr_SYSTEM_r_SOURCE(i_mem_source);
1359  end if;
1360  end process;
1361  process(CLKPARB(i_mem_source),pll_locked)
1362  begin
1363  if pll_locked/='1' then
1364  counter_reset_rr_SYSTEM_r_SOURCE(i_mem_source)<='0';
1365  elsif rising_edge(CLKPARB(i_mem_source)) then
1366  counter_reset_rr_SYSTEM_r_SOURCE(i_mem_source)<=counter_reset_rr_SYSTEM(i_mem_source);
1367  end if;
1368  end process;
1369 
1370 
1371 
1372  --double register to close timing
1373  process(buf_clk40)
1374  begin
1375  if rising_edge(buf_clk40) then
1376  counter_reset_rr_SYSTEM(i_mem_source)<=counter_reset_r_SYSTEM(i_mem_source);
1377  end if;
1378  end process;
1379  process(buf_clk40,pll_locked)
1380  begin
1381  if pll_locked/='1' then
1382  counter_reset_r_SYSTEM(i_mem_source)<='0';
1383  elsif rising_edge(buf_clk40) then
1384  counter_reset_r_SYSTEM(i_mem_source)<=counter_reset;
1385  end if;
1386  end process;
1387 
1388 
1389  gen_err_latch_bit: for i_bit in 0 to numbitsinchan-1 generate
1390 
1391  --resettable 'latch' (so not really a latch) that is set if there is an error
1392  --on a given bit
1393  process(CLKPARB(i_mem_source))
1394  begin
1395  if rising_edge(CLKPARB(i_mem_source)) then
1396  if counter_reset_rr_SYSTEM_rr_SOURCE(i_mem_source)/='1' then
1397  if bit_error_detect(i_mem_source)(i_bit)='1' or bit_error_detect(i_mem_source)(i_bit+numbitsinchan)='1' then
1398  bit_error_latch(i_mem_source)(i_bit)<='1';
1399  end if;
1400  else
1401  bit_error_latch(i_mem_source)(i_bit)<='0';
1402  end if;
1403  end if;
1404  end process;
1405 
1406  end generate gen_err_latch_bit;
1407 
1408  --assign latches as data to the registers
1409  data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0(i_mem_source)<=bit_error_latch(i_mem_source)(15 downto 0);
1410  data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1(i_mem_source)(numbitsinchan-16 -1 downto 0) <=bit_error_latch(i_mem_source)(numbitsinchan-1 downto 16);
1411  data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1(i_mem_source)(15 downto numbitsinchan-16)<=(others=>'1');
1412 
1413 
1414  vme_outreg_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0: vme_outreg_notri_async
1415  generic map (
1416  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR+(4*i_mem_source),
1417  width => 16)
1418  port map (
1419  addr_vme => addr_vme,
1420  ncs => ncs,
1421  rd_nwr => rd_nwr,
1422  ds => ds,
1423  data_to_vme => data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0(i_mem_source),
1424  data_vme => data_vme_from_below(9 + 2*numactchan-1 + i_mem_source*5 +1),
1425  bus_drive => bus_drive_from_below ( 9 + 2*numactchan-1 + i_mem_source*5 +1 )
1426  );
1427 
1428 
1429  vme_outreg_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1: vme_outreg_notri_async
1430  generic map (
1431  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR+(4*i_mem_source)+2,
1432  width => 16)
1433  port map (
1434  addr_vme => addr_vme,
1435  ncs => ncs,
1436  rd_nwr => rd_nwr,
1437  ds => ds,
1438  data_to_vme => data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1(i_mem_source),
1439  data_vme => data_vme_from_below(9 + 2*numactchan-1 + i_mem_source*5 +2),
1440  bus_drive => bus_drive_from_below (9 + 2*numactchan-1 + i_mem_source*5 +2)
1441  );
1442 
1443  vme_outreg_REG_RO_INPUT_SPY_MEM_SOURCE_NOERROR_COUNTER_0: vme_outreg_notri_async
1444  generic map (
1445  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_NOERROR_COUNTER+(4*i_mem_source),
1446  width => 16)
1447  port map (
1448  addr_vme => addr_vme,
1449  ncs => ncs,
1450  rd_nwr => rd_nwr,
1451  ds => ds,
1452  data_to_vme => std_logic_vector(bit_error_counter(i_mem_source)(15 downto 0)),
1453  data_vme => data_vme_from_below(9 + 2*numactchan-1 + i_mem_source*5 +3),
1454  bus_drive => bus_drive_from_below (9 + 2*numactchan-1 + i_mem_source*5 +3)
1455  );
1456 
1457  vme_outreg_REG_RO_INPUT_SPY_MEM_SOURCE_NOERROR_COUNTER_1: vme_outreg_notri_async
1458  generic map (
1459  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_NOERROR_COUNTER+(4*i_mem_source)+2,
1460  width => 16)
1461  port map (
1462  addr_vme => addr_vme,
1463  ncs => ncs,
1464  rd_nwr => rd_nwr,
1465  ds => ds,
1466  data_to_vme => std_logic_vector(bit_error_counter(i_mem_source)(31 downto 16)),
1467  data_vme => data_vme_from_below(9 + 2*numactchan-1 + i_mem_source*5 +4),
1468  bus_drive => bus_drive_from_below (9 + 2*numactchan-1 + i_mem_source*5 +4)
1469  );
1470 
1471 
1472  end generate gen_source_spy;
1473 
1474  --port enables - we read when verifying and spying and write only and spying
1475  --playback is not implemented yet from this memory
1476  enb_SPY_SOURCE<='1' when mode_control_SPY_SOURCE=CONST_DPR_CONTROL_SPY or mode_control_SPY_SOURCE=CONST_DPR_CONTROL_VERIFY else '0';
1477  web_SPY_SOURCE<='1' when mode_control_SPY_SOURCE=CONST_DPR_CONTROL_SPY else '0';
1478 
1479 
1480 
1481 
1482 
1483 
1484  --spy memory control (for 'SYSYTEM' memories)
1485 
1486  CMX_input_module_spy_mem_control_FSM_inst_system: CMX_generic_spy_mem_control_FSM
1487  generic map (
1488  ADDR_REG_RW_GENERIC_SPY_MEM_WORD => ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_WORD,
1489  ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL => ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_CONTROL,
1490  ADDR_REG_RO_GENERIC_SPY_MEM_STATUS => ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_STATUS ,
1491  num_external_RAMS => numactchan)
1492  port map (
1493  clk => buf_clk40,
1494  ncs => ncs,
1495  rd_nwr => rd_nwr,
1496  ds => ds,
1497  addr_vme => addr_vme,
1498  data_vme_in => data_vme_in,
1499  data_vme_out => data_vme_from_below(10+ 2*numactchan-1 + 5*numactchan-1 ),
1500  bus_drive => bus_drive_from_below(10+ 2*numactchan-1 + 5*numactchan-1 ),
1501  mode_control => mode_control_SPY_SYSTEM ,
1502  ena => ena_SPY_SYSTEM,
1503  wea => wea_SPY_SYSTEM,
1504  addra => addra_SPY_SYSTEM ,
1505  mem_select_address => mem_select_address_SPY_SYSTEM ,
1506  dina => dina_SPY_SYSTEM,
1507  douta => douta_SPY_SYSTEM ,
1508  port_b_master_inhibit => port_b_master_inhibit_SPY_SYSTEM );
1509 
1510 
1511 
1512  vme_inreg_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS: vme_inreg_notri_async
1513  generic map (
1514  ia_vme => ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS,
1515  width =>16)
1516  port map (
1517  ncs => ncs,
1518  rd_nwr => rd_nwr,
1519  ds => ds,
1520  addr_vme => addr_vme,
1521  data_vme_in => data_vme_in,
1522  data_vme_out => data_vme_from_below(11+ 2*numactchan-1 + 5*numactchan-1),
1523  bus_drive => bus_drive_from_below(11+ 2*numactchan-1 + 5*numactchan-1),
1524  data_from_vme => data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS,
1525  data_to_vme => data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS
1526  );
1527  data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS<=data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS;
1528 
1529  --- douta_SPY_SYSTEM<=douta_SPY_SYSTEM_individual(to_integer(unsigned(mem_select_address_SPY_SYSTEM)) );
1530 
1531 
1532  gen_system_spy: for i_mem_system in 0 to numactchan-1 generate
1533 
1534  --process to locally register the inhibit signal;
1535  process(buf_clk40,pll_locked)
1536  begin
1537  if pll_locked/='1' then
1538  spy_write_inhibit_r_SYSTEM(i_mem_system)<='0';
1539  elsif rising_edge(buf_clk40) then
1540  spy_write_inhibit_r_SYSTEM(i_mem_system)<=spy_write_inhibit;
1541  end if;
1542  end process;
1543  process(buf_clk40)
1544  begin
1545  if rising_edge(buf_clk40) then
1546  spy_write_inhibit_rr_SYSTEM(i_mem_system)<=spy_write_inhibit_r_SYSTEM(i_mem_system);
1547  end if;
1548  end process;
1549 
1550 
1551 
1552  blk_mem_A8x96_B8x96_SPY_SYSTEM: blk_mem_A8x96_B8x96
1553  port map (
1554  clka => buf_clk40,
1555  ena => ena_SPY_SYSTEM_individual (i_mem_system),
1556  wea => wea_SPY_SYSTEM_individual (i_mem_system),
1557  addra => addra_SPY_SYSTEM ,
1558  dina => dina_SPY_SYSTEM ,
1559  douta => douta_SPY_SYSTEM_individual (i_mem_system),
1560  clkb => buf_clk40,
1561  enb => enb_SPY_SYSTEM_individual (i_mem_system),
1562  web => web_SPY_SYSTEM_individual (i_mem_system),
1563  addrb => addrb_SPY_SYSTEM_individual (i_mem_system),
1564  dinb => dinb_SPY_SYSTEM_individual (i_mem_system),
1565  doutb => doutb_SPY_SYSTEM_individual (i_mem_system));
1566 
1567  -- select the control signals based on the value of the mem_select_address_SPY_SYSTEM
1568  ena_SPY_SYSTEM_individual(i_mem_system) <= ena_SPY_SYSTEM when mem_select_address_SPY_SYSTEM
1569  =std_logic_vector(to_unsigned(i_mem_system,4)) else '0';
1570 
1571  wea_SPY_SYSTEM_individual(i_mem_system)(0) <= wea_SPY_SYSTEM when mem_select_address_SPY_SYSTEM
1572  =std_logic_vector(to_unsigned(i_mem_system,4)) else '0';
1573 
1574  --this should generate a wide multiplexer with douta_SPY_SYSTEM as output
1575  --and the douta_SPY_SYSTEM_individual's as inputs
1576  douta_SPY_SYSTEM<=douta_SPY_SYSTEM_individual(i_mem_system) when mem_select_address_SPY_SYSTEM
1577  =std_logic_vector(to_unsigned(i_mem_system,4)) else (others=>'Z');
1578 
1579 
1580  --data coming in from the 80->40 Mbps deserialiser
1581  dinb_SPY_SYSTEM_individual(i_mem_system)<= ODATA_sig_r_SYSTEM(i_mem_system);
1582  addrb_SPY_SYSTEM_individual(i_mem_system)<=std_logic_vector(addrb_SPY_SYSTEM_counter(i_mem_system));
1583 
1584 
1585 
1586 
1587  process(buf_clk40,pll_locked)
1588  begin
1589  if pll_locked/='1' then
1590  start_playback_r_SYSTEM(i_mem_system)<='0';
1591  elsif rising_edge(buf_clk40) then
1592  start_playback_r_SYSTEM(i_mem_system)<=start_playback;
1593  end if;
1594  end process;
1595  spy_source_addr_proc: process(buf_clk40)
1596  begin
1597  if rising_edge(buf_clk40) then
1598  --a local register (one copy for each of the memories)to ease timing
1599  start_playback_rr_SYSTEM(i_mem_system)<=start_playback_r_SYSTEM(i_mem_system);
1600  if start_playback_rr_SYSTEM(i_mem_system)='0' then
1601  addrb_SPY_SYSTEM_counter(i_mem_system)<=addrb_SPY_SYSTEM_counter(i_mem_system)+1;
1602  else
1603  addrb_SPY_SYSTEM_counter(i_mem_system)<=unsigned(
1604  data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS(7 downto 0));
1605  end if;
1606 
1607  end if;
1608  end process;
1609 
1610  --create local registers for the master inhibit to aid timing closure
1611  local_buf_master_inhibit_system: process(buf_clk40,pll_locked)
1612  begin
1613  if pll_locked='0' then
1614  port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM(i_mem_system)<='1';
1615  web_SPY_SYSTEM_r_SYSTEM(i_mem_system)<='0';
1616  enb_SPY_SYSTEM_r_SYSTEM(i_mem_system)<='0';
1617  elsif rising_edge(buf_clk40) then
1618  port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM(i_mem_system)<=port_b_master_inhibit_SPY_SYSTEM_split(i_mem_system);
1619  web_SPY_SYSTEM_r_SYSTEM(i_mem_system)<=web_SPY_SYSTEM_split(i_mem_system);
1620  enb_SPY_SYSTEM_r_SYSTEM(i_mem_system)<=enb_SPY_SYSTEM_split(i_mem_system);
1621  end if;
1622  end process local_buf_master_inhibit_system;
1623 
1624  web_SPY_SYSTEM_individual(i_mem_system)(0)<=web_SPY_SYSTEM_r_SYSTEM(i_mem_system) and (not port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM(i_mem_system)) and (not spy_write_inhibit_rr_SYSTEM(i_mem_system));
1625  enb_SPY_SYSTEM_individual(i_mem_system)<=enb_SPY_SYSTEM_r_SYSTEM(i_mem_system) and (not port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM(i_mem_system));
1626 
1627 
1628  port_b_master_inhibit_SPY_SYSTEM_split(i_mem_system)<=port_b_master_inhibit_SPY_SYSTEM;
1629  enb_SPY_SYSTEM_split(i_mem_system)<=enb_SPY_SYSTEM;
1630  web_SPY_SYSTEM_split(i_mem_system)<=web_SPY_SYSTEM;
1631 
1632 
1633 
1634  --this will make an error detection register that in turn will be used to
1635  --generate a latch; also an no-error run length counter is made in this process
1636  error_detect_process_system: process(buf_clk40)
1637  begin
1638  if rising_edge(buf_clk40) then
1639  if counter_reset_rr_SYSTEM(i_mem_system)/='1' then
1640  if bit_error_latch_system(i_mem_system)/=x"000000" or std_logic_vector(bit_error_counter_system(i_mem_system))=x"ffffffff" then --bit_error_detect(i_mem_source)/=x"000000000000" or bit_error_counter(i_mem_source)/=to_unsigned(0,32) or std_logic_vector(bit_error_counter(i_mem_source))=x"ffffffff" then
1641  bit_error_counter_system_next(i_mem_system)<=bit_error_counter_system(i_mem_system);
1642  else
1643  bit_error_counter_system_next(i_mem_system)<=bit_error_counter_system(i_mem_system)+1;
1644  end if;
1645  else
1646  bit_error_counter_system_next(i_mem_system)<=to_unsigned(0,32);
1647  end if;
1648 
1649 
1650  bit_error_counter_system(i_mem_system)<=bit_error_counter_system_next(i_mem_system);
1651  bit_error_detect_system(i_mem_system)<=doutb_SPY_SYSTEM_individual(i_mem_system) xor ODATA_sig_rr_SYSTEM(i_mem_system);
1652 
1653  ODATA_sig_rr_SYSTEM(i_mem_system)<=ODATA_sig_r_SYSTEM(i_mem_system);
1654 
1655 
1656  end if;
1657  end process error_detect_process_system;
1658  process(buf_clk40, pll_locked)
1659  begin
1660  if pll_locked/='1' then
1661  ODATA(i_mem_system)<=(others=>'0');
1662  PAR_ERROR_total<='0';
1663  ODATA_sig_r_SYSTEM(i_mem_system)<=(others=>'0');
1664  PAR_ERROR_sig_r_SYSTEM<=(others=>'0');
1665  elsif rising_edge(buf_clk40) then
1666  --WTF 20150204 push the mux before the last flip-flop
1667  if mode_control_SPY_SYSTEM /= CONST_DPR_CONTROL_PLAYBACK then
1668  PAR_ERROR_total<=PAR_ERROR_sig_r_SYSTEM_ORed;
1669  ODATA(i_mem_system)<=ODATA_sig(i_mem_system);
1670  else
1671  ODATA(i_mem_system)<=doutb_SPY_SYSTEM_individual(i_mem_system);
1672  PAR_ERROR_total<='0';
1673  end if;
1674  PAR_ERROR_sig_r_SYSTEM<=PAR_ERROR_sig;
1675  ODATA_sig_r_SYSTEM(i_mem_system)<=ODATA_sig(i_mem_system);
1676  end if;
1677  end process;
1678 
1679 
1680 
1681  gen_err_latch_bit_system: for i_bit in 0 to numbitsinchan-1 generate
1682 
1683 
1684  --resettable 'latch' (so not really a latch) that is set if there is an error
1685  --on a given bit
1686  process(buf_clk40)
1687  begin
1688  if rising_edge(buf_clk40) then
1689 
1690  if counter_reset_rr_SYSTEM(i_mem_system)/='1' then
1691  if bit_error_detect_system(i_mem_system)(i_bit)='1' or
1692  bit_error_detect_system(i_mem_system)(i_bit+numbitsinchan)='1' or
1693  bit_error_detect_system(i_mem_system)(i_bit+2*numbitsinchan)='1' or
1694  bit_error_detect_system(i_mem_system)(i_bit+3*numbitsinchan)='1' then
1695 
1696  bit_error_latch_system(i_mem_system)(i_bit)<='1';
1697 
1698  end if;
1699 
1700  else
1701  bit_error_latch_system(i_mem_system)(i_bit)<='0';
1702  end if;
1703 
1704  end if;
1705  end process;
1706 
1707  end generate gen_err_latch_bit_system;
1708 
1709  --assign latches as data to the registers
1710  data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0(i_mem_system)<=bit_error_latch_system(i_mem_system)(15 downto 0);
1711  data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1(i_mem_system)(numbitsinchan-16 -1 downto 0) <=bit_error_latch_system(i_mem_system)(numbitsinchan-1 downto 16);
1712  data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1(i_mem_system)(15 downto numbitsinchan-16)<=(others=>'1');
1713 
1714 
1715  vme_outreg_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0: vme_outreg_notri_async
1716  generic map (
1717  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR+(4*i_mem_system),
1718  width => 16)
1719  port map (
1720  addr_vme => addr_vme,
1721  ncs => ncs,
1722  rd_nwr => rd_nwr,
1723  ds => ds,
1724  data_to_vme => data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0(i_mem_system),
1725  data_vme => data_vme_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system),
1726  bus_drive => bus_drive_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system)
1727  );
1728 
1729 
1730  vme_outreg_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1: vme_outreg_notri_async
1731  generic map (
1732  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR+(4*i_mem_system)+2,
1733  width => 16)
1734  port map (
1735  addr_vme => addr_vme,
1736  ncs => ncs,
1737  rd_nwr => rd_nwr,
1738  ds => ds,
1739  data_to_vme => data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1(i_mem_system),
1740  data_vme => data_vme_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system+1),
1741  bus_drive => bus_drive_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system+1)
1742  );
1743 
1744  vme_outreg_REG_RO_INPUT_SPY_MEM_SYSTEM_NOERROR_COUNTER_0: vme_outreg_notri_async
1745  generic map (
1746  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_NOERROR_COUNTER+(4*i_mem_system),
1747  width => 16)
1748  port map (
1749  addr_vme => addr_vme,
1750  ncs => ncs,
1751  rd_nwr => rd_nwr,
1752  ds => ds,
1753  data_to_vme => std_logic_vector(bit_error_counter_system(i_mem_system)(15 downto 0)),
1754  data_vme => data_vme_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system+2),
1755  bus_drive => bus_drive_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system+2)
1756  );
1757 
1758  vme_outreg_REG_RO_INPUT_SPY_MEM_SYSTEM_NOERROR_COUNTER_1: vme_outreg_notri_async
1759  generic map (
1760  ia_vme => ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_NOERROR_COUNTER+(4*i_mem_system)+2,
1761  width => 16)
1762  port map (
1763  addr_vme => addr_vme,
1764  ncs => ncs,
1765  rd_nwr => rd_nwr,
1766  ds => ds,
1767  data_to_vme => std_logic_vector(bit_error_counter_system(i_mem_system)(31 downto 16)),
1768  data_vme => data_vme_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system+3),
1769  bus_drive => bus_drive_from_below(12+ 2*numactchan-1 + 5*numactchan-1 +4*i_mem_system+3)
1770  );
1771 
1772 
1773  end generate gen_system_spy;
1774 
1775  --port enables - we enable B port when verifying, spying and playing back. Write
1776  --is enabled only when spying
1777  enb_SPY_SYSTEM<='1' when mode_control_SPY_SYSTEM=CONST_DPR_CONTROL_SPY
1778  or mode_control_SPY_SYSTEM=CONST_DPR_CONTROL_VERIFY
1779  or mode_control_SPY_SYSTEM=CONST_DPR_CONTROL_PLAYBACK
1780  else '0';
1781  web_SPY_SYSTEM<='1' when mode_control_SPY_SYSTEM=CONST_DPR_CONTROL_SPY else '0';
1782 
1783 
1784  event_counter_s<=signed(std_logic_vector(event_counter));
1785  gen_clock_detect: for channel in 0 to numactchan-1 generate
1786 
1787 
1788  clock_detect_counter_next(channel)<=clock_detect_counter(channel)+1;
1789  process(CLKPARB(channel))
1790  begin
1791  if rising_edge(CLKPARB(channel)) then
1792  clock_detect_counter(channel)<=clock_detect_counter_next(channel);
1793  end if;
1794  end process;
1795 
1796  backplane_events_counter_next(channel)<=backplane_events_counter(channel)+1;
1797  process(CLKPARB(channel))
1798  begin
1799  if rising_edge(CLKPARB(channel)) then
1800  if counter_reset_rr_SYSTEM_rr_SOURCE(channel)/='1' then
1801  if backplane_events_counter(channel)/=max_ctr32 then
1802  if cyclecounter(channel)=to_unsigned(1,1) then
1803  backplane_events_counter(channel)<=backplane_events_counter_next(channel);
1804  end if;
1805  end if;
1806  else
1807  backplane_events_counter(channel)<=to_unsigned(0,32);
1808  end if;
1809  end if;
1810  end process;
1811 
1812  backplane_events_counter_s(channel)<=signed(std_logic_vector(backplane_events_counter(channel)));
1813 
1814  process(buf_clk40)
1815  begin
1816  if rising_edge(buf_clk40) then
1817  clock_diff_counter(channel)<=event_counter_s-backplane_events_counter_s(channel);
1818  end if;
1819  end process;
1820 
1821  process(buf_clk40)
1822  begin
1823  if rising_edge(buf_clk40) then
1824  if counter_reset_rr_SYSTEM(channel) /= '1' then
1825  if clock_diff_counter(channel)/=to_signed(0,32) then
1826  clock_diff_duration_counter(channel)<=clock_diff_duration_counter(channel)+1;
1827  end if;
1828  else
1829  clock_diff_duration_counter(channel)<=to_unsigned(0,32);
1830  end if;
1831  end if;
1832  end process;
1833 
1834  process(buf_clk40)
1835  begin
1836  if rising_edge(buf_clk40) then
1837  if counter_reset_rr_SYSTEM(channel) /= '1' then
1838  if clock_diff_counter(channel) > clock_diff_counter_ratchet_up(channel) then
1839  clock_diff_counter_ratchet_up(channel)<=clock_diff_counter(channel);
1840  end if;
1841  if clock_diff_counter(channel) < clock_diff_counter_ratchet_down(channel) then
1842  clock_diff_counter_ratchet_down(channel)<=clock_diff_counter(channel);
1843  end if;
1844  else
1845  clock_diff_counter_ratchet_up(channel)<=to_signed(0,32);
1846  clock_diff_counter_ratchet_down(channel)<=to_signed(0,32);
1847  end if;
1848  end if;
1849  end process;
1850 
1851 
1852 
1853 
1854  vme_outreg_REG_RO_CLOCK_DETECT_COUNTER: vme_outreg_notri_async
1855  generic map (
1856  ia_vme => ADDR_REG_RO_CLOCK_DETECT_COUNTER+2*channel,
1857  width => 16)
1858  port map (
1859  addr_vme => addr_vme,
1860  ncs => ncs,
1861  rd_nwr => rd_nwr,
1862  ds => ds,
1863  data_to_vme => std_logic_vector(clock_detect_counter(channel)),
1864  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel),
1865  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel)
1866  );
1867 
1868 
1869  vme_outreg_REG_RO_CLOCK_DIFF_DETECT_COUNTER_0: vme_outreg_notri_async
1870  generic map (
1871  ia_vme => ADDR_REG_RO_CLOCK_DIFF_DETECT_COUNTER+4*channel,
1872  width => 16)
1873  port map (
1874  addr_vme => addr_vme,
1875  ncs => ncs,
1876  rd_nwr => rd_nwr,
1877  ds => ds,
1878  data_to_vme => std_logic_vector(clock_diff_counter(channel)(15 downto 0)),
1879  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+1),
1880  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+1)
1881  );
1882 
1883  vme_outreg_REG_RO_CLOCK_DIFF_DETECT_COUNTER_1: vme_outreg_notri_async
1884  generic map (
1885  ia_vme => ADDR_REG_RO_CLOCK_DIFF_DETECT_COUNTER+4*channel+2,
1886  width => 16)
1887  port map (
1888  addr_vme => addr_vme,
1889  ncs => ncs,
1890  rd_nwr => rd_nwr,
1891  ds => ds,
1892  data_to_vme => std_logic_vector(clock_diff_counter(channel)(31 downto 16)),
1893  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+2),
1894  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+2));
1895 
1896 
1897  vme_outreg_REG_RO_CLOCK_DIFF_DURATION_COUNTER_0: vme_outreg_notri_async
1898  generic map (
1899  ia_vme => ADDR_REG_RO_CLOCK_DIFF_DURATION_COUNTER+4*channel,
1900  width => 16)
1901  port map (
1902  addr_vme => addr_vme,
1903  ncs => ncs,
1904  rd_nwr => rd_nwr,
1905  ds => ds,
1906  data_to_vme => std_logic_vector(clock_diff_duration_counter(channel)(15 downto 0)),
1907  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+3),
1908  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+3)
1909  );
1910 
1911  vme_outreg_REG_RO_CLOCK_DIFF_DURATION_COUNTER_1: vme_outreg_notri_async
1912  generic map (
1913  ia_vme => ADDR_REG_RO_CLOCK_DIFF_DURATION_COUNTER+4*channel+2,
1914  width => 16)
1915  port map (
1916  addr_vme => addr_vme,
1917  ncs => ncs,
1918  rd_nwr => rd_nwr,
1919  ds => ds,
1920  data_to_vme => std_logic_vector(clock_diff_duration_counter(channel)(31 downto 16)),
1921  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+4),
1922  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+4));
1923 
1924 
1925 
1926  vme_outreg_REG_RO_CLOCK_DIFF_RATCHET_UP_COUNTER_0: vme_outreg_notri_async
1927  generic map (
1928  ia_vme => ADDR_REG_RO_CLOCK_DIFF_RATCHET_UP_COUNTER+4*channel,
1929  width => 16)
1930  port map (
1931  addr_vme => addr_vme,
1932  ncs => ncs,
1933  rd_nwr => rd_nwr,
1934  ds => ds,
1935  data_to_vme => std_logic_vector(clock_diff_counter_ratchet_up(channel)(15 downto 0)),
1936  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+5),
1937  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+5)
1938  );
1939 
1940  vme_outreg_REG_RO_CLOCK_DIFF_RATCHET_UP_COUNTER_1: vme_outreg_notri_async
1941  generic map (
1942  ia_vme => ADDR_REG_RO_CLOCK_DIFF_RATCHET_UP_COUNTER+4*channel+2,
1943  width => 16)
1944  port map (
1945  addr_vme => addr_vme,
1946  ncs => ncs,
1947  rd_nwr => rd_nwr,
1948  ds => ds,
1949  data_to_vme => std_logic_vector(clock_diff_counter_ratchet_up(channel)(31 downto 16)),
1950  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+6),
1951  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+6));
1952 
1953 
1954 
1955  vme_outreg_REG_RO_CLOCK_DIFF_RATCHET_DOWN_COUNTER_0: vme_outreg_notri_async
1956  generic map (
1957  ia_vme => ADDR_REG_RO_CLOCK_DIFF_RATCHET_DOWN_COUNTER+4*channel,
1958  width => 16)
1959  port map (
1960  addr_vme => addr_vme,
1961  ncs => ncs,
1962  rd_nwr => rd_nwr,
1963  ds => ds,
1964  data_to_vme => std_logic_vector(clock_diff_counter_ratchet_down(channel)(15 downto 0)),
1965  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+7),
1966  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+7)
1967  );
1968 
1969  vme_outreg_REG_RO_CLOCK_DIFF_RATCHET_DOWN_COUNTER_1: vme_outreg_notri_async
1970  generic map (
1971  ia_vme => ADDR_REG_RO_CLOCK_DIFF_RATCHET_DOWN_COUNTER+4*channel+2,
1972  width => 16)
1973  port map (
1974  addr_vme => addr_vme,
1975  ncs => ncs,
1976  rd_nwr => rd_nwr,
1977  ds => ds,
1978  data_to_vme => std_logic_vector(clock_diff_counter_ratchet_down(channel)(31 downto 16)),
1979  data_vme => data_vme_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+8),
1980  bus_drive => bus_drive_from_below(13+ 2*numactchan-1 + 5*numactchan-1 +4*numactchan-1 + 9*channel+8));
1981 
1982 
1983 
1984  end generate gen_clock_detect;
1985 
1986  --chipscope_icon_u1_c1_inst: entity work.chipscope_icon_u1_c1
1987  -- port map (
1988  -- CONTROL0 => CONTROL0);
1989  --
1990  --chipscope_ila_inputmod_systemSPY_logic_inst: entity work.chipscope_ila_inputmod_systemSPY_logic
1991  -- port map (
1992  -- CONTROL => CONTROL0,
1993  -- CLK => buf_clk40,
1994  -- DATA => data_ila,
1995  -- TRIG0 => trig_ila);
1996  --
1997  --
1998  --data_ila(23 downto 0)<=bit_error_latch_system(5);
1999  --data_ila(119 downto 24)<=bit_error_detect_system(5);
2000  --data_ila(120) <= counter_reset_r_SYSTEM(5);
2001  --data_ila(121) <= counter_reset_rr_SYSTEM(5);
2002  --data_ila(122) <= spy_write_inhibit_r_SYSTEM(5);
2003  --data_ila(123) <= spy_write_inhibit_rr_SYSTEM(5);
2004  --data_ila(124) <= enb_SPY_SYSTEM_individual(5);
2005  --data_ila(125) <= web_SPY_SYSTEM_individual(5)(0);
2006  --data_ila(126) <= enb_SPY_SYSTEM_r_SYSTEM(5);
2007  --data_ila(127) <= web_SPY_SYSTEM_r_SYSTEM(5);
2008  --data_ila(128) <= port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM(5);
2009  --data_ila(129) <= spy_write_inhibit_rr_SYSTEM(5);
2010  --data_ila(130) <= start_playback_rr_SYSTEM(5);
2011  --data_ila(138 downto 131)<=addrb_SPY_SYSTEM_individual(5);
2012  --data_ila(170 downto 139)<=std_logic_vector(bit_error_counter_system(5));
2013  --data_ila(202 downto 171)<=std_logic_vector(bit_error_counter_system_next(5));
2014  --data_ila(298 downto 203)<=doutb_SPY_SYSTEM_individual(5);
2015  --data_ila(394 downto 299)<=ODATA_sig_r_SYSTEM(5);
2016  --data_ila(490 downto 395)<=ODATA_sig_rr_SYSTEM(5);
2017  --
2018  --
2019  --trig_ila(7 downto 0)<=bit_error_latch_system(5)(7 downto 0);
2020  --trig_ila(15 downto 8)<=bit_error_detect_system(5)(7 downto 0);
2021  --trig_ila(16) <= counter_reset_r_SYSTEM(5);
2022  --trig_ila(17) <= counter_reset_rr_SYSTEM(5);
2023  --trig_ila(18) <= spy_write_inhibit_r_SYSTEM(5);
2024  --trig_ila(19) <= spy_write_inhibit_rr_SYSTEM(5);
2025  --trig_ila(20) <= enb_SPY_SYSTEM_individual(5);
2026  --trig_ila(21) <= web_SPY_SYSTEM_individual(5)(0);
2027  --trig_ila(22) <= enb_SPY_SYSTEM_r_SYSTEM(5);
2028  --trig_ila(23) <= web_SPY_SYSTEM_r_SYSTEM(5);
2029  --trig_ila(24) <= port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM(5);
2030  --trig_ila(25) <= spy_write_inhibit_rr_SYSTEM(5);
2031  --trig_ila(26) <= start_playback_rr_SYSTEM(5);
2032  --trig_ila(27) <= pll_locked;
2033 
2034 
2035 
2036 
2037 end Behavioral;
2038 
CMX_input_module.Behavioral.any_reset_B_s1
std_logic_vector (numactchan - 1 downto 0) any_reset_B_s1
Definition: CMX_input_module.vhd:299
CMX_input_module.Behavioral.clock_detect_counter_next
arr_ctr_16bit (numactchan - 1 downto 0) clock_detect_counter_next
Definition: CMX_input_module.vhd:306
blk_mem_a8x96_b8x96_spy_system
blk_mem_a8x96_b8x96 blk_mem_a8x96_b8x96_spy_systemblk_mem_a8x96_b8x96_spy_system
Definition: CMX_input_module.vhd:1552
CMX_input_module.Behavioral.CLKPAR_DATA
STD_LOGIC_VECTOR (numactchan - 1 downto 0) CLKPAR_DATA
Definition: CMX_input_module.vhd:285
CMX_data_delay.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_data_delay.vhd:50
CMX_input_module.Behavioral.enb_SPY_SOURCE_individual
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:485
CMX_input_module.Behavioral.PDATA_r_SOURCE
arr_word (numactchan - 1 downto 0) PDATA_r_SOURCE
Definition: CMX_input_module.vhd:273
CMX_input_module.Behavioral.CLKPARB
STD_LOGIC_VECTOR (numactchan - 1 downto 0) CLKPARB
Definition: CMX_input_module.vhd:282
CMX_input_module.Behavioral.data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS
std_logic_vector (15 downto 0) data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS
Definition: CMX_input_module.vhd:587
CMX_input_module.Behavioral.any_reset_B_synced_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) any_reset_B_synced_r_SOURCE
Definition: CMX_input_module.vhd:300
CMX_input_module.Behavioral.PAR_ERROR_sig_r_SYSTEM_ORed
std_logic PAR_ERROR_sig_r_SYSTEM_ORed
Definition: CMX_input_module.vhd:101
CMX_input_module.Behavioral.par_err_counter
arr_ctr_32bit (numactchan - 1 downto 0) par_err_counter
Definition: CMX_input_module.vhd:113
CMX_input_module.Behavioral.dina_SPY_SOURCE
std_logic_vector (95 downto 0) dina_SPY_SOURCE
Definition: CMX_input_module.vhd:426
CMX_input_module.Behavioral.cyclecounter
arr_ctr_1bit (numactchan - 1 downto 0) cyclecounter
Definition: CMX_input_module.vhd:302
CMX_data_delay.ncs
in ncsstd_logic
Definition: CMX_data_delay.vhd:45
CMX_input_module.ODATA
out ODATAarr_4Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:33
CMX_input_module.Behavioral.data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS
std_logic_vector (15 downto 0) data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS
Definition: CMX_input_module.vhd:586
CMX_input_module.Behavioral.spy_write_inhibit_r_SYSTEM_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) spy_write_inhibit_r_SYSTEM_r_SOURCE
Definition: CMX_input_module.vhd:480
BUF_2X24_AT_80_TO_1X96_AT_40.clk80
in clk80std_logic
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:30
or_all
Definition: or_all.vhd:28
CMX_generic_spy_mem_control_FSM.ADDR_REG_RW_GENERIC_SPY_MEM_WORD
ADDR_REG_RW_GENERIC_SPY_MEM_WORDinteger :=0
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:25
CMX_data_delay.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_data_delay.vhd:49
CMX_input_module.ds
in dsstd_logic
Definition: CMX_input_module.vhd:59
CMX_input_module.Behavioral.DELAYED_DATA24
arr_word (numactchan - 1 downto 0) DELAYED_DATA24
Definition: CMX_input_module.vhd:73
CMX_input_module.Behavioral.counter_reset_unstretched
std_logic counter_reset_unstretched
Definition: CMX_input_module.vhd:125
vme_outreg_reg_ro_clock_diff_ratchet_up_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_ratchet_up_counter_0vme_outreg_reg_ro_clock_diff_ratchet_up_counter_0
Definition: CMX_input_module.vhd:1926
vme_inreg_notri.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:39
CMX_input_module.Behavioral.enb_SPY_SYSTEM_split
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SYSTEM_split
Definition: CMX_input_module.vhd:553
CMX_input_module.Behavioral.spy_write_inhibit_r_SYSTEM_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) spy_write_inhibit_r_SYSTEM_rr_SOURCE
Definition: CMX_input_module.vhd:481
vme_outreg_notri_async.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:22
CMX_input_module.PAR_ERROR_total
out PAR_ERROR_totalstd_logic
Definition: CMX_input_module.vhd:39
CMX_input_module.Behavioral.event_counter_next
unsigned (31 downto 0) event_counter_next
Definition: CMX_input_module.vhd:110
CMX_input_module.Behavioral.vme_local_switch
vme_local_switch
Definition: CMX_input_module.vhd:656
vme_outreg_reg_ro_clock_diff_ratchet_down_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_ratchet_down_counter_0vme_outreg_reg_ro_clock_diff_ratchet_down_counter_0
Definition: CMX_input_module.vhd:1955
BUF_2X24_AT_80_TO_1X96_AT_40.ODATA_first_half
out ODATA_first_halfstd_logic_vector ((numbitsinchan * 2) - 1 downto 0)
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:29
vme_inreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:29
CMX_generic_spy_mem_control_FSM.UNISIM
_library_ UNISIMUNISIM
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:16
CMX_input_module.Behavioral.data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1
arr_16 (numactchan - 1 downto 0) data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1
Definition: CMX_input_module.vhd:646
CMX_data_delay.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_data_delay.vhd:48
BUF_2X24_AT_80_TO_1X96_AT_40
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:25
vme_outreg_notri_async.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:27
vme_inreg_notri.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:33
CMX_input_module.Behavioral.vme_reset_B
std_logic vme_reset_B
Definition: CMX_input_module.vhd:262
CMX_input_module.Behavioral.bit_error_counter_next
arr_ctr_32bit (numactchan - 1 downto 0) bit_error_counter_next
Definition: CMX_input_module.vhd:632
CMX_input_module.Behavioral.bit_error_counter_system
arr_ctr_32bit (numactchan - 1 downto 0) bit_error_counter_system
Definition: CMX_input_module.vhd:642
CMX_input_module.Behavioral.clock_diff_counter_ratchet_down
arr_sig_32bit (numactchan - 1 downto 0) clock_diff_counter_ratchet_down
Definition: CMX_input_module.vhd:123
CMX_data_delay.CLK_40
in CLK_40std_logic
Definition: CMX_data_delay.vhd:31
vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_0vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_0
Definition: CMX_input_module.vhd:1443
CMX_generic_spy_mem_control_FSM.IEEE
_library_ IEEEIEEE
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:11
CMX_input_module.Behavioral.ena_SPY_SYSTEM_individual
std_logic_vector (numactchan - 1 downto 0) ena_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:541
CMX_input_module.Behavioral.any_reset_B
std_logic any_reset_B
Definition: CMX_input_module.vhd:264
Stretch_10.stretched_OUT
out stretched_OUTstd_logic
Definition: Stretch_10.vhd:23
CMX_input_module.Behavioral.par_err_counter_next
arr_ctr_32bit (numactchan - 1 downto 0) par_err_counter_next
Definition: CMX_input_module.vhd:114
CMX_input_module.Behavioral.bit_error_detect
arr_48 (numactchan - 1 downto 0) bit_error_detect
Definition: CMX_input_module.vhd:628
vme_outreg_reg_ro_clock_diff_detect_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_detect_counter_1vme_outreg_reg_ro_clock_diff_detect_counter_1
Definition: CMX_input_module.vhd:1883
CMX_generic_spy_mem_control_FSM.ena
out enastd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:56
CMX_input_module.counter_enable_out
out counter_enable_outstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:41
inst_cmx_data_delay
CMX_data_delay inst_cmx_data_delayinst_cmx_data_delay
Definition: CMX_input_module.vhd:738
CMX_input_module.Behavioral.mem_select_address_SPY_SYSTEM
std_logic_vector (3 downto 0) mem_select_address_SPY_SYSTEM
Definition: CMX_input_module.vhd:513
CMX_input_module.Behavioral.event_counter_s
signed (31 downto 0) event_counter_s
Definition: CMX_input_module.vhd:109
stretch_10_counter_reset
Stretch_10 stretch_10_counter_resetstretch_10_counter_reset
Definition: CMX_input_module.vhd:912
CMX_generic_spy_mem_control_FSM.ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL
ADDR_REG_RW_GENERIC_SPY_MEM_CONTROLinteger :=0
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:26
CMX_input_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_input_module.vhd:45
CMX_input_module.Behavioral.data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE
std_logic_vector (15 downto 0) data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE
Definition: CMX_input_module.vhd:238
vme_outreg_reg_ro_clock_diff_ratchet_up_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_ratchet_up_counter_1vme_outreg_reg_ro_clock_diff_ratchet_up_counter_1
Definition: CMX_input_module.vhd:1940
vme_inreg_notri.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri.vhd:27
CMX_input_module.Behavioral.error_detect_process
error_detect_processCLKPARB(i_mem_source)
Definition: CMX_input_module.vhd:1330
CMX_input_module.Behavioral.spy_write_inhibit_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) spy_write_inhibit_r_SYSTEM
Definition: CMX_input_module.vhd:559
CMX_input_module.Behavioral.start_playback_r_SYSTEM_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) start_playback_r_SYSTEM_r_SOURCE
Definition: CMX_input_module.vhd:501
CMX_input_module.Behavioral.PAR_ERROR_sig_rr_SYSTEM
std_logic_vector (numactchan - 1 downto 0) PAR_ERROR_sig_rr_SYSTEM
Definition: CMX_input_module.vhd:105
CMX_input_module.buf_clk40_m180o
in buf_clk40_m180ostd_logic
Definition: CMX_input_module.vhd:29
CMX_input_module.Behavioral.bit_error_counter
arr_ctr_32bit (numactchan - 1 downto 0) bit_error_counter
Definition: CMX_input_module.vhd:631
CMX_input_module.Behavioral.vme_inreg_notri_async
vme_inreg_notri_async
Definition: CMX_input_module.vhd:200
CMX_input_module.Behavioral.addra_SPY_SYSTEM
std_logic_vector (7 downto 0) addra_SPY_SYSTEM
Definition: CMX_input_module.vhd:512
CMX_input_module
Definition: CMX_input_module.vhd:25
vme_outreg_notri_async.width
widthinteger :=16
Definition: vme_outreg_rtl_notri_async.vhd:19
CMX_input_module.Behavioral.data_from_vme_REG_RW_INPUT_MOD_RESET
std_logic_vector (15 downto 0) data_from_vme_REG_RW_INPUT_MOD_RESET
Definition: CMX_input_module.vhd:254
CMX_data_delay.IDELAYCTRL_RDY
out IDELAYCTRL_RDYstd_logic_vector (num_IDELAYCTRL - 1 downto 0)
Definition: CMX_data_delay.vhd:40
CMX_input_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:61
CMX_input_module.Behavioral.or_all
or_all
Definition: CMX_input_module.vhd:648
CMX_input_module.Behavioral.wea_SPY_SYSTEM_individual
arr_1 (numactchan - 1 downto 0) wea_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:542
CMX_input_module.Behavioral.web_SPY_SOURCE_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) web_SPY_SOURCE_r_SYSTEM
Definition: CMX_input_module.vhd:474
CMX_input_module.Behavioral.ena_SPY_SYSTEM
std_logic ena_SPY_SYSTEM
Definition: CMX_input_module.vhd:510
vme_inreg_notri.width
widthinteger :=16
Definition: vme_inreg_rtl_notri.vhd:22
CMX_input_module.Behavioral.bus_drive_from_below
std_logic_vector (13 + 2 * numactchan - 1 + 5 * numactchan - 1 + 4 * numactchan - 1 + 9 * numactchan - 1 downto 0) bus_drive_from_below)
Definition: CMX_input_module.vhd:666
vme_inreg_notri_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:34
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SOURCE
std_logic port_b_master_inhibit_SPY_SOURCE
Definition: CMX_input_module.vhd:428
CMX_input_module.Behavioral.any_reset_B_synced
std_logic_vector (numactchan - 1 downto 0) any_reset_B_synced
Definition: CMX_input_module.vhd:299
CMX_input_module.P
in Pmat_var (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:27
vme_inreg_notri_async.width
widthinteger :=16
Definition: vme_inreg_rtl_notri_async.vhd:21
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SOURCE_split
std_logic_vector (numactchan - 1 downto 0) port_b_master_inhibit_SPY_SOURCE_split
Definition: CMX_input_module.vhd:430
vme_outreg_reg_ro_clock_diff_duration_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_duration_counter_0vme_outreg_reg_ro_clock_diff_duration_counter_0
Definition: CMX_input_module.vhd:1897
CMX_input_module.Behavioral.bit_error_detect_system
arr_96 (numactchan - 1 downto 0) bit_error_detect_system
Definition: CMX_input_module.vhd:639
vme_outreg_reg_ro_parity_error_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_parity_error_counter_1vme_outreg_reg_ro_parity_error_counter_1
Definition: CMX_input_module.vhd:981
CMX_generic_spy_mem_control_FSM.ADDR_REG_RO_GENERIC_SPY_MEM_STATUS
ADDR_REG_RO_GENERIC_SPY_MEM_STATUSinteger :=0
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:27
CMX_input_module.Behavioral.enb_SPY_SOURCE_rr_SYSTEM
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SOURCE_rr_SYSTEM
Definition: CMX_input_module.vhd:469
CMX_input_module.Behavioral.doutb_SPY_SOURCE_individual
arr_48 (numactchan - 1 downto 0) doutb_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:493
CMX_input_module.Behavioral.ena_SPY_SOURCE
std_logic ena_SPY_SOURCE
Definition: CMX_input_module.vhd:422
CMX_input_module.del_register
in del_registerdel_register_type
Definition: CMX_input_module.vhd:44
vme_outreg_reg_ro_clock_diff_ratchet_down_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_ratchet_down_counter_1vme_outreg_reg_ro_clock_diff_ratchet_down_counter_1
Definition: CMX_input_module.vhd:1969
CMX_generic_spy_mem_control_FSM.ds
in dsstd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:37
vme_inreg_notri.clk
in clkstd_logic
Definition: vme_inreg_rtl_notri.vhd:25
CMX_input_module.Behavioral.ODATA_sig_rr_SYSTEM
arr_4Xword (numactchan - 1 downto 0) ODATA_sig_rr_SYSTEM
Definition: CMX_input_module.vhd:87
CMX_input_module.Behavioral.NDATA
arr_word (numactchan - 1 downto 0) NDATA
Definition: CMX_input_module.vhd:271
CMX_input_module.Behavioral.i_pll_locked
std_logic i_pll_locked
Definition: CMX_input_module.vhd:295
CMX_input_module.Behavioral.enb_SPY_SOURCE
STD_LOGIC enb_SPY_SOURCE
Definition: CMX_input_module.vhd:463
CMX_input_module.Behavioral.start_playback_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) start_playback_r_SYSTEM
Definition: CMX_input_module.vhd:582
CMX_input_module.Behavioral.data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS
arr_16 (numactchan - 1 downto 0) data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS
Definition: CMX_input_module.vhd:504
CMX_input_module.Behavioral.cyclecounter_next
arr_ctr_1bit (numactchan - 1 downto 0) cyclecounter_next
Definition: CMX_input_module.vhd:303
vme_local_switch.data_vme_from_below
in data_vme_from_belowarr_16
--! inputs from local registers and from
Definition: vme_local_switch.vhd:35
CMX_input_module.Behavioral.error_detect_process_system
error_detect_process_systembuf_clk40
Definition: CMX_input_module.vhd:1636
vme_inreg_notri.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:36
CMX_input_module.Behavioral.addra_SPY_SOURCE
std_logic_vector (7 downto 0) addra_SPY_SOURCE
Definition: CMX_input_module.vhd:424
CMX_data_delay.DELAYED_CLKPAR
out DELAYED_CLKPARstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_data_delay.vhd:42
CMX_input_module.Behavioral.PAR_ERROR_sig_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) PAR_ERROR_sig_r_SYSTEM
Definition: CMX_input_module.vhd:104
CMX_input_module.Behavioral.PAR_ERROR_sig
std_logic_vector (numactchan - 1 downto 0) PAR_ERROR_sig
Definition: CMX_input_module.vhd:99
CMX_input_module.Behavioral.start_playback_r_SYSTEM_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) start_playback_r_SYSTEM_rr_SOURCE
Definition: CMX_input_module.vhd:502
CMX_input_module.Behavioral.ODATA_first_half_sig
arr_2Xword (numactchan - 1 downto 0) ODATA_first_half_sig
Definition: CMX_input_module.vhd:89
CMX_input_module.Behavioral.dinb_SPY_SOURCE_individual
arr_48 (numactchan - 1 downto 0) dinb_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:492
CMX_generic_spy_mem_control_FSM.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:40
CMX_input_module.Behavioral.data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS
arr_16 (numactchan - 1 downto 0) data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS
Definition: CMX_input_module.vhd:505
vme_inreg_notri_async.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:30
CMX_input_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:62
CMX_input_module.Behavioral.dinb_SPY_SYSTEM_individual
arr_96 (numactchan - 1 downto 0) dinb_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:570
cmx_input_module_spy_mem_control_fsm_inst
CMX_generic_spy_mem_control_FSM cmx_input_module_spy_mem_control_fsm_instcmx_input_module_spy_mem_control_fsm_inst
Definition: CMX_input_module.vhd:1168
CMX_input_module.Behavioral.enb_SPY_SOURCE_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SOURCE_r_SOURCE
Definition: CMX_input_module.vhd:470
CMX_data_delay.REF_CLK_READY
in REF_CLK_READYstd_logic
Definition: CMX_data_delay.vhd:30
CMX_generic_spy_mem_control_FSM.port_b_master_inhibit
out port_b_master_inhibitstd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:68
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE
Definition: CMX_input_module.vhd:432
CMX_input_module.Behavioral.ch_quiet
std_logic_vector (numactchan - 1 downto 0) ch_quiet
Definition: CMX_input_module.vhd:97
CMX_input_module.Behavioral.dina_SPY_SYSTEM
std_logic_vector (95 downto 0) dina_SPY_SYSTEM
Definition: CMX_input_module.vhd:514
CMX_generic_spy_mem_control_FSM.addra
out addrastd_logic_vector (7 downto 0)
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:58
CMX_input_module.Behavioral.douta_SPY_SYSTEM_individual
arr_96 (numactchan - 1 downto 0) douta_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:545
vme_inreg_notri.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:40
CMX_input_module.Behavioral.NDATA_r_SOURCE
arr_word (numactchan - 1 downto 0) NDATA_r_SOURCE
Definition: CMX_input_module.vhd:274
CMX_input_module.Behavioral.douta_SPY_SOURCE
std_logic_vector (95 downto 0) douta_SPY_SOURCE
Definition: CMX_input_module.vhd:427
CMX_generic_spy_mem_control_FSM.rd_nwr
in rd_nwrstd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:36
vme_inreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri_async.vhd:20
vme_outreg_reg_ro_clock_diff_duration_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_duration_counter_1vme_outreg_reg_ro_clock_diff_duration_counter_1
Definition: CMX_input_module.vhd:1911
vme_outreg_reg_ro_input_mod_counter_enable
vme_outreg_notri_async vme_outreg_reg_ro_input_mod_counter_enablevme_outreg_reg_ro_input_mod_counter_enable
Definition: CMX_input_module.vhd:1072
CMX_input_module.quiet
in quietstd_logic
Definition: CMX_input_module.vhd:48
bufr_inst
bufr bufr_instbufr_inst
Definition: CMX_input_module.vhd:763
CMX_input_module.Behavioral.clock_diff_counter_ratchet_up
arr_sig_32bit (numactchan - 1 downto 0) clock_diff_counter_ratchet_up
Definition: CMX_input_module.vhd:122
vme_inreg_notri
Definition: vme_inreg_rtl_notri.vhd:19
CMX_input_module.Behavioral.data_to_vme_REG_RW_INPUT_MOD_RESET
std_logic_vector (15 downto 0) data_to_vme_REG_RW_INPUT_MOD_RESET
Definition: CMX_input_module.vhd:255
CMX_input_module.Behavioral.vme_inreg_notri
vme_inreg_notri
Definition: CMX_input_module.vhd:181
CMX_input_module.Behavioral.Stretch_10
Stretch_10
Definition: CMX_input_module.vhd:126
Stretch_10.clk
in clkstd_logic
Definition: Stretch_10.vhd:24
CMX_input_module.start_playback
in start_playbackstd_logic
Definition: CMX_input_module.vhd:51
CMX_input_module.Behavioral.douta_SPY_SOURCE_individual
arr_96 (numactchan - 1 downto 0) douta_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:459
CMX_input_module.Behavioral.enb_SPY_SYSTEM_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SYSTEM_r_SYSTEM
Definition: CMX_input_module.vhd:554
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE
Definition: CMX_input_module.vhd:433
CMX_input_module.Behavioral.web_SPY_SOURCE_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) web_SPY_SOURCE_rr_SOURCE
Definition: CMX_input_module.vhd:477
CMX_generic_spy_mem_control_FSM.num_external_RAMS
num_external_RAMSpositive :=1
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:28
CMX_input_module.Behavioral.CMX_generic_spy_mem_control_FSM
CMX_generic_spy_mem_control_FSM
Definition: CMX_input_module.vhd:370
CMX_generic_spy_mem_control_FSM.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:38
CMX_input_module.Behavioral.addrb_SPY_SYSTEM_individual
arr_8 (numactchan - 1 downto 0) addrb_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:569
vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_0vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_0
Definition: CMX_input_module.vhd:1744
buf_inst
BUF_2X24_AT_80_TO_1X96_AT_40 buf_instbuf_inst
Definition: CMX_input_module.vhd:807
CMX_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_input_module.vhd:31
vme_inreg_notri_async.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:25
CMX_input_module.Behavioral.wea_SPY_SOURCE
std_logic wea_SPY_SOURCE
Definition: CMX_input_module.vhd:423
CMX_generic_spy_mem_control_FSM.dina
out dinastd_logic_vector
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:63
CMX_data_delay.CLKPAR
in CLKPARstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_data_delay.vhd:28
CMX_input_module.Behavioral.web_SPY_SOURCE_rr_SYSTEM
std_logic_vector (numactchan - 1 downto 0) web_SPY_SOURCE_rr_SYSTEM
Definition: CMX_input_module.vhd:475
CMX_input_module.Behavioral.web_SPY_SYSTEM_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) web_SPY_SYSTEM_r_SYSTEM
Definition: CMX_input_module.vhd:557
vme_inreg_reg_rw_input_spy_mem_system_start_address
vme_inreg_notri_async vme_inreg_reg_rw_input_spy_mem_system_start_addressvme_inreg_reg_rw_input_spy_mem_system_start_address
Definition: CMX_input_module.vhd:1512
CMX_input_module.counter_values
out counter_valuesstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:42
CMX_input_module.Behavioral.enb_SPY_SOURCE_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SOURCE_rr_SOURCE
Definition: CMX_input_module.vhd:471
CMX_input_module.Behavioral.event_counter
unsigned (31 downto 0) event_counter
Definition: CMX_input_module.vhd:108
or_all.or_all
out or_allstd_logic
Definition: or_all.vhd:35
BUF_2X24_AT_80_TO_1X96_AT_40.PDATA
in PDATAstd_logic_vector (numbitsinchan - 1 downto 0)
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:27
CMX_input_module.Behavioral.spy_source_addr_proc
spy_source_addr_procCLKPARB(i_mem_source)
Definition: CMX_input_module.vhd:1280
CMX_input_module.Behavioral.counter_enable
std_logic_vector (numactchan - 1 downto 0) counter_enable
Definition: CMX_input_module.vhd:298
CMX_input_module.Behavioral.channel_mask
std_logic_vector (numactchan - 1 downto 0) channel_mask
Definition: CMX_input_module.vhd:260
or_all.numbits
numbitsinteger :=2
Definition: or_all.vhd:31
CMX_input_module.Behavioral.web_SPY_SOURCE_split
std_logic_vector (numactchan - 1 downto 0) web_SPY_SOURCE_split
Definition: CMX_input_module.vhd:473
vme_inreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:35
CMX_input_module.Behavioral.PAR_ERROR_unmasked_sig
std_logic_vector (numactchan - 1 downto 0) PAR_ERROR_unmasked_sig
Definition: CMX_input_module.vhd:103
vme_outreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri_async.vhd:28
CMX_input_module.Behavioral.ODATA_first_half_sig_r_mSYSTEM
arr_2Xword (numactchan - 1 downto 0) ODATA_first_half_sig_r_mSYSTEM
Definition: CMX_input_module.vhd:95
CMX_input_module.Behavioral.mem_select_address_SPY_SOURCE
std_logic_vector (3 downto 0) mem_select_address_SPY_SOURCE
Definition: CMX_input_module.vhd:425
vme_local_switch.data_vme_up
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
Definition: vme_local_switch.vhd:24
CMX_input_module.Behavioral.bit_error_latch_system
arr_24 (numactchan - 1 downto 0) bit_error_latch_system
Definition: CMX_input_module.vhd:640
vme_outreg_reg_ro_input_spy_mem_system_check_error_1
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_system_check_error_1vme_outreg_reg_ro_input_spy_mem_system_check_error_1
Definition: CMX_input_module.vhd:1730
vme_inreg_async_reg_rw_input_mod_reset
vme_inreg_notri_async vme_inreg_async_reg_rw_input_mod_resetvme_inreg_async_reg_rw_input_mod_reset
Definition: CMX_input_module.vhd:1046
BUF_2X24_AT_80_TO_1X96_AT_40.PAR_ERROR
out PAR_ERRORstd_logic
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:33
vme_inreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri_async.vhd:32
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SYSTEM_split
std_logic_vector (numactchan - 1 downto 0) port_b_master_inhibit_SPY_SYSTEM_split
Definition: CMX_input_module.vhd:518
vme_outreg_reg_ro_clock_detect_counter
vme_outreg_notri_async vme_outreg_reg_ro_clock_detect_countervme_outreg_reg_ro_clock_detect_counter
Definition: CMX_input_module.vhd:1854
CMX_input_module.Behavioral.counter_reset_rr_SYSTEM
std_logic_vector (numactchan - 1 downto 0) counter_reset_rr_SYSTEM
Definition: CMX_input_module.vhd:133
CMX_input_module.Behavioral.DATA24
arr_word (numactchan - 1 downto 0) DATA24
Definition: CMX_input_module.vhd:71
CMX_generic_spy_mem_control_FSM.wea
out weastd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:57
CMX_input_module.Behavioral.web_SPY_SOURCE_individual
arr_1 (numactchan - 1 downto 0) web_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:486
vme_outreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:26
vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_1vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_1
Definition: CMX_input_module.vhd:1758
CMX_input_module.Behavioral.DELAYED_DATA24_reg
arr_word (numactchan - 1 downto 0) DELAYED_DATA24_reg
Definition: CMX_input_module.vhd:74
CMX_data_delay.upload_delays
in upload_delaysstd_logic
Definition: CMX_data_delay.vhd:35
vme_outreg_reg_ro_input_spy_mem_system_check_error_0
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_system_check_error_0vme_outreg_reg_ro_input_spy_mem_system_check_error_0
Definition: CMX_input_module.vhd:1715
vme_local_switch
Definition: vme_local_switch.vhd:22
vme_outreg_notri_async
Definition: vme_outreg_rtl_notri_async.vhd:16
CMX_generic_spy_mem_control_FSM
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:23
CMX_input_module.Behavioral.doutb_SPY_SYSTEM_individual
arr_4Xword (numactchan - 1 downto 0) doutb_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:571
vme_local_switch.bus_drive_up
out bus_drive_upstd_logic
or of all bus drive requests from below
Definition: vme_local_switch.vhd:38
vme_outreg_reg_ro_input_spy_mem_source_check_error_1
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_source_check_error_1vme_outreg_reg_ro_input_spy_mem_source_check_error_1
Definition: CMX_input_module.vhd:1429
CMX_input_module.Behavioral.blk_mem_A8x96_B8x96
blk_mem_A8x96_B8x96
Definition: CMX_input_module.vhd:522
CMX_input_module.Behavioral.data_from_vme_REG_RW_COUNTER_RESET
std_logic_vector (15 downto 0) data_from_vme_REG_RW_COUNTER_RESET
Definition: CMX_input_module.vhd:233
CMX_input_module.Behavioral.ODATA_sig_r_SYSTEM
arr_4Xword (numactchan - 1 downto 0) ODATA_sig_r_SYSTEM
Definition: CMX_input_module.vhd:83
CMX_input_module.Behavioral.start_playback_rr_SYSTEM
std_logic_vector (numactchan - 1 downto 0) start_playback_rr_SYSTEM
Definition: CMX_input_module.vhd:583
CMX_input_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:60
CMX_input_module.Behavioral.clock_detect_counter
arr_ctr_16bit (numactchan - 1 downto 0) clock_detect_counter
Definition: CMX_input_module.vhd:305
CMX_input_module.ncs
in ncsstd_logic
Definition: CMX_input_module.vhd:57
CMX_input_module.Behavioral.web_SPY_SOURCE_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) web_SPY_SOURCE_r_SOURCE
Definition: CMX_input_module.vhd:476
CMX_input_module.Behavioral.enb_SPY_SYSTEM_individual
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:563
vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_1vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_1
Definition: CMX_input_module.vhd:1457
CMX_input_module.Behavioral.counter_reset_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) counter_reset_r_SYSTEM
Definition: CMX_input_module.vhd:133
CMX_generic_spy_mem_control_FSM.mem_select_address
out mem_select_addressstd_logic_vector (addr_port_width (num_external_RAMS) - 1 downto 0)
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:60
CMX_data_delay.rd_nwr
in rd_nwrstd_logic
Definition: CMX_data_delay.vhd:46
CMX_input_module.ODATA_first_half
out ODATA_first_halfarr_2Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:35
CMX_input_module.Behavioral.spy_write_inhibit_rr_SYSTEM
std_logic_vector (numactchan - 1 downto 0) spy_write_inhibit_rr_SYSTEM
Definition: CMX_input_module.vhd:560
CMX_input_module.Behavioral.backplane_events_counter
arr_ctr_32bit (numactchan - 1 downto 0) backplane_events_counter
Definition: CMX_input_module.vhd:116
vme_outreg_reg_ro_input_spy_mem_source_check_error_0
vme_outreg_notri_async vme_outreg_reg_ro_input_spy_mem_source_check_error_0vme_outreg_reg_ro_input_spy_mem_source_check_error_0
Definition: CMX_input_module.vhd:1414
CMX_input_module.Behavioral.enb_SPY_SOURCE_split
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SOURCE_split
Definition: CMX_input_module.vhd:467
CMX_input_module.Behavioral.web_SPY_SYSTEM
STD_LOGIC web_SPY_SYSTEM
Definition: CMX_input_module.vhd:550
vme_inreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri.vhd:21
CMX_input_module.Behavioral.data_to_vme_REG_RW_COUNTER_RESET
std_logic_vector (15 downto 0) data_to_vme_REG_RW_COUNTER_RESET
Definition: CMX_input_module.vhd:236
CMX_input_module.Behavioral.PDATA
arr_word (numactchan - 1 downto 0) PDATA
Definition: CMX_input_module.vhd:270
CMX_input_module.Behavioral.DELAYED_CLKPAR
STD_LOGIC_VECTOR (numactchan - 1 downto 0) DELAYED_CLKPAR
Definition: CMX_input_module.vhd:281
CMX_input_module.Behavioral.addrb_SPY_SYSTEM_counter
arr_ctr_8bit (numactchan - 1 downto 0) addrb_SPY_SYSTEM_counter
Definition: CMX_input_module.vhd:577
CMX_input_module.Behavioral.clock_diff_counter
arr_sig_32bit (numactchan - 1 downto 0) clock_diff_counter
Definition: CMX_input_module.vhd:120
CMX_generic_spy_mem_control_FSM.work
_library_ workwork
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:19
vme_outreg_reg_ro_clock_diff_detect_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_clock_diff_detect_counter_0vme_outreg_reg_ro_clock_diff_detect_counter_0
Definition: CMX_input_module.vhd:1869
or_par
or_all or_paror_par
Definition: CMX_input_module.vhd:862
CMX_data_delay.ds
in dsstd_logic
Definition: CMX_data_delay.vhd:47
CMX_input_module.Behavioral.ena_SPY_SOURCE_individual
std_logic_vector (numactchan - 1 downto 0) ena_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:455
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SYSTEM
std_logic port_b_master_inhibit_SPY_SYSTEM
Definition: CMX_input_module.vhd:516
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SOURCE_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) port_b_master_inhibit_SPY_SOURCE_r_SYSTEM
Definition: CMX_input_module.vhd:431
CMX_input_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_input_module.vhd:54
Stretch_10
Definition: Stretch_10.vhd:20
CMX_input_module.Behavioral.counter_reset_rr_SYSTEM_r_SOURCE
std_logic_vector (numactchan - 1 downto 0) counter_reset_rr_SYSTEM_r_SOURCE
Definition: CMX_input_module.vhd:133
CMX_input_module.Behavioral.data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0
arr_16 (numactchan - 1 downto 0) data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0
Definition: CMX_input_module.vhd:634
vme_inreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:31
CMX_input_module.Behavioral.port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM
Definition: CMX_input_module.vhd:519
vme_inreg_reg_rw_input_spy_mem_source_start_address
vme_inreg_notri_async vme_inreg_reg_rw_input_spy_mem_source_start_addressvme_inreg_reg_rw_input_spy_mem_source_start_address
Definition: CMX_input_module.vhd:1252
vme_outreg_reg_ro_parity_error_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_parity_error_counter_0vme_outreg_reg_ro_parity_error_counter_0
Definition: CMX_input_module.vhd:966
or_all.DATA
in DATAstd_logic_vector (numbits - 1 downto 0)
Definition: or_all.vhd:34
CMX_data_delay.del_register
in del_registerdel_register_type
Definition: CMX_data_delay.vhd:32
CMX_input_module.Behavioral.bit_error_counter_system_next
arr_ctr_32bit (numactchan - 1 downto 0) bit_error_counter_system_next
Definition: CMX_input_module.vhd:643
CMX_input_module.Behavioral.mode_control_SPY_SOURCE
std_logic_vector (3 downto 0) mode_control_SPY_SOURCE
Definition: CMX_input_module.vhd:421
vme_inreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:37
CMX_input_module.Behavioral.data_vme_from_below
arr_16 (13 + 2 * numactchan - 1 + 5 * numactchan - 1 + 4 * numactchan - 1 + 9 * numactchan - 1 downto 0) data_vme_from_below)
Definition: CMX_input_module.vhd:665
CMX_input_module.Behavioral.bit_error_latch
arr_24 (numactchan - 1 downto 0) bit_error_latch
Definition: CMX_input_module.vhd:629
BUF_2X24_AT_80_TO_1X96_AT_40.counter_enable
in counter_enablestd_logic
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:32
vme_outreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:23
BUF_2X24_AT_80_TO_1X96_AT_40.ODATA
out ODATAstd_logic_vector ((numbitsinchan * 4) - 1 downto 0)
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:28
CMX_input_module.Behavioral.wea_SPY_SOURCE_individual
arr_1 (numactchan - 1 downto 0) wea_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:456
CMX_input_module.Behavioral.enb_SPY_SYSTEM
STD_LOGIC enb_SPY_SYSTEM
Definition: CMX_input_module.vhd:549
CMX_input_module.Behavioral.addrb_SPY_SOURCE_counter
arr_ctr_9bit (numactchan - 1 downto 0) addrb_SPY_SOURCE_counter
Definition: CMX_input_module.vhd:497
vme_inreg_notri_async.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:27
vme_inreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:26
CMX_input_module.Behavioral.mode_control_SPY_SYSTEM
std_logic_vector (3 downto 0) mode_control_SPY_SYSTEM
Definition: CMX_input_module.vhd:509
CMX_input_module.Behavioral.local_buf_master_inhibit
local_buf_master_inhibitbuf_clk40,pll_locked
Definition: CMX_input_module.vhd:1304
CMX_input_module.Behavioral.backplane_events_counter_next
arr_ctr_32bit (numactchan - 1 downto 0) backplane_events_counter_next
Definition: CMX_input_module.vhd:118
vme_inreg_notri_async.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:31
CMX_generic_spy_mem_control_FSM.ncs
in ncsstd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:35
CMX_input_module.Behavioral.counter_reset_rr_SYSTEM_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) counter_reset_rr_SYSTEM_rr_SOURCE
Definition: CMX_input_module.vhd:133
CMX_input_module.Behavioral.any_reset_B_synced_rr_SOURCE
std_logic_vector (numactchan - 1 downto 0) any_reset_B_synced_rr_SOURCE
Definition: CMX_input_module.vhd:300
CMX_input_module.Behavioral.clkb_SPY_SYSTEM_individual
std_logic_vector (numactchan - 1 downto 0) clkb_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:546
CMX_input_module.Behavioral.web_SPY_SYSTEM_individual
arr_1 (numactchan - 1 downto 0) web_SPY_SYSTEM_individual
Definition: CMX_input_module.vhd:564
CMX_data_delay.DELAYED_DATA24
out DELAYED_DATA24arr_word (numactchan - 1 downto 0)
Definition: CMX_data_delay.vhd:41
CMX_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_input_module.vhd:28
CMX_input_module.Behavioral.douta_SPY_SYSTEM
std_logic_vector (95 downto 0) douta_SPY_SYSTEM
Definition: CMX_input_module.vhd:515
vme_inreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri.vhd:34
CMX_input_module.Behavioral.ODATA_first_half_unmasked_sig
arr_2Xword (numactchan - 1 downto 0) ODATA_first_half_unmasked_sig
Definition: CMX_input_module.vhd:92
CMX_generic_spy_mem_control_FSM.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:39
CMX_data_delay.REF_CLK_200
in REF_CLK_200std_logic
Definition: CMX_data_delay.vhd:29
CMX_input_module.Behavioral.pcount
pcountCLKPARB(channel)
Definition: CMX_input_module.vhd:1138
vme_inreg_reg_rw_counter_reset
vme_inreg_notri vme_inreg_reg_rw_counter_resetvme_inreg_reg_rw_counter_reset
Definition: CMX_input_module.vhd:892
CMX_input_module.bus_drive
out bus_drivestd_logic
Definition: CMX_input_module.vhd:63
CMX_input_module.Behavioral.ODATA_sig
arr_4Xword (numactchan - 1 downto 0) ODATA_sig
Definition: CMX_input_module.vhd:79
CMX_generic_spy_mem_control_FSM.douta
in doutastd_logic_vector
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:64
vme_inreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri.vhd:28
CMX_input_module.Behavioral.counter_reset
std_logic counter_reset
Definition: CMX_input_module.vhd:125
vme_inreg_async_reg_rw_backplane_input_channel_mask
vme_inreg_notri_async vme_inreg_async_reg_rw_backplane_input_channel_maskvme_inreg_async_reg_rw_backplane_input_channel_mask
Definition: CMX_input_module.vhd:871
CMX_input_module.Behavioral.vme_outreg_notri_async
vme_outreg_notri_async
Definition: CMX_input_module.vhd:166
CMX_input_module.Behavioral.CLKPAR
STD_LOGIC_VECTOR (numactchan - 1 downto 0) CLKPAR
Definition: CMX_input_module.vhd:277
CMX_VME_defs
test registers
Definition: CMX_VME_defs.vhd:13
CMX_input_module.Behavioral.data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1
arr_16 (numactchan - 1 downto 0) data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1
Definition: CMX_input_module.vhd:635
BUF_2X24_AT_80_TO_1X96_AT_40.cyclecounter
in cyclecounterunsigned (0 downto 0)
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:31
CMX_input_module.Behavioral.enb_SPY_SOURCE_r_SYSTEM
std_logic_vector (numactchan - 1 downto 0) enb_SPY_SOURCE_r_SYSTEM
Definition: CMX_input_module.vhd:468
CMX_generic_spy_mem_control_FSM.clk
in clkstd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:33
vme_outreg_reg_ro_ev_counter_1
vme_outreg_notri_async vme_outreg_reg_ro_ev_counter_1vme_outreg_reg_ro_ev_counter_1
Definition: CMX_input_module.vhd:932
vme_outreg_reg_ro_ev_counter_0
vme_outreg_notri_async vme_outreg_reg_ro_ev_counter_0vme_outreg_reg_ro_ev_counter_0
Definition: CMX_input_module.vhd:918
blk_mem_a8x96_b9x48_spy_source
blk_mem_a8x96_b9x48 blk_mem_a8x96_b9x48_spy_sourceblk_mem_a8x96_b9x48_spy_source
Definition: CMX_input_module.vhd:1218
CMX_input_module.Behavioral.local_buf_master_inhibit_system
local_buf_master_inhibit_systembuf_clk40,pll_locked
Definition: CMX_input_module.vhd:1611
vme_outreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri_async.vhd:18
cmx_input_module_spy_mem_control_fsm_inst_system
CMX_generic_spy_mem_control_FSM cmx_input_module_spy_mem_control_fsm_inst_systemcmx_input_module_spy_mem_control_fsm_inst_system
Definition: CMX_input_module.vhd:1486
vme_outreg_notri_async.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:24
CMX_input_module.Behavioral.addrb_SPY_SOURCE_individual
arr_9 (numactchan - 1 downto 0) addrb_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:491
CMX_input_module.Behavioral.wea_SPY_SYSTEM
std_logic wea_SPY_SYSTEM
Definition: CMX_input_module.vhd:511
CMX_data_delay.DATA24
in DATA24arr_word (numactchan - 1 downto 0)
Definition: CMX_data_delay.vhd:27
vme_inreg_notri.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:32
iddr_inst
iddr iddr_instiddr_inst
Definition: CMX_input_module.vhd:784
CMX_input_module.Behavioral.data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0
arr_16 (numactchan - 1 downto 0) data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0
Definition: CMX_input_module.vhd:645
CMX_input_module.Behavioral.clock_diff_duration_counter
arr_ctr_32bit (numactchan - 1 downto 0) clock_diff_duration_counter
Definition: CMX_input_module.vhd:121
vme_outreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:30
CMX_input_module.Behavioral.data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK
std_logic_vector (15 downto 0) data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK
Definition: CMX_input_module.vhd:258
CMX_generic_spy_mem_control_FSM.mode_control
out mode_controlstd_logic_vector (3 downto 0)
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:43
CMX_input_module.Behavioral.clkb_SPY_SOURCE_individual
std_logic_vector (numactchan - 1 downto 0) clkb_SPY_SOURCE_individual
Definition: CMX_input_module.vhd:460
Stretch_10.unstretched_IN
in unstretched_INstd_logic
Definition: Stretch_10.vhd:22
CMX_input_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_input_module.vhd:30
CMX_input_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_input_module.vhd:58
CMX_input_module.Behavioral.ODATA_unmasked_sig
arr_4Xword (numactchan - 1 downto 0) ODATA_unmasked_sig
Definition: CMX_input_module.vhd:82
CMX_data_delay.bus_drive
out bus_drivestd_logic
Definition: CMX_data_delay.vhd:51
vme_inreg_notri.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri.vhd:29
CMX_input_module.Behavioral.web_SPY_SYSTEM_split
std_logic_vector (numactchan - 1 downto 0) web_SPY_SYSTEM_split
Definition: CMX_input_module.vhd:556
vme_local_switch.bus_drive_from_below
in bus_drive_from_belowstd_logic_vector
Definition: vme_local_switch.vhd:40
BUF_2X24_AT_80_TO_1X96_AT_40.NDATA
in NDATAstd_logic_vector (numbitsinchan - 1 downto 0)
Definition: BUF_2X24_AT_80_TO_1X96_AT_40.vhd:27
vme_inreg_notri_async
Definition: vme_inreg_rtl_notri_async.vhd:18
CMX_input_module.Behavioral.backplane_events_counter_s
arr_sig_32bit (numactchan - 1 downto 0) backplane_events_counter_s
Definition: CMX_input_module.vhd:117
CMX_data_delay
Definition: CMX_data_delay.vhd:25
CMX_input_module.Behavioral.keep
string keep
Definition: CMX_input_module.vhd:669
CMX_input_module.Behavioral.data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK
std_logic_vector (15 downto 0) data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK
Definition: CMX_input_module.vhd:257
CMX_input_module.Behavioral.web_SPY_SOURCE
STD_LOGIC web_SPY_SOURCE
Definition: CMX_input_module.vhd:464
CMX_generic_spy_mem_control_FSM.bus_drive
out bus_drivestd_logic
Definition: CMX_generic_module_spy_mem_control_FSM.vhd:41