Behavioral Architecture Reference

Processes
PROCESS_20	( buf_clk40_m180o )
PROCESS_21	( buf_clk40 )
PROCESS_22	( buf_clk40 )
PROCESS_23	( buf_clk40 , any_reset_B )
pcount	( CLKPARB (channel) )
PROCESS_24	( CLKPARB (channel) , any_reset_B )
PROCESS_25	( CLKPARB (i_mem_source) , pll_locked )
PROCESS_26	( CLKPARB (i_mem_source) )
PROCESS_27	( CLKPARB (i_mem_source) , pll_locked )
spy_source_addr_proc	( CLKPARB (i_mem_source) )
local_buf_master_inhibit	( buf_clk40 , pll_locked )
error_detect_process	( CLKPARB (i_mem_source) )
PROCESS_28	( CLKPARB (i_mem_source) )
PROCESS_29	( CLKPARB (i_mem_source) , pll_locked )
PROCESS_30	( buf_clk40 )
PROCESS_31	( buf_clk40 , pll_locked )
PROCESS_32	( CLKPARB (i_mem_source) )
PROCESS_33	( buf_clk40 , pll_locked )
PROCESS_34	( buf_clk40 )
PROCESS_35	( buf_clk40 , pll_locked )
spy_source_addr_proc	( buf_clk40 )
local_buf_master_inhibit_system	( buf_clk40 , pll_locked )
error_detect_process_system	( buf_clk40 )
PROCESS_36	( buf_clk40 , pll_locked )
PROCESS_37	( buf_clk40 )
PROCESS_38	( CLKPARB (channel) )
PROCESS_39	( CLKPARB (channel) )
PROCESS_40	( buf_clk40 )
PROCESS_41	( buf_clk40 )
PROCESS_42	( buf_clk40 )

Components
Stretch_10	<Entity Stretch_10>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>
CMX_data_delay	<Entity CMX_data_delay>
BUF_2X24_AT_80_TO_1X96_AT_40	<Entity BUF_2X24_AT_80_TO_1X96_AT_40>
DEBOUNCE_10
CMX_generic_spy_mem_control_FSM	<Entity CMX_generic_spy_mem_control_FSM>
blk_mem_A8x96_B9x48
blk_mem_A8x96_B8x96
or_all	<Entity or_all>
vme_local_switch	<Entity vme_local_switch>

Signals
DATA24	arr_word ( numactchan - 1 downto 0 )
DELAYED_DATA24	arr_word ( numactchan - 1 downto 0 )
DELAYED_DATA24_reg	arr_word ( numactchan - 1 downto 0 )
ODATA_sig	arr_4Xword ( numactchan - 1 downto 0 )
ODATA_unmasked_sig	arr_4Xword ( numactchan - 1 downto 0 )
ODATA_sig_r_SYSTEM	arr_4Xword ( numactchan - 1 downto 0 )
ODATA_sig_rr_SYSTEM	arr_4Xword ( numactchan - 1 downto 0 )
ODATA_first_half_sig	arr_2Xword ( numactchan - 1 downto 0 )
ODATA_first_half_unmasked_sig	arr_2Xword ( numactchan - 1 downto 0 )
ODATA_first_half_sig_r_mSYSTEM	arr_2Xword ( numactchan - 1 downto 0 )
ch_quiet	std_logic_vector ( numactchan - 1 downto 0 )
PAR_ERROR_sig	std_logic_vector ( numactchan - 1 downto 0 )
PAR_ERROR_sig_r_SYSTEM_ORed	std_logic
PAR_ERROR_unmasked_sig	std_logic_vector ( numactchan - 1 downto 0 )
PAR_ERROR_sig_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
PAR_ERROR_sig_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
event_counter	unsigned ( 31 downto 0 )
event_counter_s	signed ( 31 downto 0 )
event_counter_next	unsigned ( 31 downto 0 )
par_err_counter	arr_ctr_32bit ( numactchan - 1 downto 0 )
par_err_counter_next	arr_ctr_32bit ( numactchan - 1 downto 0 )
backplane_events_counter	arr_ctr_32bit ( numactchan - 1 downto 0 )
backplane_events_counter_s	arr_sig_32bit ( numactchan - 1 downto 0 )
backplane_events_counter_next	arr_ctr_32bit ( numactchan - 1 downto 0 )
clock_diff_counter	arr_sig_32bit ( numactchan - 1 downto 0 )
clock_diff_duration_counter	arr_ctr_32bit ( numactchan - 1 downto 0 )
clock_diff_counter_ratchet_up	arr_sig_32bit ( numactchan - 1 downto 0 )
clock_diff_counter_ratchet_down	arr_sig_32bit ( numactchan - 1 downto 0 )
counter_reset	std_logic
counter_reset_unstretched	std_logic
counter_reset_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
data_from_vme_REG_RW_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_INPUT_MOD_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_INPUT_MOD_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK	std_logic_vector ( 15 downto 0 )
channel_mask	std_logic_vector ( numactchan - 1 downto 0 )
vme_reset_B	std_logic
any_reset_B	std_logic
PDATA	arr_word ( numactchan - 1 downto 0 )
NDATA	arr_word ( numactchan - 1 downto 0 )
PDATA_r_SOURCE	arr_word ( numactchan - 1 downto 0 )
NDATA_r_SOURCE	arr_word ( numactchan - 1 downto 0 )
CLKPAR	STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )
DELAYED_CLKPAR	STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )
CLKPARB	STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )
CLKPAR_DATA	STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )
i_pll_locked	std_logic
counter_enable	std_logic_vector ( numactchan - 1 downto 0 )
any_reset_B_s1	std_logic_vector ( numactchan - 1 downto 0 )
any_reset_B_synced	std_logic_vector ( numactchan - 1 downto 0 )
any_reset_B_synced_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
any_reset_B_synced_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
cyclecounter	arr_ctr_1bit ( numactchan - 1 downto 0 )
cyclecounter_next	arr_ctr_1bit ( numactchan - 1 downto 0 )
clock_detect_counter	arr_ctr_16bit ( numactchan - 1 downto 0 )
clock_detect_counter_next	arr_ctr_16bit ( numactchan - 1 downto 0 )
mode_control_SPY_SOURCE	std_logic_vector ( 3 downto 0 )
ena_SPY_SOURCE	std_logic
wea_SPY_SOURCE	std_logic
addra_SPY_SOURCE	std_logic_vector ( 7 downto 0 )
mem_select_address_SPY_SOURCE	std_logic_vector ( 3 downto 0 )
dina_SPY_SOURCE	std_logic_vector ( 95 downto 0 )
douta_SPY_SOURCE	std_logic_vector ( 95 downto 0 )
port_b_master_inhibit_SPY_SOURCE	std_logic
port_b_master_inhibit_SPY_SOURCE_split	std_logic_vector ( numactchan - 1 downto 0 )
port_b_master_inhibit_SPY_SOURCE_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
ena_SPY_SOURCE_individual	std_logic_vector ( numactchan - 1 downto 0 )
wea_SPY_SOURCE_individual	arr_1 ( numactchan - 1 downto 0 )
douta_SPY_SOURCE_individual	arr_96 ( numactchan - 1 downto 0 )
clkb_SPY_SOURCE_individual	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SOURCE	STD_LOGIC
web_SPY_SOURCE	STD_LOGIC
enb_SPY_SOURCE_split	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SOURCE_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SOURCE_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SOURCE_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SOURCE_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SOURCE_split	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SOURCE_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SOURCE_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SOURCE_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SOURCE_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
spy_write_inhibit_r_SYSTEM_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
spy_write_inhibit_r_SYSTEM_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SOURCE_individual	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SOURCE_individual	arr_1 ( numactchan - 1 downto 0 )
addrb_SPY_SOURCE_individual	arr_9 ( numactchan - 1 downto 0 )
dinb_SPY_SOURCE_individual	arr_48 ( numactchan - 1 downto 0 )
doutb_SPY_SOURCE_individual	arr_48 ( numactchan - 1 downto 0 )
addrb_SPY_SOURCE_counter	arr_ctr_9bit ( numactchan - 1 downto 0 )
start_playback_r_SYSTEM_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
start_playback_r_SYSTEM_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS	arr_16 ( numactchan - 1 downto 0 )
data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS	arr_16 ( numactchan - 1 downto 0 )
mode_control_SPY_SYSTEM	std_logic_vector ( 3 downto 0 )
ena_SPY_SYSTEM	std_logic
wea_SPY_SYSTEM	std_logic
addra_SPY_SYSTEM	std_logic_vector ( 7 downto 0 )
mem_select_address_SPY_SYSTEM	std_logic_vector ( 3 downto 0 )
dina_SPY_SYSTEM	std_logic_vector ( 95 downto 0 )
douta_SPY_SYSTEM	std_logic_vector ( 95 downto 0 )
port_b_master_inhibit_SPY_SYSTEM	std_logic
port_b_master_inhibit_SPY_SYSTEM_split	std_logic_vector ( numactchan - 1 downto 0 )
port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
ena_SPY_SYSTEM_individual	std_logic_vector ( numactchan - 1 downto 0 )
wea_SPY_SYSTEM_individual	arr_1 ( numactchan - 1 downto 0 )
douta_SPY_SYSTEM_individual	arr_96 ( numactchan - 1 downto 0 )
clkb_SPY_SYSTEM_individual	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SYSTEM	STD_LOGIC
web_SPY_SYSTEM	STD_LOGIC
enb_SPY_SYSTEM_split	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SYSTEM_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SYSTEM_split	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SYSTEM_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
spy_write_inhibit_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
spy_write_inhibit_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
enb_SPY_SYSTEM_individual	std_logic_vector ( numactchan - 1 downto 0 )
web_SPY_SYSTEM_individual	arr_1 ( numactchan - 1 downto 0 )
addrb_SPY_SYSTEM_individual	arr_8 ( numactchan - 1 downto 0 )
dinb_SPY_SYSTEM_individual	arr_96 ( numactchan - 1 downto 0 )
doutb_SPY_SYSTEM_individual	arr_4Xword ( numactchan - 1 downto 0 )
addrb_SPY_SYSTEM_counter	arr_ctr_8bit ( numactchan - 1 downto 0 )
start_playback_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
start_playback_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
bit_error_detect	arr_48 ( numactchan - 1 downto 0 )
bit_error_latch	arr_24 ( numactchan - 1 downto 0 )
bit_error_counter	arr_ctr_32bit ( numactchan - 1 downto 0 )
bit_error_counter_next	arr_ctr_32bit ( numactchan - 1 downto 0 )
data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0	arr_16 ( numactchan - 1 downto 0 )
data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1	arr_16 ( numactchan - 1 downto 0 )
bit_error_detect_system	arr_96 ( numactchan - 1 downto 0 )
bit_error_latch_system	arr_24 ( numactchan - 1 downto 0 )
bit_error_counter_system	arr_ctr_32bit ( numactchan - 1 downto 0 )
bit_error_counter_system_next	arr_ctr_32bit ( numactchan - 1 downto 0 )
data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0	arr_16 ( numactchan - 1 downto 0 )
data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1	arr_16 ( numactchan - 1 downto 0 )
data_vme_from_below	arr_16 ( 13 + 2 * numactchan - 1 + 5 * numactchan - 1 + 4 * numactchan - 1 + 9 * numactchan - 1 downto 0 )
bus_drive_from_below	std_logic_vector ( 13 + 2 * numactchan - 1 + 5 * numactchan - 1 + 4 * numactchan - 1 + 9 * numactchan - 1 downto 0 )

Attributes
keep	string
keep	enb_SPY_SOURCE_r_SOURCE , web_SPY_SOURCE_r_SOURCE , enb_SPY_SOURCE_split , web_SPY_SOURCE_split , enb_SPY_SOURCE_rr_SOURCE , web_SPY_SOURCE_rr_SOURCE , enb_SPY_SOURCE_r_SYSTEM , web_SPY_SOURCE_r_SYSTEM , enb_SPY_SOURCE_rr_SYSTEM , web_SPY_SOURCE_rr_SYSTEM , port_b_master_inhibit_SPY_SOURCE_split , port_b_master_inhibit_SPY_SOURCE_r_SYSTEM , port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE , port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE , counter_reset_r_SYSTEM , counter_reset_rr_SYSTEM , counter_reset_rr_SYSTEM_r_SOURCE , any_reset_B_synced_r_SOURCE , any_reset_B_synced_rr_SOURCE , ODATA_sig_r_SYSTEM : signal is " TRUE "

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
inst_cmx_data_delay	CMX_data_delay <Entity CMX_data_delay>
bufr_inst	bufr
iddr_inst	iddr
buf_inst	BUF_2X24_AT_80_TO_1X96_AT_40 <Entity BUF_2X24_AT_80_TO_1X96_AT_40>
or_par	or_all <Entity or_all>
vme_inreg_async_reg_rw_backplane_input_channel_mask	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_inreg_reg_rw_counter_reset	vme_inreg_notri <Entity vme_inreg_notri>
stretch_10_counter_reset	Stretch_10 <Entity Stretch_10>
vme_outreg_reg_ro_ev_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_ev_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_parity_error_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_parity_error_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_inreg_async_reg_rw_input_mod_reset	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_outreg_reg_ro_input_mod_counter_enable	vme_outreg_notri_async <Entity vme_outreg_notri_async>
cmx_input_module_spy_mem_control_fsm_inst	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
blk_mem_a8x96_b9x48_spy_source	blk_mem_a8x96_b9x48
vme_inreg_reg_rw_input_spy_mem_source_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_source_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_source_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
cmx_input_module_spy_mem_control_fsm_inst_system	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
vme_inreg_reg_rw_input_spy_mem_system_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>
blk_mem_a8x96_b8x96_spy_system	blk_mem_a8x96_b8x96
vme_outreg_reg_ro_input_spy_mem_system_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_system_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_detect_counter	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_detect_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_detect_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_duration_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_duration_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_ratchet_up_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_ratchet_up_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_ratchet_down_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_clock_diff_ratchet_down_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>

Detailed Description

Definition at line 68 of file CMX_input_module.vhd.

Member Function Documentation

error_detect_process (   CLKPARB (i_mem_source)   )

Process

Definition at line 1330 of file CMX_input_module.vhd.

error_detect_process_system (   buf_clk40   )

Process

Definition at line 1636 of file CMX_input_module.vhd.

local_buf_master_inhibit (   buf_clk40 ,   pll_locked   )

Process

Definition at line 1304 of file CMX_input_module.vhd.

local_buf_master_inhibit_system (   buf_clk40 ,   pll_locked   )

Process

Definition at line 1611 of file CMX_input_module.vhd.

pcount (   CLKPARB (channel)   )

Process

Definition at line 1138 of file CMX_input_module.vhd.

PROCESS_20

(

buf_clk40_m180o

)

Definition at line 834 of file CMX_input_module.vhd.

PROCESS_21

(

buf_clk40

)

Definition at line 948 of file CMX_input_module.vhd.

PROCESS_22

(

buf_clk40

)

Definition at line 996 of file CMX_input_module.vhd.

PROCESS_23	(		buf_clk40 ,
			any_reset_B
	)

Definition at line 1103 of file CMX_input_module.vhd.

PROCESS_24 (   CLKPARB (channel) ,   any_reset_B   )

Process

Definition at line 1149 of file CMX_input_module.vhd.

PROCESS_25	(		CLKPARB (i_mem_source) ,
			pll_locked
	)

Definition at line 1201 of file CMX_input_module.vhd.

PROCESS_26 (   CLKPARB (i_mem_source)   )

Process

Definition at line 1211 of file CMX_input_module.vhd.

PROCESS_27	(		CLKPARB (i_mem_source) ,
			pll_locked
	)

Definition at line 1269 of file CMX_input_module.vhd.

PROCESS_28 (   CLKPARB (i_mem_source)   )

Process

Definition at line 1355 of file CMX_input_module.vhd.

PROCESS_29 (   CLKPARB (i_mem_source) ,   pll_locked   )

Process

Definition at line 1361 of file CMX_input_module.vhd.

PROCESS_30 (   buf_clk40   )

Process

Definition at line 1373 of file CMX_input_module.vhd.

PROCESS_31 (   buf_clk40 ,   pll_locked   )

Process

Definition at line 1379 of file CMX_input_module.vhd.

PROCESS_32 (   CLKPARB (i_mem_source)   )

Process

Definition at line 1393 of file CMX_input_module.vhd.

PROCESS_33	(		buf_clk40 ,
			pll_locked
	)

Definition at line 1535 of file CMX_input_module.vhd.

PROCESS_34 (   buf_clk40   )

Process

Definition at line 1543 of file CMX_input_module.vhd.

PROCESS_35	(		buf_clk40 ,
			pll_locked
	)

Definition at line 1587 of file CMX_input_module.vhd.

PROCESS_36 (   buf_clk40 ,   pll_locked   )

Process

Definition at line 1658 of file CMX_input_module.vhd.

PROCESS_37 (   buf_clk40   )

Process

Definition at line 1686 of file CMX_input_module.vhd.

PROCESS_38

(

CLKPARB (channel)

)

Definition at line 1789 of file CMX_input_module.vhd.

PROCESS_39 (   CLKPARB (channel)   )

Process

Definition at line 1797 of file CMX_input_module.vhd.

PROCESS_40 (   buf_clk40   )

Process

Definition at line 1814 of file CMX_input_module.vhd.

PROCESS_41 (   buf_clk40   )

Process

Definition at line 1821 of file CMX_input_module.vhd.

PROCESS_42 (   buf_clk40   )

Process

Definition at line 1834 of file CMX_input_module.vhd.

spy_source_addr_proc (   CLKPARB (i_mem_source)   )

Process

Definition at line 1280 of file CMX_input_module.vhd.

spy_source_addr_proc (   buf_clk40   )

Process

Definition at line 1595 of file CMX_input_module.vhd.

Member Data Documentation

addra_SPY_SOURCE std_logic_vector ( 7 downto 0 )

Signal

Definition at line 424 of file CMX_input_module.vhd.

addra_SPY_SYSTEM std_logic_vector ( 7 downto 0 )

Signal

Definition at line 512 of file CMX_input_module.vhd.

addrb_SPY_SOURCE_counter arr_ctr_9bit ( numactchan - 1 downto 0 )

Signal

Definition at line 497 of file CMX_input_module.vhd.

addrb_SPY_SOURCE_individual arr_9 ( numactchan - 1 downto 0 )

Signal

Definition at line 491 of file CMX_input_module.vhd.

addrb_SPY_SYSTEM_counter arr_ctr_8bit ( numactchan - 1 downto 0 )

Signal

Definition at line 577 of file CMX_input_module.vhd.

addrb_SPY_SYSTEM_individual arr_8 ( numactchan - 1 downto 0 )

Signal

Definition at line 569 of file CMX_input_module.vhd.

any_reset_B std_logic

Signal

Definition at line 264 of file CMX_input_module.vhd.

any_reset_B_s1 std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 299 of file CMX_input_module.vhd.

any_reset_B_synced std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 299 of file CMX_input_module.vhd.

any_reset_B_synced_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 300 of file CMX_input_module.vhd.

any_reset_B_synced_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 300 of file CMX_input_module.vhd.

backplane_events_counter arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 116 of file CMX_input_module.vhd.

backplane_events_counter_next arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 118 of file CMX_input_module.vhd.

backplane_events_counter_s arr_sig_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 117 of file CMX_input_module.vhd.

bit_error_counter arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 631 of file CMX_input_module.vhd.

bit_error_counter_next arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 632 of file CMX_input_module.vhd.

bit_error_counter_system arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 642 of file CMX_input_module.vhd.

bit_error_counter_system_next arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 643 of file CMX_input_module.vhd.

bit_error_detect arr_48 ( numactchan - 1 downto 0 )

Signal

Definition at line 628 of file CMX_input_module.vhd.

bit_error_detect_system arr_96 ( numactchan - 1 downto 0 )

Signal

Definition at line 639 of file CMX_input_module.vhd.

bit_error_latch arr_24 ( numactchan - 1 downto 0 )

Signal

Definition at line 629 of file CMX_input_module.vhd.

bit_error_latch_system arr_24 ( numactchan - 1 downto 0 )

Signal

Definition at line 640 of file CMX_input_module.vhd.

blk_mem_A8x96_B8x96

Component

Definition at line 522 of file CMX_input_module.vhd.

blk_mem_a8x96_b8x96_spy_system blk_mem_a8x96_b8x96

Instantiation

Definition at line 1552 of file CMX_input_module.vhd.

blk_mem_A8x96_B9x48

Component

Definition at line 438 of file CMX_input_module.vhd.

blk_mem_a8x96_b9x48_spy_source blk_mem_a8x96_b9x48

Instantiation

Definition at line 1218 of file CMX_input_module.vhd.

BUF_2X24_AT_80_TO_1X96_AT_40

Component

Definition at line 341 of file CMX_input_module.vhd.

buf_inst BUF_2X24_AT_80_TO_1X96_AT_40

Instantiation

Definition at line 807 of file CMX_input_module.vhd.

bufr_inst bufr

Instantiation

Definition at line 763 of file CMX_input_module.vhd.

bus_drive_from_below std_logic_vector ( 13 + 2 * numactchan - 1 + 5 * numactchan - 1 + 4 * numactchan - 1 + 9 * numactchan - 1 downto 0 )

Signal

Definition at line 666 of file CMX_input_module.vhd.

ch_quiet std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 97 of file CMX_input_module.vhd.

channel_mask std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 260 of file CMX_input_module.vhd.

clkb_SPY_SOURCE_individual std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 460 of file CMX_input_module.vhd.

clkb_SPY_SYSTEM_individual std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 546 of file CMX_input_module.vhd.

CLKPAR STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )

Signal

Definition at line 277 of file CMX_input_module.vhd.

CLKPAR_DATA STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )

Signal

Definition at line 285 of file CMX_input_module.vhd.

CLKPARB STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )

Signal

Definition at line 282 of file CMX_input_module.vhd.

clock_detect_counter arr_ctr_16bit ( numactchan - 1 downto 0 )

Signal

Definition at line 305 of file CMX_input_module.vhd.

clock_detect_counter_next arr_ctr_16bit ( numactchan - 1 downto 0 )

Signal

Definition at line 306 of file CMX_input_module.vhd.

clock_diff_counter arr_sig_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 120 of file CMX_input_module.vhd.

clock_diff_counter_ratchet_down arr_sig_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 123 of file CMX_input_module.vhd.

clock_diff_counter_ratchet_up arr_sig_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 122 of file CMX_input_module.vhd.

clock_diff_duration_counter arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 121 of file CMX_input_module.vhd.

CMX_data_delay

Component

Definition at line 309 of file CMX_input_module.vhd.

CMX_generic_spy_mem_control_FSM

Component

Definition at line 370 of file CMX_input_module.vhd.

cmx_input_module_spy_mem_control_fsm_inst CMX_generic_spy_mem_control_FSM

Instantiation

Definition at line 1168 of file CMX_input_module.vhd.

cmx_input_module_spy_mem_control_fsm_inst_system CMX_generic_spy_mem_control_FSM

Instantiation

Definition at line 1486 of file CMX_input_module.vhd.

counter_enable std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 298 of file CMX_input_module.vhd.

counter_reset std_logic

Signal

Definition at line 125 of file CMX_input_module.vhd.

counter_reset_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 133 of file CMX_input_module.vhd.

counter_reset_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 133 of file CMX_input_module.vhd.

counter_reset_rr_SYSTEM_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 133 of file CMX_input_module.vhd.

counter_reset_rr_SYSTEM_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 133 of file CMX_input_module.vhd.

counter_reset_unstretched std_logic

Signal

Definition at line 125 of file CMX_input_module.vhd.

cyclecounter arr_ctr_1bit ( numactchan - 1 downto 0 )

Signal

Definition at line 302 of file CMX_input_module.vhd.

cyclecounter_next arr_ctr_1bit ( numactchan - 1 downto 0 )

Signal

Definition at line 303 of file CMX_input_module.vhd.

DATA24 arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 71 of file CMX_input_module.vhd.

data_from_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK std_logic_vector ( 15 downto 0 )

Signal

Definition at line 258 of file CMX_input_module.vhd.

data_from_vme_REG_RW_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 233 of file CMX_input_module.vhd.

data_from_vme_REG_RW_INPUT_MOD_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 254 of file CMX_input_module.vhd.

data_from_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS arr_16 ( numactchan - 1 downto 0 )

Signal

Definition at line 504 of file CMX_input_module.vhd.

data_from_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 586 of file CMX_input_module.vhd.

data_to_vme_REG_RO_INPUT_MOD_COUNTER_ENABLE std_logic_vector ( 15 downto 0 )

Signal

Definition at line 238 of file CMX_input_module.vhd.

data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_0 arr_16 ( numactchan - 1 downto 0 )

Signal

Definition at line 634 of file CMX_input_module.vhd.

data_to_vme_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR_1 arr_16 ( numactchan - 1 downto 0 )

Signal

Definition at line 635 of file CMX_input_module.vhd.

data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_0 arr_16 ( numactchan - 1 downto 0 )

Signal

Definition at line 645 of file CMX_input_module.vhd.

data_to_vme_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR_1 arr_16 ( numactchan - 1 downto 0 )

Signal

Definition at line 646 of file CMX_input_module.vhd.

data_to_vme_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK std_logic_vector ( 15 downto 0 )

Signal

Definition at line 257 of file CMX_input_module.vhd.

data_to_vme_REG_RW_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 236 of file CMX_input_module.vhd.

data_to_vme_REG_RW_INPUT_MOD_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 255 of file CMX_input_module.vhd.

data_to_vme_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS arr_16 ( numactchan - 1 downto 0 )

Signal

Definition at line 505 of file CMX_input_module.vhd.

data_to_vme_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 587 of file CMX_input_module.vhd.

data_vme_from_below arr_16 ( 13 + 2 * numactchan - 1 + 5 * numactchan - 1 + 4 * numactchan - 1 + 9 * numactchan - 1 downto 0 )

Signal

Definition at line 665 of file CMX_input_module.vhd.

DEBOUNCE_10

Component

Definition at line 359 of file CMX_input_module.vhd.

DELAYED_CLKPAR STD_LOGIC_VECTOR ( numactchan - 1 downto 0 )

Signal

Definition at line 281 of file CMX_input_module.vhd.

DELAYED_DATA24 arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 73 of file CMX_input_module.vhd.

DELAYED_DATA24_reg arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 74 of file CMX_input_module.vhd.

dina_SPY_SOURCE std_logic_vector ( 95 downto 0 )

Signal

Definition at line 426 of file CMX_input_module.vhd.

dina_SPY_SYSTEM std_logic_vector ( 95 downto 0 )

Signal

Definition at line 514 of file CMX_input_module.vhd.

dinb_SPY_SOURCE_individual arr_48 ( numactchan - 1 downto 0 )

Signal

Definition at line 492 of file CMX_input_module.vhd.

dinb_SPY_SYSTEM_individual arr_96 ( numactchan - 1 downto 0 )

Signal

Definition at line 570 of file CMX_input_module.vhd.

douta_SPY_SOURCE std_logic_vector ( 95 downto 0 )

Signal

Definition at line 427 of file CMX_input_module.vhd.

douta_SPY_SOURCE_individual arr_96 ( numactchan - 1 downto 0 )

Signal

Definition at line 459 of file CMX_input_module.vhd.

douta_SPY_SYSTEM std_logic_vector ( 95 downto 0 )

Signal

Definition at line 515 of file CMX_input_module.vhd.

douta_SPY_SYSTEM_individual arr_96 ( numactchan - 1 downto 0 )

Signal

Definition at line 545 of file CMX_input_module.vhd.

doutb_SPY_SOURCE_individual arr_48 ( numactchan - 1 downto 0 )

Signal

Definition at line 493 of file CMX_input_module.vhd.

doutb_SPY_SYSTEM_individual arr_4Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 571 of file CMX_input_module.vhd.

ena_SPY_SOURCE std_logic

Signal

Definition at line 422 of file CMX_input_module.vhd.

ena_SPY_SOURCE_individual std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 455 of file CMX_input_module.vhd.

ena_SPY_SYSTEM std_logic

Signal

Definition at line 510 of file CMX_input_module.vhd.

ena_SPY_SYSTEM_individual std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 541 of file CMX_input_module.vhd.

enb_SPY_SOURCE STD_LOGIC

Signal

Definition at line 463 of file CMX_input_module.vhd.

enb_SPY_SOURCE_individual std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 485 of file CMX_input_module.vhd.

enb_SPY_SOURCE_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 470 of file CMX_input_module.vhd.

enb_SPY_SOURCE_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 468 of file CMX_input_module.vhd.

enb_SPY_SOURCE_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 471 of file CMX_input_module.vhd.

enb_SPY_SOURCE_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 469 of file CMX_input_module.vhd.

enb_SPY_SOURCE_split std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 467 of file CMX_input_module.vhd.

enb_SPY_SYSTEM STD_LOGIC

Signal

Definition at line 549 of file CMX_input_module.vhd.

enb_SPY_SYSTEM_individual std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 563 of file CMX_input_module.vhd.

enb_SPY_SYSTEM_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 554 of file CMX_input_module.vhd.

enb_SPY_SYSTEM_split std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 553 of file CMX_input_module.vhd.

event_counter unsigned ( 31 downto 0 )

Signal

Definition at line 108 of file CMX_input_module.vhd.

event_counter_next unsigned ( 31 downto 0 )

Signal

Definition at line 110 of file CMX_input_module.vhd.

event_counter_s signed ( 31 downto 0 )

Signal

Definition at line 109 of file CMX_input_module.vhd.

i_pll_locked std_logic

Signal

Definition at line 295 of file CMX_input_module.vhd.

iddr_inst iddr

Instantiation

Definition at line 784 of file CMX_input_module.vhd.

inst_cmx_data_delay CMX_data_delay

Instantiation

Definition at line 738 of file CMX_input_module.vhd.

keep string

Attribute

Definition at line 669 of file CMX_input_module.vhd.

keep enb_SPY_SOURCE_r_SOURCE , web_SPY_SOURCE_r_SOURCE , enb_SPY_SOURCE_split , web_SPY_SOURCE_split , enb_SPY_SOURCE_rr_SOURCE , web_SPY_SOURCE_rr_SOURCE , enb_SPY_SOURCE_r_SYSTEM , web_SPY_SOURCE_r_SYSTEM , enb_SPY_SOURCE_rr_SYSTEM , web_SPY_SOURCE_rr_SYSTEM , port_b_master_inhibit_SPY_SOURCE_split , port_b_master_inhibit_SPY_SOURCE_r_SYSTEM , port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE , port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE , counter_reset_r_SYSTEM , counter_reset_rr_SYSTEM , counter_reset_rr_SYSTEM_r_SOURCE , any_reset_B_synced_r_SOURCE , any_reset_B_synced_rr_SOURCE , ODATA_sig_r_SYSTEM : signal is " TRUE "

Attribute

Definition at line 671 of file CMX_input_module.vhd.

mem_select_address_SPY_SOURCE std_logic_vector ( 3 downto 0 )

Signal

Definition at line 425 of file CMX_input_module.vhd.

mem_select_address_SPY_SYSTEM std_logic_vector ( 3 downto 0 )

Signal

Definition at line 513 of file CMX_input_module.vhd.

mode_control_SPY_SOURCE std_logic_vector ( 3 downto 0 )

Signal

Definition at line 421 of file CMX_input_module.vhd.

mode_control_SPY_SYSTEM std_logic_vector ( 3 downto 0 )

Signal

Definition at line 509 of file CMX_input_module.vhd.

NDATA arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 271 of file CMX_input_module.vhd.

NDATA_r_SOURCE arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 274 of file CMX_input_module.vhd.

ODATA_first_half_sig arr_2Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 89 of file CMX_input_module.vhd.

ODATA_first_half_sig_r_mSYSTEM arr_2Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 95 of file CMX_input_module.vhd.

ODATA_first_half_unmasked_sig arr_2Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 92 of file CMX_input_module.vhd.

ODATA_sig arr_4Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 79 of file CMX_input_module.vhd.

ODATA_sig_r_SYSTEM arr_4Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 83 of file CMX_input_module.vhd.

ODATA_sig_rr_SYSTEM arr_4Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 87 of file CMX_input_module.vhd.

ODATA_unmasked_sig arr_4Xword ( numactchan - 1 downto 0 )

Signal

Definition at line 82 of file CMX_input_module.vhd.

or_all

Component

Definition at line 648 of file CMX_input_module.vhd.

or_par or_all

Instantiation

Definition at line 862 of file CMX_input_module.vhd.

par_err_counter arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 113 of file CMX_input_module.vhd.

par_err_counter_next arr_ctr_32bit ( numactchan - 1 downto 0 )

Signal

Definition at line 114 of file CMX_input_module.vhd.

PAR_ERROR_sig std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 99 of file CMX_input_module.vhd.

PAR_ERROR_sig_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 104 of file CMX_input_module.vhd.

PAR_ERROR_sig_r_SYSTEM_ORed std_logic

Signal

Definition at line 101 of file CMX_input_module.vhd.

PAR_ERROR_sig_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 105 of file CMX_input_module.vhd.

PAR_ERROR_unmasked_sig std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 103 of file CMX_input_module.vhd.

PDATA arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 270 of file CMX_input_module.vhd.

PDATA_r_SOURCE arr_word ( numactchan - 1 downto 0 )

Signal

Definition at line 273 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SOURCE std_logic

Signal

Definition at line 428 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SOURCE_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 431 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 432 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SOURCE_r_SYSTEM_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 433 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SOURCE_split std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 430 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SYSTEM std_logic

Signal

Definition at line 516 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SYSTEM_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 519 of file CMX_input_module.vhd.

port_b_master_inhibit_SPY_SYSTEM_split std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 518 of file CMX_input_module.vhd.

spy_write_inhibit_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 559 of file CMX_input_module.vhd.

spy_write_inhibit_r_SYSTEM_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 480 of file CMX_input_module.vhd.

spy_write_inhibit_r_SYSTEM_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 481 of file CMX_input_module.vhd.

spy_write_inhibit_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 560 of file CMX_input_module.vhd.

start_playback_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 582 of file CMX_input_module.vhd.

start_playback_r_SYSTEM_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 501 of file CMX_input_module.vhd.

start_playback_r_SYSTEM_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 502 of file CMX_input_module.vhd.

start_playback_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 583 of file CMX_input_module.vhd.

Stretch_10

Component

Definition at line 126 of file CMX_input_module.vhd.

stretch_10_counter_reset Stretch_10

Instantiation

Definition at line 912 of file CMX_input_module.vhd.

vme_inreg_async_reg_rw_backplane_input_channel_mask vme_inreg_notri_async

Instantiation

Definition at line 871 of file CMX_input_module.vhd.

vme_inreg_async_reg_rw_input_mod_reset vme_inreg_notri_async

Instantiation

Definition at line 1046 of file CMX_input_module.vhd.

vme_inreg_notri

Component

Definition at line 181 of file CMX_input_module.vhd.

vme_inreg_notri_async

Component

Definition at line 200 of file CMX_input_module.vhd.

vme_inreg_reg_rw_counter_reset vme_inreg_notri

Instantiation

Definition at line 892 of file CMX_input_module.vhd.

vme_inreg_reg_rw_input_spy_mem_source_start_address vme_inreg_notri_async

Instantiation

Definition at line 1252 of file CMX_input_module.vhd.

vme_inreg_reg_rw_input_spy_mem_system_start_address vme_inreg_notri_async

Instantiation

Definition at line 1512 of file CMX_input_module.vhd.

vme_local_switch

Component

Definition at line 656 of file CMX_input_module.vhd.

vme_local_switch_inst vme_local_switch

Instantiation

Definition at line 719 of file CMX_input_module.vhd.

vme_outreg_notri_async

Component

Definition at line 166 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_detect_counter vme_outreg_notri_async

Instantiation

Definition at line 1854 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_detect_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1869 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_detect_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1883 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_duration_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1897 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_duration_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1911 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_ratchet_down_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1955 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_ratchet_down_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1969 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_ratchet_up_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1926 of file CMX_input_module.vhd.

vme_outreg_reg_ro_clock_diff_ratchet_up_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1940 of file CMX_input_module.vhd.

vme_outreg_reg_ro_ev_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 918 of file CMX_input_module.vhd.

vme_outreg_reg_ro_ev_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 932 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_mod_counter_enable vme_outreg_notri_async

Instantiation

Definition at line 1072 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_source_check_error_0 vme_outreg_notri_async

Instantiation

Definition at line 1414 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_source_check_error_1 vme_outreg_notri_async

Instantiation

Definition at line 1429 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1443 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_source_noerror_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1457 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_system_check_error_0 vme_outreg_notri_async

Instantiation

Definition at line 1715 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_system_check_error_1 vme_outreg_notri_async

Instantiation

Definition at line 1730 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1744 of file CMX_input_module.vhd.

vme_outreg_reg_ro_input_spy_mem_system_noerror_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1758 of file CMX_input_module.vhd.

vme_outreg_reg_ro_parity_error_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 966 of file CMX_input_module.vhd.

vme_outreg_reg_ro_parity_error_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 981 of file CMX_input_module.vhd.

vme_reset_B std_logic

Signal

Definition at line 262 of file CMX_input_module.vhd.

wea_SPY_SOURCE std_logic

Signal

Definition at line 423 of file CMX_input_module.vhd.

wea_SPY_SOURCE_individual arr_1 ( numactchan - 1 downto 0 )

Signal

Definition at line 456 of file CMX_input_module.vhd.

wea_SPY_SYSTEM std_logic

Signal

Definition at line 511 of file CMX_input_module.vhd.

wea_SPY_SYSTEM_individual arr_1 ( numactchan - 1 downto 0 )

Signal

Definition at line 542 of file CMX_input_module.vhd.

web_SPY_SOURCE STD_LOGIC

Signal

Definition at line 464 of file CMX_input_module.vhd.

web_SPY_SOURCE_individual arr_1 ( numactchan - 1 downto 0 )

Signal

Definition at line 486 of file CMX_input_module.vhd.

web_SPY_SOURCE_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 476 of file CMX_input_module.vhd.

web_SPY_SOURCE_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 474 of file CMX_input_module.vhd.

web_SPY_SOURCE_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 477 of file CMX_input_module.vhd.

web_SPY_SOURCE_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 475 of file CMX_input_module.vhd.

web_SPY_SOURCE_split std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 473 of file CMX_input_module.vhd.

web_SPY_SYSTEM STD_LOGIC

Signal

Definition at line 550 of file CMX_input_module.vhd.

web_SPY_SYSTEM_individual arr_1 ( numactchan - 1 downto 0 )

Signal

Definition at line 564 of file CMX_input_module.vhd.

web_SPY_SYSTEM_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 557 of file CMX_input_module.vhd.

web_SPY_SYSTEM_split std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 556 of file CMX_input_module.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_input_module.vhd