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CMX_data_delay Entity Reference
Inheritance diagram for CMX_data_delay:
vme_local_switch vme_outreg_notri_async CMX_input_module

Entities

Behavioral  architecture
 

Libraries

IEEE 
UNISIM 

Use Clauses

IEEE.STD_LOGIC_1164.all 
IEEE.NUMERIC_STD.all 
UNISIM.VComponents.all 
work.CMX_VME_defs.all 
WORK.CMXpackage.all 

Ports

DATA24   in arr_word ( numactchan - 1 downto 0 )
CLKPAR   in std_logic_vector ( numactchan - 1 downto 0 )
REF_CLK_200   in std_logic
REF_CLK_READY   in std_logic
CLK_40   in std_logic
del_register   in del_register_type
upload_delays   in std_logic
IDELAYCTRL_RDY   out std_logic_vector ( num_IDELAYCTRL - 1 downto 0 )
DELAYED_DATA24   out arr_word ( numactchan - 1 downto 0 )
DELAYED_CLKPAR   out std_logic_vector ( numactchan - 1 downto 0 )
ncs   in std_logic
rd_nwr   in std_logic
ds   in std_logic
addr_vme   in std_logic_vector ( 15 downto 0 )
data_vme_in   in std_logic_vector ( 15 downto 0 )
data_vme_out   out std_logic_vector ( 15 downto 0 )
bus_drive   out std_logic

Detailed Description

Definition at line 25 of file CMX_data_delay.vhd.

Member Data Documentation

addr_vme in std_logic_vector ( 15 downto 0 )
Port

Definition at line 48 of file CMX_data_delay.vhd.

bus_drive out std_logic
Port

Definition at line 51 of file CMX_data_delay.vhd.

CLK_40 in std_logic
Port

Definition at line 31 of file CMX_data_delay.vhd.

CLKPAR in std_logic_vector ( numactchan - 1 downto 0 )
Port

Definition at line 28 of file CMX_data_delay.vhd.

DATA24 in arr_word ( numactchan - 1 downto 0 )
Port

Definition at line 27 of file CMX_data_delay.vhd.

data_vme_in in std_logic_vector ( 15 downto 0 )
Port

Definition at line 49 of file CMX_data_delay.vhd.

data_vme_out out std_logic_vector ( 15 downto 0 )
Port

Definition at line 50 of file CMX_data_delay.vhd.

del_register in del_register_type
Port

Definition at line 32 of file CMX_data_delay.vhd.

DELAYED_CLKPAR out std_logic_vector ( numactchan - 1 downto 0 )
Port

Definition at line 42 of file CMX_data_delay.vhd.

DELAYED_DATA24 out arr_word ( numactchan - 1 downto 0 )
Port

Definition at line 41 of file CMX_data_delay.vhd.

ds in std_logic
Port

Definition at line 47 of file CMX_data_delay.vhd.

IDELAYCTRL_RDY out std_logic_vector ( num_IDELAYCTRL - 1 downto 0 )
Port

Definition at line 40 of file CMX_data_delay.vhd.

IEEE
Library

Definition at line 11 of file CMX_data_delay.vhd.

IEEE.NUMERIC_STD.all
Package

Definition at line 13 of file CMX_data_delay.vhd.

IEEE.STD_LOGIC_1164.all
Package

Definition at line 12 of file CMX_data_delay.vhd.

ncs in std_logic
Port

Definition at line 45 of file CMX_data_delay.vhd.

rd_nwr in std_logic
Port

Definition at line 46 of file CMX_data_delay.vhd.

REF_CLK_200 in std_logic
Port

Definition at line 29 of file CMX_data_delay.vhd.

REF_CLK_READY in std_logic
Port

Definition at line 30 of file CMX_data_delay.vhd.

UNISIM
Library

Definition at line 18 of file CMX_data_delay.vhd.

UNISIM.VComponents.all
Package

Definition at line 19 of file CMX_data_delay.vhd.

upload_delays in std_logic
Port

Definition at line 35 of file CMX_data_delay.vhd.

work.CMX_VME_defs.all
Package

Definition at line 21 of file CMX_data_delay.vhd.

WORK.CMXpackage.all
Package

Definition at line 23 of file CMX_data_delay.vhd.

The documentation for this class was generated from the following file: