CMX_data_delay.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

use work.CMX_VME_defs.all;

USE WORK.CMXpackage.all;

entity CMX_data_delay is
   PORT(
    DATA24: in arr_word (numactchan-1 downto 0);
    CLKPAR: in std_logic_vector(numactchan - 1 downto 0);
    REF_CLK_200: in std_logic;
    REF_CLK_READY: in std_logic;
    CLK_40: in std_logic;
    del_register: in del_register_type;  --input from VME holding 5 bit delay
                                         --for every data and clkpar signal of
                                         --every channel
    upload_delays: in std_logic;        --needs to be pulsed high for the
                                        --upload of the registers into the
                                        --iodelay instances

    
    IDELAYCTRL_RDY: out std_logic_vector(num_IDELAYCTRL-1 downto 0);
    DELAYED_DATA24: out arr_word (numactchan-1 downto 0);
    DELAYED_CLKPAR: out std_logic_vector(numactchan - 1 downto 0);

    --VME control:
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;
    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    
    );
end CMX_data_delay;

architecture Behavioral of CMX_data_delay is

  signal rst_after_clkrdy : std_logic_vector(num_IDELAYCTRL-1 downto 0);

  signal IDELAYCTRL_RDY_sig : std_logic_vector(num_IDELAYCTRL-1 downto 0);
  
  signal IDELcount_rst_pulse: arr_ctr_16bit(num_IDELAYCTRL-1 downto 0);
  signal IDELcount_rst_pulse_next: arr_ctr_16bit(num_IDELAYCTRL-1 downto 0);

  signal data_to_vme_REG_RO_IDELAYCTRL_RDY : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RO_IDELAYCTRL_RST : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RO_IDELAYCTRL_WAS_RST : std_logic_vector(15 downto 0);

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  
  signal data_vme_from_below  : arr_16(2 downto 0);
  signal bus_drive_from_below : std_logic_vector(2 downto 0);
 
  
  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;
 
begin

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_from_below,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_from_below);

    
  vme_outreg_REG_RO_IDELAYCTRL_RDY: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_IDELAYCTRL_RDY ,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme   =>     data_vme_from_below(0),
      bus_drive      =>     bus_drive_from_below (0),
      data_to_vme  => data_to_vme_REG_RO_IDELAYCTRL_RDY
      );

  data_to_vme_REG_RO_IDELAYCTRL_RDY(15)<=REF_CLK_READY;
  data_to_vme_REG_RO_IDELAYCTRL_RDY(num_IDELAYCTRL-1 downto 0)<=IDELAYCTRL_RDY_sig;
  data_to_vme_REG_RO_IDELAYCTRL_RDY(14 downto num_IDELAYCTRL)<=(others=>'0');

    
  vme_outreg_REG_RO_IDELAYCTRL_RST: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_IDELAYCTRL_RST ,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme   =>     data_vme_from_below(1),
      bus_drive      =>     bus_drive_from_below (1),
      data_to_vme  => data_to_vme_REG_RO_IDELAYCTRL_RST
      );

  
  data_to_vme_REG_RO_IDELAYCTRL_RST(num_IDELAYCTRL-1 downto 0)<=rst_after_clkrdy;
  data_to_vme_REG_RO_IDELAYCTRL_RST(15 downto num_IDELAYCTRL)<=(others=>'0');
  

  vme_outreg_REG_RO_IDELAYCTRL_WAS_RST: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_IDELAYCTRL_WAS_RST ,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme   =>     data_vme_from_below(2),
      bus_drive      =>     bus_drive_from_below (2),
      data_to_vme  => data_to_vme_REG_RO_IDELAYCTRL_WAS_RST
      );

  data_to_vme_REG_RO_IDELAYCTRL_WAS_RST(15 downto num_IDELAYCTRL)<=(others=>'0');
  

  IDELAYCTRL_RDY<=IDELAYCTRL_RDY_sig;
  
  ioctrlgen: for ctrl in 0 to num_IDELAYCTRL - 1 generate


  --this generates a long clock reset pulse for ioctrl after the MMCM has locked
  IDELcount_rst_pulse_next(ctrl)<=IDELcount_rst_pulse(ctrl)+1;
  
  rst_ioctrl: process (REF_CLK_200, REF_CLK_READY)
  begin  -- process rst_ioctrl
    if REF_CLK_READY/='1' then
      rst_after_clkrdy(ctrl)<='1';
      IDELcount_rst_pulse(ctrl)<=to_unsigned(0,16);
    else
      if rising_edge(REF_CLK_200) then
        if IDELcount_rst_pulse(ctrl)<to_unsigned(32768,16) then
          rst_after_clkrdy(ctrl)<='1';
          IDELcount_rst_pulse(ctrl)<=IDELcount_rst_pulse_next(ctrl);
        else
          rst_after_clkrdy(ctrl)<='0';
        end if;
      end if;
    end if;
  end process rst_ioctrl;

  data_to_vme_REG_RO_IDELAYCTRL_WAS_RST(ctrl)<=IDELcount_rst_pulse(ctrl)(15);
    
    IDELAYCTRL_inst : IDELAYCTRL
      port map (
        RDY  => IDELAYCTRL_RDY_sig(ctrl),       -- 1-bit output indicates validity of the REFCLK
        REFCLK  => REF_CLK_200, -- 1-bit reference clock input
        RST  => rst_after_clkrdy (ctrl)        -- 1-bit reset input
        );
    
  end generate ioctrlgen;

  iodelgen_chan: for channel in 0 to numactchan - 1 generate
    iodelgen_bit: for bitnum in 0 to numbitsinchan - 1  generate

      IODELAYE1_inst_data : IODELAYE1
        generic map (
          CINVCTRL_SEL => FALSE,          -- Enable dynamic clock inversion (TRUE/FALSE)
          DELAY_SRC  => "I",               -- Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
          HIGH_PERFORMANCE_MODE  => TRUE, -- Reduced jitter (TRUE), Reduced power (FALSE)
          IDELAY_TYPE  => "VAR_LOADABLE",       -- "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE" 
          IDELAY_VALUE => 0,              -- Input delay tap setting (0-31)
          ODELAY_TYPE  => "FIXED" ,         -- "FIXED", "VARIABLE", or "VAR_LOADABLE" 
          ODELAY_VALUE => 0,              -- Output delay tap setting (0-31)
          REFCLK_FREQUENCY  => 200.0,      -- IDELAYCTRL clock input frequency in MHz
          SIGNAL_PATTERN  => "DATA"        -- "DATA" or "CLOCK" input signal
          )
        port map (
          CNTVALUEOUT  => open, -- 5-bit output: Counter value output
          DATAOUT  => DELAYED_DATA24(channel)(bitnum),         -- 1-bit output: Delayed data output
          C  => CLK_40,                     -- 1-bit input: Clock input
          CE  => '0',                   -- 1-bit input: Active high enable increment/decrement input
          CINVCTRL  => '0',       -- 1-bit input: Dynamic clock inversion input
          CLKIN  => '0',             -- 1-bit input: Clock delay input
          CNTVALUEIN  => del_register(channel,bitnum),   -- 5-bit input: Counter value input
          DATAIN  => '0',           -- 1-bit input: Internal delay data input
          IDATAIN  => DATA24 (channel)(bitnum),         -- 1-bit input: Data input from the I/O
          INC  => '0',                 -- 1-bit input: Increment / Decrement tap delay input
          ODATAIN  => '0',         -- 1-bit input: Output delay data input
          RST  => upload_delays ,                 -- 1-bit input: Active-high reset tap-delay input
          T  => '1'                       -- 1-bit input: 3-state input
          );
      
    end generate iodelgen_bit;

    IODELAYE1_inst_clkpar : IODELAYE1
        generic map (
          CINVCTRL_SEL => FALSE,          -- Enable dynamic clock inversion (TRUE/FALSE)
          DELAY_SRC  => "I",               -- Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
          HIGH_PERFORMANCE_MODE  => TRUE, -- Reduced jitter (TRUE), Reduced power (FALSE)
          IDELAY_TYPE  => "VAR_LOADABLE",       -- "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE" 
          IDELAY_VALUE => 0,              -- Input delay tap setting (0-31)
          ODELAY_TYPE  => "FIXED" ,         -- "FIXED", "VARIABLE", or "VAR_LOADABLE" 
          ODELAY_VALUE => 0,              -- Output delay tap setting (0-31)
          REFCLK_FREQUENCY  => 200.0,      -- IDELAYCTRL clock input frequency in MHz
          SIGNAL_PATTERN  => "CLOCK"        -- "DATA" or "CLOCK" input signal
          )
        port map (
          CNTVALUEOUT  => open, -- 5-bit output: Counter value output
          DATAOUT  => DELAYED_CLKPAR(channel),         -- 1-bit output: Delayed data output
          C  => CLK_40,                     -- 1-bit input: Clock input
          CE  => '0',                   -- 1-bit input: Active high enable increment/decrement input
          CINVCTRL  => '0',       -- 1-bit input: Dynamic clock inversion input
          CLKIN  => '0',             -- 1-bit input: Clock delay input
          CNTVALUEIN  => del_register(channel,numbitsinchan),   -- 5-bit input: Counter value input
          DATAIN  => '0',           -- 1-bit input: Internal delay data input
          IDATAIN  => CLKPAR (channel),         -- 1-bit input: Data input from the I/O
          INC  => '0',                 -- 1-bit input: Increment / Decrement tap delay input
          ODATAIN  => '0',         -- 1-bit input: Output delay data input
          RST  => upload_delays ,                 -- 1-bit input: Active-high reset tap-delay input
          T  => '1'                       -- 1-bit input: 3-state input
          );
    
  end generate iodelgen_chan;
  
  
end Behavioral;