CMX_CTP_output_module.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;



entity CMX_CTP_output_module is
  port (
    --data to be sent to CTP as received from the adder
    --numbits_in_CTP_connector does not include clock
    data : in std_logic_vector( (numbits_in_CTP_connector*2)-1 downto 0);

    --registered data or playback data from the RAM
    sdr_data_out              : out arr_CTP; 
    --includes clock
    buf_clk40          : in std_logic;       -- global 40 MHz clock
    buf_clk40_center   : in std_logic;       -- global 40 MHz clock pushed by 90^o
    buf_clk200         : in std_logic;       -- global 200 MHz clock for iodelay calibration
    pll_locked         : in std_logic;       -- is the main MMCM locked?
    start_playback     : in std_logic;
    spy_write_inhibit  : in std_logic;
    --VME control:
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;
    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
  
end CMX_CTP_output_module;

architecture Behavioral of CMX_CTP_output_module is

  attribute IOB : string;
  
  signal data_r : std_logic_vector( (numbits_in_CTP_connector*2)-1 downto 0);

  attribute IOB of data_r : signal is "TRUE";
    
  component CMX_generic_spy_mem_control_FSM is
    generic (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD    : integer;
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL : integer;
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS  : integer;
      num_external_RAMS                   : positive);
    port (
      clk                   : in    std_logic;
      ncs                   : in    std_logic;
      rd_nwr                : in    std_logic;
      ds                    : in    std_logic;
      addr_vme              : in    std_logic_vector (15 downto 0);
      data_vme_in           : in    std_logic_vector (15 downto 0);
      data_vme_out          : out   std_logic_vector (15 downto 0);
      bus_drive             : out   std_logic;
      mode_control          : out   std_logic_vector(3 downto 0);
      ena                   : out   std_logic;
      wea                   : out   std_logic;
      addra                 : out   std_logic_vector(7 DOWNTO 0);
      mem_select_address    : out   std_logic_vector(addr_port_width(num_external_RAMS)-1 downto 0);
      dina                  : out   std_logic_vector;
      douta                 : in    std_logic_vector;
      port_b_master_inhibit : out   std_logic);
  end component CMX_generic_spy_mem_control_FSM;


  signal mode_control_CTP_SPY          : std_logic_vector(3 downto 0);
  signal ena_CTP_SPY                   : std_logic;
  signal wea_CTP_SPY                   : std_logic_vector(0 downto 0);
  signal addra_CTP_SPY                 : std_logic_vector(7 DOWNTO 0);
  signal dina_CTP_SPY                  : std_logic_vector( ( numbits_in_CTP_connector *2)-1 downto 0);
  signal douta_CTP_SPY                 : std_logic_vector( ( numbits_in_CTP_connector *2)-1 downto 0);
  signal port_b_master_inhibit_CTP_SPY : std_logic;
  signal port_b_master_inhibit_CTP_SPY_r : std_logic;
  
  
  signal spy_write_inhibit_r  : std_logic;
  signal spy_write_inhibit_rr : std_logic;
  
  component blk_mem_A8x62_B8x62 is
    port (
      clka  : IN  STD_LOGIC;
      ena   : IN  STD_LOGIC;
      wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dina  : IN  STD_LOGIC_VECTOR(61 DOWNTO 0);
      douta : OUT STD_LOGIC_VECTOR(61 DOWNTO 0);
      clkb  : IN  STD_LOGIC;
      enb   : IN  STD_LOGIC;
      web   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addrb : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dinb  : IN  STD_LOGIC_VECTOR(61 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(61 DOWNTO 0));
  end component blk_mem_A8x62_B8x62;

  signal enb_CTP_SPY                   : std_logic;
  signal web_CTP_SPY                   : std_logic;
  signal enb_CTP_SPY_r                 : std_logic;
  signal web_CTP_SPY_r                 : std_logic;
  signal enb_CTP_SPY_inhibited         : std_logic;
  signal web_CTP_SPY_inhibited         : std_logic_vector(0 downto 0);

  signal addrb_CTP_SPY_counter : unsigned(7 downto 0);
  signal addrb_CTP_SPY : std_logic_vector(7 downto 0);

  signal dinb_CTP_SPY: std_logic_vector(61 downto 0);
  signal doutb_CTP_SPY: std_logic_vector(61 downto 0);
  
  signal start_playback_r, start_playback_rr : std_logic;

  
  
  component Stretch_10 is
    port (
      unstretched_IN : in  std_logic;
      stretched_OUT  : out std_logic;
      clk            : in  std_logic);
  end component Stretch_10;

  
  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  
  signal data_vme_from_below  : arr_16(8 downto 0);
  signal bus_drive_from_below : std_logic_vector(8 downto 0);
  

  
  component vme_outreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk         : in  std_logic;
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0);
      read_detect : out std_logic);
  end component vme_outreg_notri;

  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;

  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;

  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;
  
  

  --first "-1" because the clock line is skipped...
  signal bit_error_detect: std_logic_vector(numbits_in_CTP_connector*2 - 1 downto 0);
  signal bit_error_latch:  std_logic_vector(numbits_in_CTP_connector*2 - 1 downto 0);
  signal all_null : std_logic_vector(numbits_in_CTP_connector*2 - 1 downto 0);

  signal bit_error_counter: unsigned(31 downto 0);
  signal bit_error_counter_next: unsigned(31 downto 0);
  
  signal data_to_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET : std_logic_vector(15 downto 0);
  signal data_from_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET : std_logic_vector(15 downto 0);
  signal counter_reset : std_logic;
  signal counter_reset_unstretched : std_logic;
  signal counter_reset_r : std_logic;
  signal counter_reset_rr : std_logic;


  signal data_to_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS : std_logic_vector(15 downto 0);
  signal data_from_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS : std_logic_vector(15 downto 0);

  signal data_to_vme_reg_ro_ctp_spy_mem_check_error_0 : std_logic_vector(15 downto 0);
  signal data_to_vme_reg_ro_ctp_spy_mem_check_error_1 : std_logic_vector(15 downto 0);
  signal data_to_vme_reg_ro_ctp_spy_mem_check_error_2 : std_logic_vector(15 downto 0);
  signal data_to_vme_reg_ro_ctp_spy_mem_check_error_3 : std_logic_vector(15 downto 0);
  
  
begin

  
  all_null<= (others=>'0');

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_from_below,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_from_below);

  
  vme_inreg_REG_RW_CTP_OUTPUT_COUNTER_RESET: vme_inreg_notri
    generic map (
      ia_vme  => ADDR_REG_RW_CTP_OUTPUT_COUNTER_RESET ,
      width   => 16)
    port map (
      clk            => buf_clk40 ,
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      data_from_vme  => data_from_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET,
      data_to_vme    => data_to_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET,  
      addr_vme       => addr_vme,
      read_detect    => open,
      write_detect   => counter_reset_unstretched ,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_from_below (0),
      bus_drive      => bus_drive_from_below (0));
  
  data_to_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET<=data_from_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET;

  Stretch_10_counter_reset : Stretch_10
    port map (
      unstretched_IN  => counter_reset_unstretched ,
      stretched_OUT   => counter_reset,
      clk             => buf_clk40 );


  CMX_generic_spy_mem_control_FSM_inst: entity work.CMX_generic_spy_mem_control_FSM
    generic map (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD     => ADDR_REG_RW_CTP_SPY_MEM_WORD ,
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL  => ADDR_REG_RW_CTP_SPY_MEM_CONTROL,
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS   => ADDR_REG_RO_CTP_SPY_MEM_STATUS,
      num_external_RAMS                    => 1)
    port map (
      clk                    => buf_clk40,
      ncs                    => ncs,
      rd_nwr                 => rd_nwr,
      ds                     => ds,
      addr_vme               => addr_vme,
      data_vme_in            => data_vme_in,
      data_vme_out           => data_vme_from_below(1),
      bus_drive              => bus_drive_from_below(1),
      mode_control           => mode_control_CTP_SPY,
      ena                    => ena_CTP_SPY,
      wea                    => wea_CTP_SPY(0),
      addra                  => addra_CTP_SPY,
      mem_select_address     => open,
      dina                   => dina_CTP_SPY,
      douta                  => douta_CTP_SPY,
      port_b_master_inhibit  => port_b_master_inhibit_CTP_SPY );
  

  
  vme_inreg_REG_RW_CTP_SPY_MEM_START_ADDRESS: vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_CTP_SPY_MEM_START_ADDRESS,
      width =>16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_from_below (2),
      bus_drive      => bus_drive_from_below (2),
      data_from_vme  => data_from_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS,
      data_to_vme    => data_to_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS
      );
  data_to_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS<=data_from_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS;



  
  --process to locally register the inhibit signal;
  process(buf_clk40,pll_locked)
  begin
    if pll_locked/='1' then
      spy_write_inhibit_r<='0';
    elsif rising_edge(buf_clk40) then
      spy_write_inhibit_r<=spy_write_inhibit;
    end if;
  end process;
  process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      spy_write_inhibit_rr<=spy_write_inhibit_r;
    end if;
  end process;
  
  

  blk_mem_A8x62_B8x62_CTP_SPY: blk_mem_A8x62_B8x62
    port map (
      clka   => buf_clk40,             
      ena    => ena_CTP_SPY,
      wea    => wea_CTP_SPY,
      addra  => addra_CTP_SPY,
      dina   => dina_CTP_SPY,
      douta  => douta_CTP_SPY,
      clkb   => buf_clk40,
      enb    => enb_CTP_SPY_inhibited,
      web    => web_CTP_SPY_inhibited,
      addrb  => addrb_CTP_SPY,
      dinb   => dinb_CTP_SPY,
      doutb  => doutb_CTP_SPY);

  
  --data coming in from the adder module
  dinb_CTP_SPY<= data;

  
  addrb_CTP_SPY<=std_logic_vector(addrb_CTP_SPY_counter);

  
  process(buf_clk40,pll_locked)
  begin
    if pll_locked/='1' then
      start_playback_r<='0';
    elsif rising_edge(buf_clk40) then
      start_playback_r<=start_playback;
    end if;
  end process;
  spy_source_addr_proc: process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      --a local register (one copy for each of the memories)to ease timing
      start_playback_rr<=start_playback_r;
      if start_playback_rr='0' then
        addrb_CTP_SPY_counter<=addrb_CTP_SPY_counter+1;
      else
        addrb_CTP_SPY_counter<=unsigned(
          data_from_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS(7 downto 0));
      end if;
    end if;
  end process;

  --create local registers for the master inhibit to aid timing closure
  local_buf_master_inhibit_system: process(buf_clk40,pll_locked)
  begin
    if pll_locked='0' then
      port_b_master_inhibit_CTP_SPY_r<='1';
      web_CTP_SPY_r<='0';
      enb_CTP_SPY_r<='0';
    elsif rising_edge(buf_clk40) then
      port_b_master_inhibit_CTP_SPY_r<=port_b_master_inhibit_CTP_SPY;
      web_CTP_SPY_r<=web_CTP_SPY;
      enb_CTP_SPY_r<=enb_CTP_SPY;
    end if;
  end process local_buf_master_inhibit_system;

  web_CTP_SPY_inhibited(0)<=web_CTP_SPY_r and (not port_b_master_inhibit_CTP_SPY_r) and (not spy_write_inhibit_rr);
  enb_CTP_SPY_inhibited<=enb_CTP_SPY_r and (not port_b_master_inhibit_CTP_SPY_r);
  


  
  --this will make an error detection register that in turn will be used to
  --generate a latch; also an no-error run length counter is made in this process
  error_detect_process: process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      if counter_reset_rr/='1' then
        if bit_error_latch/=all_null or std_logic_vector(bit_error_counter)=x"ffffffff" then --bit_error_detect(i_mem_source)/=x"000000000000" or bit_error_counter(i_mem_source)/=to_unsigned(0,32) or std_logic_vector(bit_error_counter(i_mem_source))=x"ffffffff" then
          bit_error_counter_next<=bit_error_counter;
        else
          bit_error_counter_next<=bit_error_counter+1;
        end if;
      else
        bit_error_counter_next<=to_unsigned(0,32);
      end if;
      

      bit_error_counter<=bit_error_counter_next;
      bit_error_detect<=doutb_CTP_SPY xor (not data_r);
    end if;
  end process error_detect_process;
  process(buf_clk40, pll_locked)
  begin
    if pll_locked/='1' then
      data_r<=(others=>'0');
    elsif rising_edge(buf_clk40) then
      if mode_control_CTP_SPY /= CONST_DPR_CONTROL_PLAYBACK then
        data_r<= not data;
      else
        data_r<=not doutb_CTP_SPY;
      end if;
    end if;
  end process;


  --connect the output data
  --stupendous numbering scheme... 
  sdr_data_out(0)(30 downto 0)<=data_r(30 downto 0);
  sdr_data_out(0)(31)<=buf_clk40_center;
  sdr_data_out(1)(30 downto 0)<=data_r(61 downto 31);
  sdr_data_out(1)(31)<=buf_clk40_center;


  
  --double register to close timing
  process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      counter_reset_rr<=counter_reset_r;
    end if;
  end process;
  process(buf_clk40,pll_locked)
  begin
    if pll_locked/='1' then
      counter_reset_r<='0';
    elsif rising_edge(buf_clk40) then
      counter_reset_r<=counter_reset;
    end if;
  end process;

  
  gen_err_latch_bit: for i_bit in 0 to (numbits_in_CTP_connector*2 - 1) generate

    
    --resettable 'latch' (so not really a latch) that is set if there is an error
    --on a given bit 
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then

        if counter_reset_rr/='1' then
          if bit_error_detect(i_bit)='1' then
            bit_error_latch(i_bit)<='1';
          end if;
        else
          bit_error_latch(i_bit)<='0';
        end if;
        
      end if;
    end process;
    
  end generate gen_err_latch_bit;

  --assign latches as data to the registers
  data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_0<=bit_error_latch(15 downto 0);
  data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_1<=bit_error_latch(31 downto 16);
  data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_2<=bit_error_latch(47 downto 32);
  data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_3(13 downto 0)<=bit_error_latch(61 downto 48);
  data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_3(15 downto 14)<=(others=>'0');
  
  
  
  vme_outreg_REG_RO_CTP_SPY_MEM_CHECK_ERROR_0: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CTP_SPY_MEM_CHECK_ERROR+0,
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_0,
      data_vme       => data_vme_from_below (3),
      bus_drive      => bus_drive_from_below (3));

  
  vme_outreg_REG_RO_CTP_SPY_MEM_CHECK_ERROR_1: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CTP_SPY_MEM_CHECK_ERROR+2,
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_1,
      data_vme       => data_vme_from_below (4),
      bus_drive      => bus_drive_from_below (4));

  
  vme_outreg_REG_RO_CTP_SPY_MEM_CHECK_ERROR_2: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CTP_SPY_MEM_CHECK_ERROR+4,
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_2,
      data_vme       => data_vme_from_below (5),
      bus_drive      => bus_drive_from_below (5));

  vme_outreg_REG_RO_CTP_SPY_MEM_CHECK_ERROR_3: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CTP_SPY_MEM_CHECK_ERROR+6,
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => data_to_vme_REG_RO_CTP_SPY_MEM_CHECK_ERROR_3,
      data_vme       => data_vme_from_below (6),
      bus_drive      => bus_drive_from_below (6));

  
  
  vme_outreg_REG_RO_CTP_SPY_MEM_NOERROR_COUNTER_0: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CTP_SPY_MEM_NOERROR_COUNTER,
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => std_logic_vector(bit_error_counter(15 downto 0)),
      data_vme       => data_vme_from_below (7),
      bus_drive      => bus_drive_from_below (7));

  vme_outreg_REG_RO_CTP_SPY_MEM_NOERROR_COUNTER_1: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CTP_SPY_MEM_NOERROR_COUNTER+2,
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => std_logic_vector(bit_error_counter(31 downto 16)),
      data_vme       => data_vme_from_below (8),
      bus_drive      => bus_drive_from_below (8));
  
  
  
  
  --port enables - we enable B port when verifying, spying and playing back. Write
  --is enabled only when spying
  enb_CTP_SPY<='1' when mode_control_CTP_SPY=CONST_DPR_CONTROL_SPY
                or mode_control_CTP_SPY=CONST_DPR_CONTROL_VERIFY
                or mode_control_CTP_SPY=CONST_DPR_CONTROL_PLAYBACK
                else '0';
  web_CTP_SPY<='1' when mode_control_CTP_SPY=CONST_DPR_CONTROL_SPY else '0';


  
  
  
end Behavioral;