CMX_crate_cable_output_module.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMX_local_package.all;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;


entity CMX_crate_cable_output_module is 

  port(
    --data in to be sent out
    data : in std_logic_vector( numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
    --data to be sent out (connect this to the top level output ports)
    ddr_data_out : out arr_RTM(num_RTM_cables-1 downto 0);
    buf_clk40 : in std_logic;
    buf_clk40_center : in std_logic;
    pll_locked : in std_logic;
    start_playback : in std_logic;
    --inhibit signal for writing to the spy memories
    spy_write_inhibit : in std_logic;
    --VME control:
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;
    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
        
end CMX_crate_cable_output_module;


architecture Behavioral of CMX_crate_cable_output_module is

  constant mem_select_addr_width : integer := addr_port_width(num_RTM_cables);
  
  component CMX_cable_clocked_80Mbps_output_module is
    generic (
      numbits_in_cable_connector : integer);
    port (
      data             : in  std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
      ddr_data_out     : out std_logic_vector(numbits_in_cable_connector downto 0);
      buf_clk40        : in  std_logic;
      buf_clk40_center : in  std_logic;
      buf_clk200       : in  std_logic;
      pll_locked       : in  std_logic;
      del_array        : in  cable_del_array_type(numbits_in_cable_connector downto 0);
      upload_delays    : in  std_logic);
  end component CMX_cable_clocked_80Mbps_output_module;

  signal data_sdr                       : arr_RTM_sdr;
  signal data_sdr_r_SYSTEM              : arr_RTM_sdr;--need this for
                                                        --comparison to data
                                                        --from RAM

  
  
  component blk_mem_A8x52_B8x52_1clock is
    port (
      clka  : IN  STD_LOGIC;
      ena   : IN  STD_LOGIC;
      wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dina  : IN  STD_LOGIC_VECTOR(51 DOWNTO 0);
      douta : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
      clkb  : IN  STD_LOGIC;
      enb   : IN  STD_LOGIC;
      web   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addrb : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dinb  : IN  STD_LOGIC_VECTOR(51 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(51 DOWNTO 0));
  end component blk_mem_A8x52_B8x52_1clock;


  signal counter_reset, counter_reset_unstretched: std_logic;
  component Stretch_10 is
    port (
      unstretched_IN : in  std_logic;
      stretched_OUT  : out std_logic;
      clk            : in  std_logic);
  end component Stretch_10;

  signal counter_reset_r_SYSTEM,counter_reset_rr_SYSTEM : std_logic_vector(numactchan-1 downto 0);

  signal data_from_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET : std_logic_vector (15 downto 0);  --actual value is
                                                                               --ignored but
                                                                               --supplied for sw check
  signal data_to_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET   : std_logic_vector (15 downto 0);

  
  signal all_null : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);

  component CMX_generic_spy_mem_control_FSM is
    generic (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD    : integer;
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL : integer;
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS  : integer;
      num_external_RAMS                   : positive);
    port (
      clk                   : in    std_logic;
      ncs                   : in    std_logic;
      rd_nwr                : in    std_logic;
      ds                    : in    std_logic;
      addr_vme              : in    std_logic_vector (15 downto 0);
      data_vme_in   : in    std_logic_vector (15 downto 0);
      data_vme_out  : out   std_logic_vector (15 downto 0);
      bus_drive     : out   std_logic;
      mode_control          : out   std_logic_vector(3 downto 0);
      ena                   : out   std_logic;
      wea                   : out   std_logic;
      addra                 : out   std_logic_vector(7 DOWNTO 0);
      mem_select_address    : out   std_logic_vector(addr_port_width(num_external_RAMS)-1 downto 0);
      dina                  : out   std_logic_vector;
      douta                 : in    std_logic_vector;
      port_b_master_inhibit : out   std_logic);
  end component CMX_generic_spy_mem_control_FSM;

  

  
  signal mode_control_RTM_OUTPUT_SPY_SYSTEM : std_logic_vector(3 downto 0);     
  signal ena_RTM_OUTPUT_SPY_SYSTEM : std_logic;                 
  signal wea_RTM_OUTPUT_SPY_SYSTEM : std_logic;       
  signal addra_RTM_OUTPUT_SPY_SYSTEM : std_logic_vector(7 DOWNTO 0);
  signal mem_select_address_RTM_OUTPUT_SPY_SYSTEM : std_logic_vector(addr_port_width(num_RTM_cables)-1 downto 0);
  signal dina_RTM_OUTPUT_SPY_SYSTEM : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal douta_RTM_OUTPUT_SPY_SYSTEM : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM : std_logic;

  signal ena_rtm_output_spy_system_individual : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal wea_rtm_output_spy_system_individual : arr_1(num_RTM_cables-1 downto 0);   
  signal douta_rtm_output_spy_system_individual : arr_RTM_sdr;
  signal enb_rtm_output_spy_system_individual   : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_output_spy_system_individual   : arr_1(num_RTM_cables-1 downto 0);   
  signal addrb_rtm_output_spy_system_individual : arr_8(num_RTM_cables-1 downto 0);   
  signal dinb_rtm_output_spy_system_individual  : arr_RTM_sdr;
  signal doutb_rtm_output_spy_system_individual : arr_RTM_sdr;

  signal addrb_RTM_OUTPUT_SPY_SYSTEM_counter : arr_ctr_8bit(num_RTM_cables-1 downto 0);

  signal port_b_master_inhibit_rtm_output_spy_system_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_output_spy_system_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_output_spy_system_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal port_b_master_inhibit_rtm_output_spy_system_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_output_spy_system_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_output_spy_system_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_output_spy_system : std_logic;
  signal web_rtm_output_spy_system : std_logic;
  
  signal spy_write_inhibit_r_system : std_logic_vector(num_RTM_cables-1 downto 0);
  signal spy_write_inhibit_rr_system : std_logic_vector(num_RTM_cables-1 downto 0);
  
  signal start_playback_r_system : std_logic_vector(num_RTM_cables-1 downto 0);
  signal start_playback_rr_system : std_logic_vector(num_RTM_cables-1 downto 0);
  
  
  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  signal data_vme_from_below  : arr_16(4+9*num_RTM_cables+2 downto 0);
  signal bus_drive_from_below : std_logic_vector(4+9*num_RTM_cables+2 downto 0);
  
  
  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;
  
  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;
  
  component vme_outreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk         : in  std_logic;
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0);
      read_detect : out std_logic);
  end component vme_outreg_notri;


  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;


  signal data_to_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS : std_logic_vector(15 downto 0);
  signal data_from_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS : std_logic_vector(15 downto 0);

  
  
  signal data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_0 : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_1 : arr_16(num_RTM_cables-1 downto 0);
  
  signal bit_error_counter_system_next : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_counter_system : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_latch_system : arr_26(num_RTM_cables-1 downto 0); 
  signal bit_error_detect_system : arr_52(num_RTM_cables-1 downto 0);   

  signal sdr_data_after_mux : arr_RTM_sdr;

begin

  all_null<=(others=>'0');

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_from_below,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_from_below);

  
  
  vme_inreg_REG_RW_RTM_OUTPUT_COUNTER_RESET: vme_inreg_notri
    generic map (
      ia_vme  => ADDR_REG_RW_RTM_OUTPUT_COUNTER_RESET ,
      width   => 16)
    port map (
      clk            => buf_clk40 ,
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      data_from_vme  => data_from_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET,
      data_to_vme    => data_to_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET,  
      addr_vme       => addr_vme,
      read_detect    => open,
      write_detect   => counter_reset_unstretched ,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_from_below (0),
      bus_drive      => bus_drive_from_below (0));
  
  data_to_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET<=data_from_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET;

  Stretch_10_counter_reset : Stretch_10
    port map (
      unstretched_IN  => counter_reset_unstretched ,
      stretched_OUT   => counter_reset,
      clk             => buf_clk40 );



  CMX_generic_spy_mem_control_FSM_inst_SYSTEM: entity work.CMX_generic_spy_mem_control_FSM
    generic map (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD     => ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_WORD ,
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL  => ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_CONTROL ,
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS   => ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_STATUS ,
      num_external_RAMS                    => num_RTM_cables)
    port map (
      clk                    => buf_clk40,
      ncs                    => ncs,
      rd_nwr                 => rd_nwr,
      ds                     => ds,
      addr_vme               => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_from_below (1),
      bus_drive      => bus_drive_from_below (1),
      mode_control           => mode_control_RTM_OUTPUT_SPY_SYSTEM ,
      ena                    => ena_RTM_OUTPUT_SPY_SYSTEM ,
      wea                    => wea_RTM_OUTPUT_SPY_SYSTEM ,
      addra                  => addra_RTM_OUTPUT_SPY_SYSTEM ,
      mem_select_address     => mem_select_address_RTM_OUTPUT_SPY_SYSTEM,
      dina                   => dina_RTM_OUTPUT_SPY_SYSTEM,
      douta                  => douta_RTM_OUTPUT_SPY_SYSTEM ,
      port_b_master_inhibit  => port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM);

  
  channel_gen: for channel in 0 to num_RTM_cables-1 generate


    
    data_sdr(channel)<=data( (channel+1)*2*numbits_in_RTM_connector -1 downto channel*2*numbits_in_RTM_connector);
    
    --process to locally register the inhibit signal in system domain and yet again;
    process(buf_clk40,pll_locked)
    begin
      if pll_locked/='1' then
        spy_write_inhibit_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        spy_write_inhibit_r_SYSTEM(channel)<=spy_write_inhibit;
      end if;
    end process;
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        spy_write_inhibit_rr_SYSTEM(channel)<=spy_write_inhibit_r_SYSTEM(channel);
      end if;
    end process;


    
    
    CMX_cable_clocked_80Mbps_output_module_inst: CMX_cable_clocked_80Mbps_output_module
      generic map (
        numbits_in_cable_connector  => numbits_in_RTM_connector)
      port map (
        data              => sdr_data_after_mux(channel),
        ddr_data_out      => ddr_data_out(channel),
        buf_clk40         => buf_clk40,
        buf_clk40_center  => buf_clk40_center ,
        buf_clk200        => '0',
        pll_locked        => pll_locked,
        del_array         =>  (others=>(others =>'0')),
        upload_delays     => '0');
    
    --CMX_cable_clocked_80Mbps_input_module_inst: entity work.CMX_cable_clocked_80Mbps_input_module
    --  generic map (
    --    numbits_in_cable_connector => numbits_in_RTM_connector)
    --  port map (
    --    data            => data_sdr(channel),
    --    parity_error    => parity_error_sig(channel),
    --    forwarded_clock => forwarded_clock(channel),
    --    ddr_data_in     => ddr_data_in(channel),
    --    buf_clk40       => buf_clk40,
    --    buf_clk200      => '0',
    --    pll_locked      => pll_locked,
    --    del_array       => (others=>(others=>'0')),
    --    upload_delays   => '0');


    
    blk_mem_A8x52_B8x52_1clock_SYSTEM: blk_mem_A8x52_B8x52_1clock
      port map (
        clka   => buf_clk40,
        ena    => ena_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        wea    => wea_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        addra  => addra_RTM_OUTPUT_SPY_SYSTEM ,
        dina   => dina_RTM_OUTPUT_SPY_SYSTEM ,
        douta  => douta_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        clkb   => buf_clk40,
        enb    => enb_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        web    => web_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        addrb  => addrb_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        dinb   => dinb_RTM_OUTPUT_SPY_SYSTEM_individual(channel),
        doutb  => doutb_RTM_OUTPUT_SPY_SYSTEM_individual(channel));


    assert (1=0) report "crate cable output; mem_select_addr_width:"&integer'IMAGE(mem_select_addr_width)&", num_RTM_cables:"&integer'IMAGE(num_RTM_cables) severity NOTE;


    
    gen_sig_select_mux: if num_RTM_cables/=1 generate
      assert (1=0) report "generating a mux for the memory signals" severity NOTE;
      -- select the control signals based on the value of the mem_select_address_RTM_OUTPUT_SPY_SYSTEM
      ena_RTM_OUTPUT_SPY_SYSTEM_individual(channel) <= ena_RTM_OUTPUT_SPY_SYSTEM when mem_select_address_RTM_OUTPUT_SPY_SYSTEM
                                                       =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';
    
      wea_RTM_OUTPUT_SPY_SYSTEM_individual(channel)(0) <= wea_RTM_OUTPUT_SPY_SYSTEM when mem_select_address_RTM_OUTPUT_SPY_SYSTEM
                                                          =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';

      --this should generate a n-1 multiplexer with douta_RTM_OUTPUT_SPY_SYSTEM as output
      --if there are moren than 1 rtm_output sources; if there is just one rtm_output source 
      --I expect the 1-1 'mux' will be optimized out.
      douta_RTM_OUTPUT_SPY_SYSTEM<=douta_RTM_OUTPUT_SPY_SYSTEM_individual(channel) when  mem_select_address_RTM_OUTPUT_SPY_SYSTEM
                                    =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else (others=>'Z');
    end generate gen_sig_select_mux;
    gen_no_sig_select_mux: if num_RTM_cables=1 generate
      assert (1=0) report "no mux needed, only one output cable, connecting signals straight" severity NOTE;
      ena_RTM_OUTPUT_SPY_SYSTEM_individual(channel) <= ena_RTM_OUTPUT_SPY_SYSTEM;
      wea_RTM_OUTPUT_SPY_SYSTEM_individual(channel)(0) <= wea_RTM_OUTPUT_SPY_SYSTEM;
      douta_RTM_OUTPUT_SPY_SYSTEM<=douta_RTM_OUTPUT_SPY_SYSTEM_individual(channel);
    end generate gen_no_sig_select_mux;
    
    dinb_RTM_OUTPUT_SPY_SYSTEM_individual(channel)<=data( ((channel+1)*numbits_in_RTM_connector*2)-1 downto ((channel)*numbits_in_RTM_connector*2) )  ; 
    addrb_RTM_OUTPUT_SPY_SYSTEM_individual(channel)<=std_logic_vector(addrb_RTM_OUTPUT_SPY_SYSTEM_counter(channel));



    
    process(buf_clk40,pll_locked)
    begin
      if pll_locked/='1' then
        start_playback_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        start_playback_r_SYSTEM(channel)<=start_playback;
      end if;
    end process;
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        --a local register (one copy for each of the memories)to ease timing
        start_playback_rr_SYSTEM(channel)<=start_playback_r_SYSTEM(channel);
      end if;
    end process;
    
    
    spy_system_addr_proc: process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        if start_playback_rr_SYSTEM(channel)='0' then
          addrb_RTM_OUTPUT_SPY_SYSTEM_counter(channel)<=addrb_RTM_OUTPUT_SPY_SYSTEM_counter(channel)+1;
        else
          addrb_RTM_OUTPUT_SPY_SYSTEM_counter(channel)<=unsigned(
            data_from_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS(7 downto 0));
        end if;
      end if;
    end process;
    
    

    --create local registers for the master inhibit to aid timing closure
    local_buf_master_inhibit_system: process(buf_clk40,pll_locked)
    begin
      if pll_locked='0' then
        port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)<='1';
        web_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)<='0';
        enb_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)<=port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM_split(channel);
        web_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)<=web_RTM_OUTPUT_SPY_SYSTEM_split(channel);
        enb_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)<=enb_RTM_OUTPUT_SPY_SYSTEM_split(channel);
      end if;
    end process local_buf_master_inhibit_system;

    web_RTM_OUTPUT_SPY_SYSTEM_individual(channel)(0)<=web_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel) and (not port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel)) and (not spy_write_inhibit_rr_SYSTEM(channel));
    enb_RTM_OUTPUT_SPY_SYSTEM_individual(channel)<=enb_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel) and (not port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM_r_SYSTEM(channel));
    
    
    port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM_split(channel)<=port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM;
    enb_RTM_OUTPUT_SPY_SYSTEM_split(channel)<=enb_RTM_OUTPUT_SPY_SYSTEM;
    web_RTM_OUTPUT_SPY_SYSTEM_split(channel)<=web_RTM_OUTPUT_SPY_SYSTEM;


       --WTF
    --select the data going out  
    sdr_data_after_mux(channel)<=data( (channel+1)*2*numbits_in_RTM_connector-1
                                       downto channel*2*numbits_in_RTM_connector )
                                  when mode_control_RTM_OUTPUT_SPY_SYSTEM/=CONST_DPR_CONTROL_PLAYBACK
                                  else doutb_RTM_OUTPUT_SPY_SYSTEM_individual(channel);
    
    --this will make an error detection register that in turn will be used to
    --generate a latch; also an no-error run length counter is made in this process

    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        data_sdr_r_SYSTEM(channel)<=data_sdr(channel);
      end if;
    end process;
    
    error_detect_process_system: process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        if counter_reset_rr_SYSTEM(channel)/='1' then
          if bit_error_latch_system(channel)/=all_null or bit_error_counter_system(channel)=max_ctr32 then
            bit_error_counter_system_next(channel)<=bit_error_counter_system(channel);
          else
            bit_error_counter_system_next(channel)<=bit_error_counter_system(channel)+1;
          end if;
        else
          bit_error_counter_system_next(channel)<=to_unsigned(0,32);
        end if;  
        bit_error_counter_system(channel)<=bit_error_counter_system_next(channel);
        bit_error_detect_system(channel)<=doutb_RTM_OUTPUT_SPY_SYSTEM_individual(channel) xor data_sdr_r_SYSTEM(channel);
      end if;
    end process error_detect_process_system;

    gen_err_latch_bit_system: for i_bit in 0 to numbits_in_RTM_connector -1 generate
      --resettable 'latch' (so not really a latch) that is set if there is an error
      --on a given bit 
      process(buf_clk40)
      begin
        if rising_edge(buf_clk40) then
          if counter_reset_rr_SYSTEM(channel)/='1' then
            if bit_error_detect_system(channel)(i_bit)='1' or bit_error_detect_system(channel)(i_bit+numbits_in_RTM_connector)='1' then
              bit_error_latch_system(channel)(i_bit)<='1';
            end if;
          else
            bit_error_latch_system(channel)(i_bit)<='0';
          end if;
        end if;
      end process;
    end generate gen_err_latch_bit_system;



    -- create counter reset registers
    --double register to close timing
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        counter_reset_rr_SYSTEM(channel)<=counter_reset_r_SYSTEM(channel);
      end if;
    end process;
    process(buf_clk40,pll_locked)
    begin
      if pll_locked/='1' then
        counter_reset_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        counter_reset_r_SYSTEM(channel)<=counter_reset;
      end if;
    end process;

    --assign latches as data to the registers

    data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_0(channel)<=bit_error_latch_system(channel)(15 downto 0);
    data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_1(channel)(numbits_in_RTM_connector-16-1 downto 0)<=bit_error_latch_system(channel)(numbits_in_RTM_connector-1 downto 16);
    data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_1(channel)(15 downto numbits_in_RTM_connector-16)<=(others=>'0');
    
    vme_outreg_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_0: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR+(4*channel),
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_0(channel),
        data_vme     => data_vme_from_below (2+2*channel),
        bus_drive    => bus_drive_from_below (2+2*channel));

    vme_outreg_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_1: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR+(4*channel)+2,
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_1(channel),
        data_vme     => data_vme_from_below (2+2*channel+1),
        bus_drive    => bus_drive_from_below (2+2*channel+1));

    
    
  end generate channel_gen;
  

  
  --port enables - we enable B port when verifying, spying and playing back. Write
  --is enabled only when spying
  --no playback for the source spy


  enb_RTM_OUTPUT_SPY_SYSTEM <='1' when mode_control_RTM_OUTPUT_SPY_SYSTEM=CONST_DPR_CONTROL_SPY
                           or   mode_control_RTM_OUTPUT_SPY_SYSTEM=CONST_DPR_CONTROL_VERIFY
                           or   mode_control_RTM_OUTPUT_SPY_SYSTEM=CONST_DPR_CONTROL_PLAYBACK
                           else '0';
  web_RTM_OUTPUT_SPY_SYSTEM<='1' when mode_control_RTM_OUTPUT_SPY_SYSTEM=CONST_DPR_CONTROL_SPY else '0';





    
  vme_inreg_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS: vme_inreg_notri_async
  generic map (
    ia_vme  => ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS,
    width =>16)
  port map (
    ncs            => ncs,
    rd_nwr         => rd_nwr,
    ds             => ds,
    addr_vme       => addr_vme,
    data_vme_in    => data_vme_in,
    data_vme_out   => data_vme_from_below (2+2*num_RTM_cables),
    bus_drive      => bus_drive_from_below (2+2*num_RTM_cables),
    data_from_vme  => data_from_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS,
    data_to_vme    => data_to_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS);
  data_to_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS<=data_from_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS; 
  
  
    
end Behavioral;