CMX_clock_manager.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
use work.CMX_VME_defs.all;

entity CMX_clock_manager is
  
  port (
    I_DS1 : in std_logic;                   -- inputs from the top level pins
    IB_DS1 : in std_logic; 
    buf_clk40 : out std_logic;          -- globally buffered clocks
    buf_clk40_90o :out std_logic;
    buf_clk40_m180o : out std_logic;
    buf_clk40_m90o : out std_logic;
    buf_clk320 : out std_logic;
    buf_clk160 : out std_logic;
    buf_clk200 : out std_logic;
    pll_locked : out std_logic;
    I_DS2 : in std_logic;
    IB_DS2 : in std_logic;
    buf_clk40_ds2: out std_logic;
    pll_locked_ds2: out std_logic;
    ncs           : in    std_logic;
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in  std_logic_vector (15 downto 0);
    data_vme_out  : out std_logic_vector (15 downto 0);
    bus_drive     : out std_logic
    );
end CMX_clock_manager;

architecture Behavioral of CMX_clock_manager is

  signal clk40_ibufgds1,clk40_ibufgds2 : std_logic;     -- outside clock buffered at the input
                                        -- pin pair, drives the MMCM

  signal FEEDBACK_CLK_DS1 : std_logic;      -- feedback clock for the MMCM
  signal FEEDBACK_CLK_DS2 : std_logic;      -- feedback clock for the MMCM

  signal clk40, clk40_90o, clk40_m90o, clk40_m180o, clk320, clk160, clk200 : std_logic;  -- unbuffered clocks, mmcm
                                                                -- outputs (ds1)
  signal buf_clk40_sig : std_logic; --local copy of the buggered ds1 40 MHz
                                    --clock for use in the pll status reg
  
  signal clk40_ds2: std_logic; --mmcm 2 output
  
  
  signal pll_locked_ds1_sig, pll_locked_ds2_sig : std_logic;

  
----   component IBUFGDS
----     port (
----       I : in std_logic;
----       IB : in std_logic;
----       O : out std_logic); 
----   end component;

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  signal data_vme_out_local : arr_16(1 downto 0);
  signal bus_drive_local : std_logic_vector(1  downto 0);
  
  
  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;


  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;
  
  signal data_from_vme_REG_RW_CLOCK_MANAGER_RESET : std_logic_vector (15 downto 0);
  signal data_to_vme_REG_RW_CLOCK_MANAGER_RESET   : std_logic_vector (15 downto 0);

  signal data_to_vme_REG_RO_CLOCK_MANAGER_STATUS   : std_logic_vector (15 downto 0);
  
  
begin

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local);
  
  
  IBUFGDS_inst_ds1: IBUFGDS
    generic map (
      DIFF_TERM  => TRUE, -- Differential Termination 
      IBUF_LOW_PWR  => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD  => "LVDS_25")
    port map (
      I  => I_DS1,
      IB  => IB_DS1,
      O  => clk40_ibufgds1);

  IBUFGDS_inst_ds2: IBUFGDS
    generic map (
      DIFF_TERM  => TRUE, -- Differential Termination 
      IBUF_LOW_PWR  => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD  => "LVDS_25")
    port map (
      I  => I_DS2,
      IB  => IB_DS2 ,
      O  => clk40_ibufgds2);

 --the MMCM for the global reference for iodelay
  MMCM_BASE_inst_ds1 : MMCM_BASE
    generic map (
      BANDWIDTH  => "OPTIMIZED",  -- Jitter programming ("HIGH","LOW","OPTIMIZED")
      CLKFBOUT_MULT_F  => 32.0,    -- Multiply value for all CLKOUT (5.0-64.0).
                                  -- F_VCO = 32*40 MHz =1280 MHz
      CLKFBOUT_PHASE  => 0.0,     -- Phase offset in degrees of CLKFB (0.00-360.00).
      CLKIN1_PERIOD  => 24.95,      -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
      -- MHz) WTF: 25ns = 40MHz, 24.95=40.08 MHz - actual LHC BC
      CLKOUT0_DIVIDE_F => 6.4,   -- Divide amount for CLKOUT0 (1.000-128.000).
                                       -- 200 MHz
      -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
      CLKOUT0_DUTY_CYCLE  => 0.5,
      CLKOUT1_DUTY_CYCLE  => 0.5,
      CLKOUT2_DUTY_CYCLE  => 0.5,
      CLKOUT3_DUTY_CYCLE  => 0.5,
      CLKOUT4_DUTY_CYCLE  => 0.5,
      CLKOUT5_DUTY_CYCLE  => 0.5,
      CLKOUT6_DUTY_CYCLE  => 0.5,
      -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
      CLKOUT0_PHASE  => 0.0,
      CLKOUT1_PHASE  => 0.0,
      CLKOUT2_PHASE  => 0.0,-- -45.0,
      CLKOUT3_PHASE  => 0.0,
      CLKOUT4_PHASE  => 90.0,
      CLKOUT5_PHASE  => 0.0,
      CLKOUT6_PHASE  => -90.0,
      -- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
      CLKOUT1_DIVIDE  => 32,             --40 MHz
      CLKOUT2_DIVIDE  => 4,              --320 MHz
      CLKOUT3_DIVIDE  => 8,              --160 MHz
      CLKOUT4_DIVIDE  => 32,
      CLKOUT5_DIVIDE  => 32,
      CLKOUT6_DIVIDE  => 32,
      CLKOUT4_CASCADE  => FALSE,  -- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
      CLOCK_HOLD  => FALSE,       -- Hold VCO Frequency (TRUE/FALSE)
      DIVCLK_DIVIDE  => 1,        -- Master division value (1-80)
      REF_JITTER1  => 0.0,        -- Reference input jitter in UI (0.000-0.999).
      STARTUP_WAIT  => FALSE      -- Not supported. Must be set to FALSE.
      )
    port map (
      -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
      CLKOUT0  => clk200,     -- 1-bit output: CLKOUT0 output
      CLKOUT0B  => open,   -- 1-bit output: Inverted CLKOUT0 output
      CLKOUT1  => clk40,     -- 1-bit output: CLKOUT1 output
      CLKOUT1B  => clk40_m180o,   -- 1-bit output: Inverted CLKOUT1 output
      CLKOUT2  => clk320,     -- 1-bit output: CLKOUT2 output
      CLKOUT2B  => open,   -- 1-bit output: Inverted CLKOUT2 output
      CLKOUT3  => clk160,     -- 1-bit output: CLKOUT3 output
      CLKOUT3B  => open,   -- 1-bit output: Inverted CLKOUT3 output
      CLKOUT4  => clk40_90o,     -- 1-bit output: CLKOUT4 output
      CLKOUT5  => open,     -- 1-bit output: CLKOUT5 output
      CLKOUT6  => clk40_m90o,     -- 1-bit output: CLKOUT6 output
      -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
      CLKFBOUT  => FEEDBACK_CLK_DS1 ,   -- 1-bit output: Feedback clock output
      CLKFBOUTB  => open, -- 1-bit output: Inverted CLKFBOUT output
      -- Status Port: 1-bit (each) output: MMCM status ports
      LOCKED  => pll_locked_ds1_sig,       -- 1-bit output: LOCK output
      -- Clock Input: 1-bit (each) input: Clock input
        CLKIN1  => clk40_ibufgds1 ,
      -- Control Ports: 1-bit (each) input: MMCM control ports
      PWRDWN  => '0',       -- 1-bit input: Power-down input
      RST  => data_from_vme_REG_RW_CLOCK_MANAGER_RESET(0),             -- 1-bit input: Reset input
      -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
      CLKFBIN  => FEEDBACK_CLK_DS1   -- 1-bit input: Feedback clock input
      );

  pll_locked<=pll_locked_ds1_sig;

  
  vme_inreg_notri_async_inst: vme_inreg_notri_async
    generic map (
      ia_vme  =>  ADDR_REG_RW_CLOCK_MANAGER_RESET ,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(0),
      bus_drive      => bus_drive_local (0),
      data_from_vme  => data_from_vme_REG_RW_CLOCK_MANAGER_RESET,
      data_to_vme    => data_to_vme_REG_RW_CLOCK_MANAGER_RESET);

  data_to_vme_REG_RW_CLOCK_MANAGER_RESET<=data_from_vme_REG_RW_CLOCK_MANAGER_RESET;
  
  BUFG_40 : BUFG
    port map (
      O  => buf_clk40_sig,     -- Buffer output 
      I  => clk40      -- Buffer input 
      );

  
  BUFG_40_90o : BUFG
    port map (
      O  => buf_clk40_90o,     -- Buffer output 
      I  => clk40_90o      -- Buffer input 
      );

  BUFG_40_m90o : BUFG
    port map (
      O  => buf_clk40_m90o,     -- Buffer output 
      I  => clk40_m90o       -- Buffer input 
      );

  BUFG_40_m180o : BUFG
    port map (
      O  => buf_clk40_m180o,     -- Buffer output 
      I  => clk40_m180o       -- Buffer input 
      );

  
  BUFG_200 : BUFG
    port map (
      O  => buf_clk200,     -- Buffer output 
      I  => clk200      -- Buffer input 
      );

  BUFG_160 : BUFG
    port map (
      O  => buf_clk160,     -- Buffer output 
      I  => clk160      -- Buffer input 
      );
  
  BUFG_320 : BUFG
    port map (
      O  => buf_clk320,     -- Buffer output 
      I  => clk320      -- Buffer input 
      );

  buf_clk40 <= buf_clk40_sig;

  --the MMCM for the ds2 clock
  MMCM_BASE_inst_ds2 : MMCM_BASE
    generic map (
      BANDWIDTH  => "OPTIMIZED",  -- Jitter programming ("HIGH","LOW","OPTIMIZED")
      CLKFBOUT_MULT_F  => 32.0,    -- Multiply value for all CLKOUT (5.0-64.0).
                                  -- F_VCO = 32*40 MHz =1280 MHz
      CLKFBOUT_PHASE  => 0.0,     -- Phase offset in degrees of CLKFB (0.00-360.00).
      CLKIN1_PERIOD  => 24.95,      -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
      -- MHz) WTF: 25ns = 40MHz, 24.95=40.08 MHz - actual LHC BC
      CLKOUT0_DIVIDE_F => 32.0,   -- Divide amount for CLKOUT0 (1.000-128.000).
                                       -- 20 MHz
      -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
      CLKOUT0_DUTY_CYCLE  => 0.5,
      CLKOUT1_DUTY_CYCLE  => 0.5,
      CLKOUT2_DUTY_CYCLE  => 0.5,
      CLKOUT3_DUTY_CYCLE  => 0.5,
      CLKOUT4_DUTY_CYCLE  => 0.5,
      CLKOUT5_DUTY_CYCLE  => 0.5,
      CLKOUT6_DUTY_CYCLE  => 0.5,
      -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
      CLKOUT0_PHASE  => 0.0,
      CLKOUT1_PHASE  => 0.0,
      CLKOUT2_PHASE  => 0.0,-- -45.0,
      CLKOUT3_PHASE  => 0.0,
      CLKOUT4_PHASE  => 90.0,
      CLKOUT5_PHASE  => 0.0,
      CLKOUT6_PHASE  => 0.0,
      -- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
      CLKOUT1_DIVIDE  => 32,             --40 MHz
      CLKOUT2_DIVIDE  => 4,              --320 MHz
      CLKOUT3_DIVIDE  => 8,              --160 MHz
      CLKOUT4_DIVIDE  => 32,
      CLKOUT5_DIVIDE  => 1,
      CLKOUT6_DIVIDE  => 1,
      CLKOUT4_CASCADE  => FALSE,  -- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
      CLOCK_HOLD  => FALSE,       -- Hold VCO Frequency (TRUE/FALSE)
      DIVCLK_DIVIDE  => 1,        -- Master division value (1-80)
      REF_JITTER1  => 0.0,        -- Reference input jitter in UI (0.000-0.999).
      STARTUP_WAIT  => FALSE      -- Not supported. Must be set to FALSE.
      )
    port map (
      -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
      CLKOUT0  => clk40_ds2,     -- 1-bit output: CLKOUT0 output
      CLKOUT0B  => open,   -- 1-bit output: Inverted CLKOUT0 output
      CLKOUT1  => open,     -- 1-bit output: CLKOUT1 output
      CLKOUT1B  => open,   -- 1-bit output: Inverted CLKOUT1 output
      CLKOUT2  => open,     -- 1-bit output: CLKOUT2 output
      CLKOUT2B  => open,   -- 1-bit output: Inverted CLKOUT2 output
      CLKOUT3  => open,     -- 1-bit output: CLKOUT3 output
      CLKOUT3B  => open,   -- 1-bit output: Inverted CLKOUT3 output
      CLKOUT4  => open,     -- 1-bit output: CLKOUT4 output
      CLKOUT5  => open,     -- 1-bit output: CLKOUT5 output
      CLKOUT6  => open,     -- 1-bit output: CLKOUT6 output
      -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
      CLKFBOUT  => FEEDBACK_CLK_DS2 ,   -- 1-bit output: Feedback clock output
      CLKFBOUTB  => open, -- 1-bit output: Inverted CLKFBOUT output
      -- Status Port: 1-bit (each) output: MMCM status ports
      LOCKED  => pll_locked_ds2_sig,       -- 1-bit output: LOCK output
      -- Clock Input: 1-bit (each) input: Clock input
        CLKIN1  => clk40_ibufgds2 ,
      -- Control Ports: 1-bit (each) input: MMCM control ports
      PWRDWN  => '0',       -- 1-bit input: Power-down input
      RST  => data_from_vme_REG_RW_CLOCK_MANAGER_RESET(1),             -- 1-bit input: Reset input
      -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
      CLKFBIN  => FEEDBACK_CLK_DS2   -- 1-bit input: Feedback clock input
      );

  pll_locked_ds2<=pll_locked_ds2_sig;


  BUFG_40_ds2 : BUFG
    port map (
      O  => buf_clk40_ds2,     -- Buffer output 
      I  => clk40_ds2      -- Buffer input 
      );


  data_to_vme_REG_RO_CLOCK_MANAGER_STATUS(0)<=pll_locked_ds1_sig;
  data_to_vme_REG_RO_CLOCK_MANAGER_STATUS(1)<=pll_locked_ds2_sig;
  data_to_vme_REG_RO_CLOCK_MANAGER_STATUS(15 downto 2)<=(others=>'0');
  
  vme_outreg_REG_RO_CLOCK_MANAGER_STATUS: entity work.vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_CLOCK_MANAGER_STATUS ,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme     => data_vme_out_local (1),
      bus_drive    => bus_drive_local (1),
      data_to_vme  => data_to_vme_REG_RO_CLOCK_MANAGER_STATUS);
  
end Behavioral;