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CMX_clock_manager Entity Reference
Inheritance diagram for CMX_clock_manager:
vme_local_switch vme_inreg_notri_async vme_outreg_notri_async

Entities

Behavioral  architecture
 

Libraries

IEEE 
work 
UNISIM 

Use Clauses

IEEE.STD_LOGIC_1164.all 
work.CMXpackage.all 
UNISIM.VComponents.all 
work.CMX_VME_defs.all 

Ports

I_DS1   in std_logic
IB_DS1   in std_logic
buf_clk40   out std_logic
buf_clk40_90o   out std_logic
buf_clk40_m180o   out std_logic
buf_clk40_m90o   out std_logic
buf_clk320   out std_logic
buf_clk160   out std_logic
buf_clk200   out std_logic
pll_locked   out std_logic
I_DS2   in std_logic
IB_DS2   in std_logic
buf_clk40_ds2   out std_logic
pll_locked_ds2   out std_logic
ncs   in std_logic
rd_nwr   in std_logic
ds   in std_logic
addr_vme   in std_logic_vector ( 15 downto 0 )
data_vme_in   in std_logic_vector ( 15 downto 0 )
data_vme_out   out std_logic_vector ( 15 downto 0 )
bus_drive   out std_logic

Detailed Description

Definition at line 27 of file CMX_clock_manager.vhd.

Member Data Documentation

addr_vme in std_logic_vector ( 15 downto 0 )
Port

Definition at line 47 of file CMX_clock_manager.vhd.

buf_clk160 out std_logic
Port

Definition at line 37 of file CMX_clock_manager.vhd.

buf_clk200 out std_logic
Port

Definition at line 38 of file CMX_clock_manager.vhd.

buf_clk320 out std_logic
Port

Definition at line 36 of file CMX_clock_manager.vhd.

buf_clk40 out std_logic
Port

Definition at line 32 of file CMX_clock_manager.vhd.

buf_clk40_90o out std_logic
Port

Definition at line 33 of file CMX_clock_manager.vhd.

buf_clk40_ds2 out std_logic
Port

Definition at line 42 of file CMX_clock_manager.vhd.

buf_clk40_m180o out std_logic
Port

Definition at line 34 of file CMX_clock_manager.vhd.

buf_clk40_m90o out std_logic
Port

Definition at line 35 of file CMX_clock_manager.vhd.

bus_drive out std_logic
Port

Definition at line 50 of file CMX_clock_manager.vhd.

data_vme_in in std_logic_vector ( 15 downto 0 )
Port

Definition at line 48 of file CMX_clock_manager.vhd.

data_vme_out out std_logic_vector ( 15 downto 0 )
Port

Definition at line 49 of file CMX_clock_manager.vhd.

ds in std_logic
Port

Definition at line 46 of file CMX_clock_manager.vhd.

I_DS1 in std_logic
Port

Definition at line 30 of file CMX_clock_manager.vhd.

I_DS2 in std_logic
Port

Definition at line 40 of file CMX_clock_manager.vhd.

IB_DS1 in std_logic
Port

Definition at line 31 of file CMX_clock_manager.vhd.

IB_DS2 in std_logic
Port

Definition at line 41 of file CMX_clock_manager.vhd.

IEEE
Library

Definition at line 10 of file CMX_clock_manager.vhd.

IEEE.STD_LOGIC_1164.all
Package

Definition at line 11 of file CMX_clock_manager.vhd.

ncs in std_logic
Port

Definition at line 44 of file CMX_clock_manager.vhd.

pll_locked out std_logic
Port

Definition at line 39 of file CMX_clock_manager.vhd.

pll_locked_ds2 out std_logic
Port

Definition at line 43 of file CMX_clock_manager.vhd.

rd_nwr in std_logic
Port

Definition at line 45 of file CMX_clock_manager.vhd.

UNISIM
Library

Definition at line 23 of file CMX_clock_manager.vhd.

UNISIM.VComponents.all
Package

Definition at line 24 of file CMX_clock_manager.vhd.

work
Library

Definition at line 13 of file CMX_clock_manager.vhd.

work.CMX_VME_defs.all
Package

Definition at line 25 of file CMX_clock_manager.vhd.

work.CMXpackage.all
Package

Definition at line 14 of file CMX_clock_manager.vhd.

The documentation for this class was generated from the following file: