CMX
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Behavioral Architecture Reference

Components

vme_local_switch  <Entity vme_local_switch>
vme_inreg_notri_async  <Entity vme_inreg_notri_async>
vme_outreg_notri_async  <Entity vme_outreg_notri_async>

Signals

clk40_ibufgds1  std_logic
clk40_ibufgds2  std_logic
FEEDBACK_CLK_DS1  std_logic
FEEDBACK_CLK_DS2  std_logic
clk40  std_logic
clk40_90o  std_logic
clk40_m90o  std_logic
clk40_m180o  std_logic
clk320  std_logic
clk160  std_logic
clk200  std_logic
buf_clk40_sig  std_logic
clk40_ds2  std_logic
pll_locked_ds1_sig  std_logic
pll_locked_ds2_sig  std_logic
data_vme_out_local  arr_16 ( 1 downto 0 )
bus_drive_local  std_logic_vector ( 1 downto 0 )
data_from_vme_REG_RW_CLOCK_MANAGER_RESET  std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_CLOCK_MANAGER_RESET  std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RO_CLOCK_MANAGER_STATUS  std_logic_vector ( 15 downto 0 )

Instantiations

vme_local_switch_inst  vme_local_switch <Entity vme_local_switch>
ibufgds_inst_ds1  ibufgds
ibufgds_inst_ds2  ibufgds
mmcm_base_inst_ds1  mmcm_base
vme_inreg_notri_async_inst  vme_inreg_notri_async <Entity vme_inreg_notri_async>
bufg_40  bufg
bufg_40_90o  bufg
bufg_40_m90o  bufg
bufg_40_m180o  bufg
bufg_200  bufg
bufg_160  bufg
bufg_320  bufg
mmcm_base_inst_ds2  mmcm_base
bufg_40_ds2  bufg
vme_outreg_reg_ro_clock_manager_status  vme_outreg_notri_async <Entity vme_outreg_notri_async>

Detailed Description

Definition at line 54 of file CMX_clock_manager.vhd.

Member Data Documentation

buf_clk40_sig std_logic
Signal

Definition at line 64 of file CMX_clock_manager.vhd.

bufg_160 bufg
Instantiation

Definition at line 279 of file CMX_clock_manager.vhd.

bufg_200 bufg
Instantiation

Definition at line 273 of file CMX_clock_manager.vhd.

bufg_320 bufg
Instantiation

Definition at line 285 of file CMX_clock_manager.vhd.

bufg_40 bufg
Instantiation

Definition at line 247 of file CMX_clock_manager.vhd.

bufg_40_90o bufg
Instantiation

Definition at line 254 of file CMX_clock_manager.vhd.

bufg_40_ds2 bufg
Instantiation

Definition at line 363 of file CMX_clock_manager.vhd.

bufg_40_m180o bufg
Instantiation

Definition at line 266 of file CMX_clock_manager.vhd.

bufg_40_m90o bufg
Instantiation

Definition at line 260 of file CMX_clock_manager.vhd.

bus_drive_local std_logic_vector ( 1 downto 0 )
Signal

Definition at line 89 of file CMX_clock_manager.vhd.

clk160 std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

clk200 std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

clk320 std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

clk40 std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

clk40_90o std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

clk40_ds2 std_logic
Signal

Definition at line 67 of file CMX_clock_manager.vhd.

clk40_ibufgds1 std_logic
Signal

Definition at line 56 of file CMX_clock_manager.vhd.

clk40_ibufgds2 std_logic
Signal

Definition at line 56 of file CMX_clock_manager.vhd.

clk40_m180o std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

clk40_m90o std_logic
Signal

Definition at line 62 of file CMX_clock_manager.vhd.

data_from_vme_REG_RW_CLOCK_MANAGER_RESET std_logic_vector ( 15 downto 0 )
Signal

Definition at line 123 of file CMX_clock_manager.vhd.

data_to_vme_REG_RO_CLOCK_MANAGER_STATUS std_logic_vector ( 15 downto 0 )
Signal

Definition at line 126 of file CMX_clock_manager.vhd.

data_to_vme_REG_RW_CLOCK_MANAGER_RESET std_logic_vector ( 15 downto 0 )
Signal

Definition at line 124 of file CMX_clock_manager.vhd.

data_vme_out_local arr_16 ( 1 downto 0 )
Signal

Definition at line 88 of file CMX_clock_manager.vhd.

FEEDBACK_CLK_DS1 std_logic
Signal

Definition at line 59 of file CMX_clock_manager.vhd.

FEEDBACK_CLK_DS2 std_logic
Signal

Definition at line 60 of file CMX_clock_manager.vhd.

ibufgds_inst_ds1 ibufgds
Instantiation

Definition at line 140 of file CMX_clock_manager.vhd.

ibufgds_inst_ds2 ibufgds
Instantiation

Definition at line 150 of file CMX_clock_manager.vhd.

mmcm_base_inst_ds1 mmcm_base
Instantiation

Definition at line 161 of file CMX_clock_manager.vhd.

mmcm_base_inst_ds2 mmcm_base
Instantiation

Definition at line 294 of file CMX_clock_manager.vhd.

pll_locked_ds1_sig std_logic
Signal

Definition at line 70 of file CMX_clock_manager.vhd.

pll_locked_ds2_sig std_logic
Signal

Definition at line 70 of file CMX_clock_manager.vhd.

vme_inreg_notri_async
Component

Definition at line 92 of file CMX_clock_manager.vhd.

vme_inreg_notri_async_inst vme_inreg_notri_async
Instantiation

Definition at line 230 of file CMX_clock_manager.vhd.

vme_local_switch
Component

Definition at line 80 of file CMX_clock_manager.vhd.

vme_local_switch_inst vme_local_switch
Instantiation

Definition at line 132 of file CMX_clock_manager.vhd.

vme_outreg_notri_async
Component

Definition at line 109 of file CMX_clock_manager.vhd.

vme_outreg_reg_ro_clock_manager_status vme_outreg_notri_async
Instantiation

Definition at line 374 of file CMX_clock_manager.vhd.

The documentation for this class was generated from the following file: