Processes
PROCESS_3	( buf_clk40 , pll_locked )
PROCESS_4	( buf_clk40 )
PROCESS_5	( buf_clk40 , pll_locked )
PROCESS_6	( buf_clk40 )
spy_system_addr_proc	( buf_clk40 )
local_buf_master_inhibit_system	( buf_clk40 , pll_locked )
PROCESS_7	( buf_clk40 )
error_detect_process_system	( buf_clk40 )
PROCESS_8	( buf_clk40 )
PROCESS_9	( buf_clk40 )
PROCESS_10	( buf_clk40 , pll_locked )

Components
CMX_cable_clocked_80Mbps_output_module	<Entity CMX_cable_clocked_80Mbps_output_module>
blk_mem_A8x52_B8x52_1clock
Stretch_10	<Entity Stretch_10>
CMX_generic_spy_mem_control_FSM	<Entity CMX_generic_spy_mem_control_FSM>
vme_local_switch	<Entity vme_local_switch>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>
vme_outreg_notri	<Entity vme_outreg_notri>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>

Constants
mem_select_addr_width	integer := addr_port_width ( num_RTM_cables )

Signals
data_sdr	arr_RTM_sdr
data_sdr_r_SYSTEM	arr_RTM_sdr
counter_reset	std_logic
counter_reset_unstretched	std_logic
counter_reset_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
data_from_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_RTM_OUTPUT_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
all_null	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
mode_control_RTM_OUTPUT_SPY_SYSTEM	std_logic_vector ( 3 downto 0 )
ena_RTM_OUTPUT_SPY_SYSTEM	std_logic
wea_RTM_OUTPUT_SPY_SYSTEM	std_logic
addra_RTM_OUTPUT_SPY_SYSTEM	std_logic_vector ( 7 downto 0 )
mem_select_address_RTM_OUTPUT_SPY_SYSTEM	std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )
dina_RTM_OUTPUT_SPY_SYSTEM	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
douta_RTM_OUTPUT_SPY_SYSTEM	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
port_b_master_inhibit_RTM_OUTPUT_SPY_SYSTEM	std_logic
ena_rtm_output_spy_system_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
wea_rtm_output_spy_system_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
douta_rtm_output_spy_system_individual	arr_RTM_sdr
enb_rtm_output_spy_system_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_output_spy_system_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
addrb_rtm_output_spy_system_individual	arr_8 ( num_RTM_cables - 1 downto 0 )
dinb_rtm_output_spy_system_individual	arr_RTM_sdr
doutb_rtm_output_spy_system_individual	arr_RTM_sdr
addrb_RTM_OUTPUT_SPY_SYSTEM_counter	arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_output_spy_system_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_output_spy_system_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_output_spy_system_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_output_spy_system_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_output_spy_system_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_output_spy_system_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_output_spy_system	std_logic
web_rtm_output_spy_system	std_logic
spy_write_inhibit_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_rr_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_rr_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
data_vme_from_below	*arr_16 ( 4 + 9 num_RTM_cables + 2 downto 0 )**
bus_drive_from_below	*std_logic_vector ( 4 + 9 num_RTM_cables + 2 downto 0 )**
data_to_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_0	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR_1	arr_16 ( num_RTM_cables - 1 downto 0 )
bit_error_counter_system_next	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_counter_system	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_latch_system	arr_26 ( num_RTM_cables - 1 downto 0 )
bit_error_detect_system	arr_52 ( num_RTM_cables - 1 downto 0 )
sdr_data_after_mux	arr_RTM_sdr

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_inreg_reg_rw_rtm_output_counter_reset	vme_inreg_notri <Entity vme_inreg_notri>
stretch_10_counter_reset	Stretch_10 <Entity Stretch_10>
cmx_generic_spy_mem_control_fsm_inst_system	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
cmx_cable_clocked_80mbps_output_module_inst	CMX_cable_clocked_80Mbps_output_module <Entity CMX_cable_clocked_80Mbps_output_module>
blk_mem_a8x52_b8x52_1clock_system	blk_mem_a8x52_b8x52_1clock
vme_outreg_reg_ro_rtm_output_spy_system_mem_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_output_spy_system_mem_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_inreg_reg_rw_rtm_output_spy_system_mem_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>