Stretch_10.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Stretch_10 is
   port (
    unstretched_IN         : in  std_logic;
    stretched_OUT        : out std_logic; 
    clk               : in std_logic);
end Stretch_10;

architecture Behavioral of Stretch_10 is
  signal s0,s1,s2,s3,s4,s5,s6,s7,s8,s9 : std_logic;
  
  
begin

  process(clk)
  begin
    if rising_edge(clk) then
      s9<=s8;
      s8<=s7;
      s7<=s6;
      s6<=s5;
      s5<=s4;
      s4<=s3;
      s3<=s2;
      s2<=s1;
      s1<=s0;
      s0<=unstretched_IN;
      stretched_OUT<= ((s0 or s1) or (s2 or s3)) or (((s4 or s5) or (s6 or s7)) or (s8 or s9));
    end if;
  end process;

  
  
end Behavioral;