SFP_TXRX.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;


library work;
use work.CMXpackage.all;



entity SFP_Data_TXRX is
  generic
    (
      direction : std_logic;  -- on CMX some GTX connected to SFP are TX some are
      -- RX but never both; controls power state
      -- and clock source; 1=TX, 0=RX
      clock_source : std_logic --if '1' then the BUFR's will be
      --instantiated and output clocks provided
      --if '0' then the outside clock will be used 
      ); 
  port
    (
      MGTREFCLK          : in  std_logic;  --buffer has to be external
      gtx_reset          : in std_logic;
      local_pll_lock_out : out std_logic;
      GTX_TX_READY_OUT   : out std_logic;
      GTX_RX_READY_OUT   : out std_logic;
      PLLLKDET_diag      : out std_logic;
      local_gtx_reset_diag  : out std_logic;
      local_mmcm_reset_diag : out std_logic;
      GTXTEST_diag          : out std_logic;
      RXN_IN             : in  std_logic;
      RXP_IN             : in  std_logic;
      TXN_OUT            : out std_logic;
      TXP_OUT            : out std_logic;
      clk40_out          : out std_logic;
      clk120_out         : out std_logic;
      clk40_in           : in  std_logic;
      clk120_in          : in  std_logic;
      indata             : in  std_logic_vector(7 downto 0);
      odata              : out std_logic_vector(7 downto 0);
      TXPREEMPHASIS_IN   : in  std_logic_vector(3 downto 0);
      TXPOSTEMPHASIS_IN  : in  std_logic_vector(4 downto 0);
      TXDIFFCTRL_IN      : in  std_logic_vector(3 downto 0);
      RXEQMIX_IN         : in  std_logic_vector(2 downto 0);
      DFECLKDLYADJ       : in  std_logic_vector(5 downto 0);
      DFECLKDLYADJMON    : out std_logic_vector(5 downto 0);
      DFEDLYOVRD         : in  std_logic;
      DFEEYEDACMON       : out std_logic_vector(4 downto 0);
      DFESENSCAL         : out std_logic_vector(2 downto 0);
      DFETAP1            : in  std_logic_vector(4 downto 0);
      DFETAP1MONITOR     : out std_logic_vector(4 downto 0);
      DFETAP2            : in  std_logic_vector(4 downto 0);
      DFETAP2MONITOR     : out std_logic_vector(4 downto 0);
      DFETAP3            : in  std_logic_vector(3 downto 0);
      DFETAP3MONITOR     : out std_logic_vector(3 downto 0);
      DFETAP4            : in  std_logic_vector(3 downto 0);
      DFETAP4MONITOR     : out std_logic_vector(3 downto 0);
      DFETAPOVRD         : in  std_logic
      );

  



  
end SFP_Data_TXRX; 



architecture RTL of SFP_Data_TXRX is


  signal local_mmcm_reset           : std_logic;
  --signal local_mmcm_reset_undelayed : std_logic;
  signal local_pll_lock   : std_logic;
  signal local_gtx_reset: std_logic;
  --signal local_gtx_reset_undelayed: std_logic;

  component Delay is
    generic (
      del_length : integer);
    port (
      undelayed_in : in  std_logic;
      delayed_out  : out std_logic;
      clk          : in  std_logic);
  end component Delay;
  
  ------------------------ Loopback and Powerdown Ports ----------------------
  signal  RXPOWERDOWN_IN                          :    std_logic_vector(1 downto 0);
  signal  TXPOWERDOWN_IN                          :    std_logic_vector(1 downto 0);
  ------------------- Receive Ports - RX Data Path interface -----------------
  signal  RXDATA_OUT                              :   std_logic_vector(7 downto 0);
  signal  RXRECCLK_OUT                            :   std_logic;
  signal  RXRESET_IN                              :   std_logic;
  signal  RXUSRCLK2_IN                            :   std_logic;
  ------------------ Transmit Ports - TX Data Path interface -----------------
  signal  TXDATA_IN                               :   std_logic_vector(7 downto 0);
  signal  TXOUTCLK_OUT                            :   std_logic;
  signal  TXRESET_IN                              :   std_logic;
  signal  TXUSRCLK2_IN                            :   std_logic;
  
  --------------- Transmit Ports - TX Driver and OOB signalling --------------
  signal  TXRESETDONE_OUT                         :   std_logic;
  signal  RXRESETDONE_OUT                         :   std_logic;

  signal RXPLLLKDET : std_logic;
  signal TXPLLLKDET : std_logic;
  signal PLLLKDET : std_logic;
  signal PLLLKDET_r,PLLLKDET_rr : std_logic;

  signal GTXTEST : std_logic_vector(12 downto 0); --nominal: "1000000000000"
  signal GTXTEST_DOUBLE_RESET_BIT : std_logic;
  signal TXRXRESET : std_logic;

  signal double_reset_counter: unsigned(10 downto 0);
  signal double_reset_counter_next: unsigned(10 downto 0);
  
  -- RX Datapath signals
  signal rxdata_i                         :   std_logic_vector(31 downto 0);      
  
  
  -- TX Datapath signals
  signal txdata_i                         :   std_logic_vector(31 downto 0);
  
  signal clk40_sig : std_logic;
  signal clk120_sig : std_logic;
  
  -- ground and tied_to_vcc_i signals
  signal  tied_to_ground_i                :   std_logic;
  signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
  signal  tied_to_vcc_i                   :   std_logic;

  signal MGTREFCLK_IN : std_logic_vector(1 downto 0);

  signal rxrec_pll_locked : std_logic;
  signal txrec_pll_locked : std_logic;

  component sfp_clk_manager 
    port
      (-- Clock in ports
        CLK_IN1           : in     std_logic;
                                        -- Clock out ports
        CLK_OUT1          : out    std_logic;
        CLK_OUT2          : out    std_logic;
                                        -- Status and control signals
        RESET             : in     std_logic;
        LOCKED            : out    std_logic
        );
  end component;

  
begin


  --double reset procedure ug366 v2.6 p137

  GTXTEST_DOUBLE_RESET_BIT<='0';
  TXRXRESET<='0';
  
  --double_reset_counter_next<=double_reset_counter+1 when double_reset_counter/=to_unsigned(2047,11) else to_unsigned(2047,11);
  --process(MGTREFCLK)
  --begin
  --
  --  if rising_edge(MGTREFCLK) then
  --    if PLLLKDET_rr/='1' then
  --      double_reset_counter<=to_unsigned(0,11);
  --      GTXTEST_DOUBLE_RESET_BIT<='0';
  --      TXRXRESET<='0';
  --    else
  --      
  --      double_reset_counter<=double_reset_counter_next;
  --      
  --      if (double_reset_counter>to_unsigned(1050,11) and double_reset_counter<=to_unsigned(1350,11))
  --        or (double_reset_counter>to_unsigned(1650,11) and double_reset_counter<=to_unsigned(1950,11)) then
  --        GTXTEST_DOUBLE_RESET_BIT<='1';
  --      else
  --        GTXTEST_DOUBLE_RESET_BIT<='0';
  --      end if;
  --
  --      if double_reset_counter=to_unsigned(1954,11) then
  --        TXRXRESET<='1';
  --      else
  --        TXRXRESET<='0';
  --      end if;
  --    end if;
  --
  --    PLLLKDET_rr<=PLLLKDET_r;
  --    PLLLKDET_r<=PLLLKDET;
  --    
  --  end if;
  --end process;

  
      
  GTXTEST<="10000000000"& GTXTEST_DOUBLE_RESET_BIT &'0';
  GTXTEST_diag<=GTXTEST_DOUBLE_RESET_BIT;
  local_gtx_reset_diag<=local_gtx_reset;
  local_gtx_reset<=gtx_reset;
  local_mmcm_reset_diag<=local_mmcm_reset;
  PLLLKDET_diag<=PLLLKDET;
  
  
  tied_to_ground_i                             <= '0';
  tied_to_ground_vec_i                         <= x"0000000000000000";
  tied_to_vcc_i                                <= '1';

  MGTREFCLK_IN<= (tied_to_ground_i & MGTREFCLK);
  
  RXDATA_OUT    <=   rxdata_i(7 downto 0);
  odata<=RXDATA_OUT;
  TXDATA_IN<=indata;
  txdata_i <=   (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);

  TXPOWERDOWN_IN<=((not direction) & (not direction));
  RXPOWERDOWN_IN<=(direction & direction);

  local_mmcm_reset<=not PLLLKDET;
  
  gen_connect_mmcm_reset_TX: if direction='1' generate
    PLLLKDET<=TXPLLLKDET;
    TXRESET_IN<=TXRXRESET;
    RXRESET_IN<='0';
  end generate gen_connect_mmcm_reset_TX;
  gen_connect_mmcm_reset_RX: if direction='0' generate
    PLLLKDET<=RXPLLLKDET;
    RXRESET_IN<=TXRXRESET;
    TXRESET_IN<='0';
  end generate gen_connect_mmcm_reset_RX;
  
  GTX_TX_READY_OUT<=TXRESETDONE_OUT;
  GTX_RX_READY_OUT<=RXRESETDONE_OUT;

  gen_clock_source: if clock_source='1' generate
    gen_BUFR_RX: if direction='0' generate
      

--  rxrecclk_bufr_i_div1 : BUFR
--        generic map
--        (
--          BUFR_DIVIDE                     =>      "1",
--          SIM_DEVICE                      =>      "VIRTEX6"
--          )
--        port map
--        (
--          CE                              =>      '1',
--          CLR                             =>      '0',
--          I                               =>      RXRECCLK_OUT,
--          O                               =>      clk120_sig
--          );


--      rxrecclk_bufr_i_div3 : BUFR
--        generic map
--        (
--          BUFR_DIVIDE                     =>      "3",
--          SIM_DEVICE                      =>      "VIRTEX6"
--          )
--        port map
--        (
--          CE                              =>      '1',
--          CLR                             =>      '0',
--          I                               =>      RXRECCLK_OUT,
--          O                               =>      clk40_sig
--          );


      rxrecclk_i : sfp_clk_manager 
        port map
        (-- Clock in ports
          CLK_IN1      => RXRECCLK_OUT,   
          -- Clock out ports
          CLK_OUT1     => clk120_sig,   
          CLK_OUT2     => clk40_sig,    
          -- Status and control signals
          RESET        => local_mmcm_reset ,     
          LOCKED       => local_pll_lock     
          );

      

      clk120_out<=clk120_sig;
      RXUSRCLK2_IN<=clk120_sig;

      clk40_out<=clk40_sig;



    end generate gen_BUFR_RX;

    
    gen_BUFR_TX: if direction='1' generate

--  
--      txoutclk_bufr_i_div1 : BUFR
--        generic map
--        (
--          BUFR_DIVIDE                     =>      "1",
--          SIM_DEVICE                      =>      "VIRTEX6"
--          )
--        port map
--        (
--          CE                              =>      '1',
--          CLR                             =>      '0',
--          I                               =>      TXOUTCLK_OUT,
--          O                               =>      clk120_sig
--          );
--
--      txoutclk_bufr_i_div3 : BUFR
--        generic map
--        (
--          BUFR_DIVIDE                     =>      "3",
--          SIM_DEVICE                      =>      "VIRTEX6"
--          )
--        port map
--        (
--          CE                              =>      '1',
--          CLR                             =>      '0',
--          I                               =>      TXOUTCLK_OUT,
--          O                               =>      clk40_sig
--          );


      txrecclk_i : sfp_clk_manager 
        port map
        (-- Clock in ports
          CLK_IN1      => TXOUTCLK_OUT,   
          -- Clock out ports
          CLK_OUT1     => clk120_sig,   
          CLK_OUT2     => clk40_sig,    
          -- Status and control signals
          RESET        => local_mmcm_reset ,     
          LOCKED       => local_pll_lock      
          );

      clk120_out<=clk120_sig;
      TXUSRCLK2_IN<=clk120_sig;

      clk40_out<=clk40_sig;
    end generate gen_BUFR_TX;

    --process(MGTREFCLK, sys_pll_lock)
    --begin
    --  if sys_pll_lock/='1' then
    --    local_gtx_reset_undelayed<='1';
    --  elsif rising_edge(MGTREFCLK) then
    --    local_gtx_reset_undelayed<='0';
    --  end if;
    --end process;
    
    
  end generate gen_clock_source;

  local_pll_lock_out<=local_pll_lock;
  

  --Delay_local_gtx_reset: entity work.Delay
  --  generic map (
  --    del_length => 200)
  --  port map (
  --    undelayed_in => local_gtx_reset_undelayed,
  --    delayed_out  => local_gtx_reset,
  --    clk          => MGTREFCLK);
  

  gen_clock_sink: if clock_source='0' generate

    local_pll_lock<='0';

    --process(MGTREFCLK, other_sfp_pll_lock)
    --begin
    --  if other_sfp_pll_lock/='1' then
    --    local_gtx_reset_undelayed<='1';
    --  elsif rising_edge(MGTREFCLK) then
    --    local_gtx_reset_undelayed<='0';
    --  end if;
    --end process;
    
    gen_sink_RX: if direction='0' generate
      clk120_sig<=clk120_in;
      RXUSRCLK2_IN<=clk120_sig;

      --WTF 2050216 clk40_out<=clk40_sig;
      clk40_sig<=clk40_in;
    end generate gen_sink_RX;

    
    gen_sink_TX: if direction='1' generate
      clk120_sig<=clk120_in;
      TXUSRCLK2_IN<=clk120_sig;

      clk40_sig<=clk40_in;
    end generate gen_sink_TX;

  end generate gen_clock_sink;
  
  
  
  gtxe1_i :GTXE1
    generic map
    (

      --_______________________ Simulation-Only Attributes ___________________

      SIM_RECEIVER_DETECT_PASS    =>      (TRUE),
      
      SIM_GTXRESET_SPEEDUP        =>      (0),

      SIM_TX_ELEC_IDLE_LEVEL      =>      ("X"),

      SIM_VERSION                 =>      ("2.0"),
      SIM_TXREFCLK_SOURCE         =>      ("000"),
      SIM_RXREFCLK_SOURCE         =>      ("000"),
      

      ----------------------------TX PLL----------------------------
      TX_CLK_SOURCE                            =>     ("TXPLL"),
      TX_OVERSAMPLE_MODE                       =>     (FALSE),
      TXPLL_COM_CFG                            =>     (x"21680a"),
      TXPLL_CP_CFG                             =>     (x"0D"),
      TXPLL_DIVSEL_FB                          =>     (4),
      TXPLL_DIVSEL_OUT                         =>     (4),
      TXPLL_DIVSEL_REF                         =>     (1),
      TXPLL_DIVSEL45_FB                        =>     (4),
      TXPLL_LKDET_CFG                          =>     ("111"),
      TX_CLK25_DIVIDER                         =>     (5),
      TXPLL_SATA                               =>     ("00"),
      TX_TDCC_CFG                              =>     ("00"),
      PMA_CAS_CLK_EN                           =>     (FALSE),
      POWER_SAVE                               =>     ("0000110000"),

      -------------------------TX Interface-------------------------
      GEN_TXUSRCLK                             =>     (TRUE),
      TX_DATA_WIDTH                            =>     (8),
      TX_USRCLK_CFG                            =>     (x"00"),
      TXOUTCLK_CTRL                            =>     ("TXOUTCLKPMA_DIV1"),
      TXOUTCLK_DLY                             =>     ("0000000000"),

      --------------TX Buffering and Phase Alignment----------------
      TX_PMADATA_OPT                           =>     ('0'),
      PMA_TX_CFG                               =>     (x"80082"),
      TX_BUFFER_USE                            =>     (TRUE),
      TX_BYTECLK_CFG                           =>     (x"00"),
      TX_EN_RATE_RESET_BUF                     =>     (TRUE),
      TX_XCLK_SEL                              =>     ("TXOUT"),
      TX_DLYALIGN_CTRINC                       =>     ("0100"),
      TX_DLYALIGN_LPFINC                       =>     ("0110"),
      TX_DLYALIGN_MONSEL                       =>     ("000"),
      TX_DLYALIGN_OVRDSETTING                  =>     ("10000000"),

      -------------------------TX Gearbox---------------------------
      GEARBOX_ENDEC                            =>     ("000"),
      TXGEARBOX_USE                            =>     (FALSE),

      ----------------TX Driver and OOB Signalling------------------
      TX_DRIVE_MODE                            =>     ("DIRECT"),
      TX_IDLE_ASSERT_DELAY                     =>     ("101"),
      TX_IDLE_DEASSERT_DELAY                   =>     ("011"),
      TXDRIVE_LOOPBACK_HIZ                     =>     (FALSE),
      TXDRIVE_LOOPBACK_PD                      =>     (FALSE),

      --------------TX Pipe Control for PCI Express/SATA------------
      COM_BURST_VAL                            =>     ("1111"),

      ------------------TX Attributes for PCI Express---------------
      TX_DEEMPH_0                              =>     ("11010"),
      TX_DEEMPH_1                              =>     ("10000"),
      TX_MARGIN_FULL_0                         =>     ("1001110"),
      TX_MARGIN_FULL_1                         =>     ("1001001"),
      TX_MARGIN_FULL_2                         =>     ("1000101"),
      TX_MARGIN_FULL_3                         =>     ("1000010"),
      TX_MARGIN_FULL_4                         =>     ("1000000"),
      TX_MARGIN_LOW_0                          =>     ("1000110"),
      TX_MARGIN_LOW_1                          =>     ("1000100"),
      TX_MARGIN_LOW_2                          =>     ("1000010"),
      TX_MARGIN_LOW_3                          =>     ("1000000"),
      TX_MARGIN_LOW_4                          =>     ("1000000"),

      ----------------------------RX PLL----------------------------
      RX_OVERSAMPLE_MODE                       =>     (FALSE),
      RXPLL_COM_CFG                            =>     (x"21680a"),
      RXPLL_CP_CFG                             =>     (x"0D"),
      RXPLL_DIVSEL_FB                          =>     (4),
      RXPLL_DIVSEL_OUT                         =>     (4),
      RXPLL_DIVSEL_REF                         =>     (1),
      RXPLL_DIVSEL45_FB                        =>     (4),
      RXPLL_LKDET_CFG                          =>     ("111"),
      RX_CLK25_DIVIDER                         =>     (5),

      -------------------------RX Interface-------------------------
      GEN_RXUSRCLK                             =>     (TRUE),
      RX_DATA_WIDTH                            =>     (8),
      RXRECCLK_CTRL                            =>     ("RXRECCLKPMA_DIV1"),
      RXRECCLK_DLY                             =>     ("0000000000"),
      RXUSRCLK_DLY                             =>     (x"0000"),

      ----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
      AC_CAP_DIS                               =>     (FALSE),
      CDR_PH_ADJ_TIME                          =>     ("10100"),
      OOBDETECT_THRESHOLD                      =>     ("011"),
      PMA_CDR_SCAN                             =>     (x"640404C"),
      PMA_RX_CFG                               =>     (x"05ce008"),
      RCV_TERM_GND                             =>     (FALSE),
      RCV_TERM_VTTRX                           =>     (TRUE),
      RX_EN_IDLE_HOLD_CDR                      =>     (FALSE),
      RX_EN_IDLE_RESET_FR                      =>     (FALSE),
      RX_EN_IDLE_RESET_PH                      =>     (FALSE),
      TX_DETECT_RX_CFG                         =>     (x"1832"),
      TERMINATION_CTRL                         =>     ("00000"),
      TERMINATION_OVRD                         =>     (FALSE),
      CM_TRIM                                  =>     ("01"),
      PMA_RXSYNC_CFG                           =>     (x"00"),
      PMA_CFG                                  =>     (x"0040000040000000003"),
      BGTEST_CFG                               =>     ("00"),
      BIAS_CFG                                 =>     (x"00000"),

      --------------RX Decision Feedback Equalizer(DFE)-------------
      DFE_CAL_TIME                             =>     ("01100"),
      DFE_CFG                                  =>     ("00011011"),
      RX_EN_IDLE_HOLD_DFE                      =>     (TRUE),
      RX_EYE_OFFSET                            =>     (x"4C"),
      RX_EYE_SCANMODE                          =>     ("00"),

      -------------------------PRBS Detection-----------------------
      RXPRBSERR_LOOPBACK                       =>     ('0'),

      ------------------Comma Detection and Alignment---------------
      ALIGN_COMMA_WORD                         =>     (1),
      COMMA_10B_ENABLE                         =>     ("1111111111"),
      COMMA_DOUBLE                             =>     (FALSE),
      DEC_MCOMMA_DETECT                        =>     (FALSE),
      DEC_PCOMMA_DETECT                        =>     (FALSE),
      DEC_VALID_COMMA_ONLY                     =>     (FALSE),
      MCOMMA_10B_VALUE                         =>     ("1010000011"),
      MCOMMA_DETECT                            =>     (TRUE),
      PCOMMA_10B_VALUE                         =>     ("0101111100"),
      PCOMMA_DETECT                            =>     (TRUE),
      RX_DECODE_SEQ_MATCH                      =>     (FALSE),
      RX_SLIDE_AUTO_WAIT                       =>     (5),
      RX_SLIDE_MODE                            =>     ("OFF"),
      SHOW_REALIGN_COMMA                       =>     (TRUE),

      -----------------RX Loss-of-sync State Machine----------------
      RX_LOS_INVALID_INCR                      =>     (8),
      RX_LOS_THRESHOLD                         =>     (128),
      RX_LOSS_OF_SYNC_FSM                      =>     (FALSE),

      -------------------------RX Gearbox---------------------------
      RXGEARBOX_USE                            =>     (FALSE),

      -------------RX Elastic Buffer and Phase alignment------------
      RX_BUFFER_USE                            =>     (TRUE),
      RX_EN_IDLE_RESET_BUF                     =>     (FALSE),
      RX_EN_MODE_RESET_BUF                     =>     (TRUE),
      RX_EN_RATE_RESET_BUF                     =>     (TRUE),
      RX_EN_REALIGN_RESET_BUF                  =>     (FALSE),
      RX_EN_REALIGN_RESET_BUF2                 =>     (FALSE),
      RX_FIFO_ADDR_MODE                        =>     ("FAST"),
      RX_IDLE_HI_CNT                           =>     ("1000"),
      RX_IDLE_LO_CNT                           =>     ("0000"),
      RX_XCLK_SEL                              =>     ("RXREC"),
      RX_DLYALIGN_CTRINC                       =>     ("1110"),
      RX_DLYALIGN_EDGESET                      =>     ("00010"),
      RX_DLYALIGN_LPFINC                       =>     ("1110"),
      RX_DLYALIGN_MONSEL                       =>     ("000"),
      RX_DLYALIGN_OVRDSETTING                  =>     ("10000000"),

      ------------------------Clock Correction----------------------
      CLK_COR_ADJ_LEN                          =>     (1),
      CLK_COR_DET_LEN                          =>     (1),
      CLK_COR_INSERT_IDLE_FLAG                 =>     (FALSE),
      CLK_COR_KEEP_IDLE                        =>     (FALSE),
      CLK_COR_MAX_LAT                          =>     (16),
      CLK_COR_MIN_LAT                          =>     (14),
      CLK_COR_PRECEDENCE                       =>     (TRUE),
      CLK_COR_REPEAT_WAIT                      =>     (0),
      CLK_COR_SEQ_1_1                          =>     ("0000000000"),
      CLK_COR_SEQ_1_2                          =>     ("0000000000"),
      CLK_COR_SEQ_1_3                          =>     ("0000000000"),
      CLK_COR_SEQ_1_4                          =>     ("0000000000"),
      CLK_COR_SEQ_1_ENABLE                     =>     ("1111"),
      CLK_COR_SEQ_2_1                          =>     ("0000000000"),
      CLK_COR_SEQ_2_2                          =>     ("0000000000"),
      CLK_COR_SEQ_2_3                          =>     ("0000000000"),
      CLK_COR_SEQ_2_4                          =>     ("0000000000"),
      CLK_COR_SEQ_2_ENABLE                     =>     ("1111"),
      CLK_COR_SEQ_2_USE                        =>     (FALSE),
      CLK_CORRECT_USE                          =>     (FALSE),

      ------------------------Channel Bonding----------------------
      CHAN_BOND_1_MAX_SKEW                     =>     (1),
      CHAN_BOND_2_MAX_SKEW                     =>     (1),
      CHAN_BOND_KEEP_ALIGN                     =>     (FALSE),
      CHAN_BOND_SEQ_1_1                        =>     ("0000000000"),
      CHAN_BOND_SEQ_1_2                        =>     ("0000000000"),
      CHAN_BOND_SEQ_1_3                        =>     ("0000000000"),
      CHAN_BOND_SEQ_1_4                        =>     ("0000000000"),
      CHAN_BOND_SEQ_1_ENABLE                   =>     ("1111"),
      CHAN_BOND_SEQ_2_1                        =>     ("0000000000"),
      CHAN_BOND_SEQ_2_2                        =>     ("0000000000"),
      CHAN_BOND_SEQ_2_3                        =>     ("0000000000"),
      CHAN_BOND_SEQ_2_4                        =>     ("0000000000"),
      CHAN_BOND_SEQ_2_CFG                      =>     ("00000"),
      CHAN_BOND_SEQ_2_ENABLE                   =>     ("1111"),
      CHAN_BOND_SEQ_2_USE                      =>     (FALSE),
      CHAN_BOND_SEQ_LEN                        =>     (1),
      PCI_EXPRESS_MODE                         =>     (FALSE),

      -------------RX Attributes for PCI Express/SATA/SAS----------
      SAS_MAX_COMSAS                           =>     (52),
      SAS_MIN_COMSAS                           =>     (40),
      SATA_BURST_VAL                           =>     ("100"),
      SATA_IDLE_VAL                            =>     ("100"),
      SATA_MAX_BURST                           =>     (9),
      SATA_MAX_INIT                            =>     (26),
      SATA_MAX_WAKE                            =>     (9),
      SATA_MIN_BURST                           =>     (5),
      SATA_MIN_INIT                            =>     (14),
      SATA_MIN_WAKE                            =>     (5),
      TRANS_TIME_FROM_P2                       =>     (x"03c"),
      TRANS_TIME_NON_P2                        =>     (x"19"),
      TRANS_TIME_RATE                          =>     (x"ff"),
      TRANS_TIME_TO_P2                         =>     (x"064")


      )
    port map
    (
      ------------------------ Loopback and Powerdown Ports ----------------------
      LOOPBACK                         =>      tied_to_ground_vec_i (2 downto 0),
      RXPOWERDOWN                      =>      RXPOWERDOWN_IN,
      TXPOWERDOWN                      =>      TXPOWERDOWN_IN,
      -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
      RXDATAVALID                      =>      open,
      RXGEARBOXSLIP                    =>      tied_to_ground_i,
      RXHEADER                         =>      open,
      RXHEADERVALID                    =>      open,
      RXSTARTOFSEQ                     =>      open,
      ----------------------- Receive Ports - 8b10b Decoder ----------------------
      RXCHARISCOMMA                    =>      open,
      RXCHARISK                        =>      open,
      RXDEC8B10BUSE                    =>      tied_to_ground_i,
      RXDISPERR                        =>      open,
      RXNOTINTABLE                     =>      open,
      RXRUNDISP                        =>      open,
      USRCODEERR                       =>      tied_to_ground_i,
      ------------------- Receive Ports - Channel Bonding Ports ------------------
      RXCHANBONDSEQ                    =>      open,
      RXCHBONDI                        =>      tied_to_ground_vec_i (3 downto 0),
      RXCHBONDLEVEL                    =>      tied_to_ground_vec_i (2 downto 0),
      RXCHBONDMASTER                   =>      tied_to_ground_i,
      RXCHBONDO                        =>      open,
      RXCHBONDSLAVE                    =>      tied_to_ground_i,
      RXENCHANSYNC                     =>      tied_to_ground_i,
      ------------------- Receive Ports - Clock Correction Ports -----------------
      RXCLKCORCNT                      =>      open,
      --------------- Receive Ports - Comma Detection and Alignment --------------
      RXBYTEISALIGNED                  =>      open,
      RXBYTEREALIGN                    =>      open,
      RXCOMMADET                       =>      open,
      RXCOMMADETUSE                    =>      tied_to_ground_i,
      RXENMCOMMAALIGN                  =>      tied_to_ground_i,
      RXENPCOMMAALIGN                  =>      tied_to_ground_i,
      RXSLIDE                          =>      tied_to_ground_i,
      ----------------------- Receive Ports - PRBS Detection ---------------------
      PRBSCNTRESET                     =>      tied_to_ground_i,
      RXENPRBSTST                      =>      tied_to_ground_vec_i (2 downto 0),
      RXPRBSERR                        =>      open,
      ------------------- Receive Ports - RX Data Path interface -----------------
      RXDATA                           =>      rxdata_i,
      RXRECCLK                         =>      RXRECCLK_OUT ,
      RXRECCLKPCS                      =>      open,
      RXRESET                          =>      tied_to_ground_i,
      RXUSRCLK                         =>      tied_to_ground_i,
      RXUSRCLK2                        =>      RXUSRCLK2_IN ,
      ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
      DFECLKDLYADJ                     =>      DFECLKDLYADJ ,    
      DFECLKDLYADJMON                  =>      DFECLKDLYADJMON, 
      DFEDLYOVRD                       =>      DFEDLYOVRD,      
      DFEEYEDACMON                     =>      DFEEYEDACMON ,    
      DFESENSCAL                       =>      DFESENSCAL,      
      DFETAP1                          =>      DFETAP1,         
      DFETAP1MONITOR                   =>      DFETAP1MONITOR,  
      DFETAP2                          =>      DFETAP2,         
      DFETAP2MONITOR                   =>      DFETAP2MONITOR,  
      DFETAP3                          =>      DFETAP3,         
      DFETAP3MONITOR                   =>      DFETAP3MONITOR,  
      DFETAP4                          =>      DFETAP4,         
      DFETAP4MONITOR                   =>      DFETAP4MONITOR,  
      DFETAPOVRD                       =>      DFETAPOVRD,      
      ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
      GATERXELECIDLE                   =>      tied_to_vcc_i,
      IGNORESIGDET                     =>      tied_to_vcc_i,
      RXCDRRESET                       =>      tied_to_ground_i,
      RXELECIDLE                       =>      open,
      RXEQMIX(9 downto 3)              =>      tied_to_ground_vec_i (6 downto 0),
      RXEQMIX(2 downto 0)              =>      RXEQMIX_IN,
      RXN                              =>      RXN_IN,
      RXP                              =>      RXP_IN,
      -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
      RXBUFRESET                       =>      tied_to_ground_i,
      RXBUFSTATUS                      =>      open,
      RXCHANISALIGNED                  =>      open,
      RXCHANREALIGN                    =>      open,
      RXDLYALIGNDISABLE                =>      tied_to_ground_i,
      RXDLYALIGNMONENB                 =>      tied_to_ground_i,
      RXDLYALIGNMONITOR                =>      open,
      RXDLYALIGNOVERRIDE               =>      tied_to_vcc_i,
      RXDLYALIGNRESET                  =>      tied_to_ground_i,
      RXDLYALIGNSWPPRECURB             =>      tied_to_vcc_i,
      RXDLYALIGNUPDSW                  =>      tied_to_ground_i,
      RXENPMAPHASEALIGN                =>      tied_to_ground_i,
      RXPMASETPHASE                    =>      tied_to_ground_i,
      RXSTATUS                         =>      open,
      --------------- Receive Ports - RX Loss-of-sync State Machine --------------
      RXLOSSOFSYNC                     =>      open,
      ---------------------- Receive Ports - RX Oversampling ---------------------
      RXENSAMPLEALIGN                  =>      tied_to_ground_i,
      RXOVERSAMPLEERR                  =>      open,
      ------------------------ Receive Ports - RX PLL Ports ----------------------
      GREFCLKRX                        =>      tied_to_ground_i,
      GTXRXRESET                       =>      local_gtx_reset,
      MGTREFCLKRX                      =>      MGTREFCLK_IN ,
      NORTHREFCLKRX                    =>      tied_to_ground_vec_i (1 downto 0),
      PERFCLKRX                        =>      tied_to_ground_i,
      PLLRXRESET                       =>      tied_to_ground_i,
      RXPLLLKDET                       =>      RXPLLLKDET,
      RXPLLLKDETEN                     =>      tied_to_vcc_i,
      RXPLLPOWERDOWN                   =>      tied_to_ground_i,
      RXPLLREFSELDY                    =>      tied_to_ground_vec_i (2 downto 0),
      RXRATE                           =>      tied_to_ground_vec_i (1 downto 0),
      RXRATEDONE                       =>      open,
      RXRESETDONE                      =>      RXRESETDONE_OUT,
      SOUTHREFCLKRX                    =>      tied_to_ground_vec_i (1 downto 0),
      -------------- Receive Ports - RX Pipe Control for PCI Express -------------
      PHYSTATUS                        =>      open,
      RXVALID                          =>      open,
      ----------------- Receive Ports - RX Polarity Control Ports ----------------
      RXPOLARITY                       =>      tied_to_ground_i,
      --------------------- Receive Ports - RX Ports for SATA --------------------
      COMINITDET                       =>      open,
      COMSASDET                        =>      open,
      COMWAKEDET                       =>      open,
      ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
      DADDR                            =>      tied_to_ground_vec_i (7 downto 0),
      DCLK                             =>      tied_to_ground_i,
      DEN                              =>      tied_to_ground_i,
      DI                               =>      tied_to_ground_vec_i (15 downto 0),
      DRDY                             =>      open,
      DRPDO                            =>      open,
      DWE                              =>      tied_to_ground_i,
      -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
      TXGEARBOXREADY                   =>      open,
      TXHEADER                         =>      tied_to_ground_vec_i (2 downto 0),
      TXSEQUENCE                       =>      tied_to_ground_vec_i (6 downto 0),
      TXSTARTSEQ                       =>      tied_to_ground_i,
      ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
      TXBYPASS8B10B                    =>      tied_to_ground_vec_i (3 downto 0),
      TXCHARDISPMODE                   =>      tied_to_ground_vec_i (3 downto 0),
      TXCHARDISPVAL                    =>      tied_to_ground_vec_i (3 downto 0),
      TXCHARISK                        =>      tied_to_ground_vec_i (3 downto 0),
      TXENC8B10BUSE                    =>      tied_to_ground_i,
      TXKERR                           =>      open,
      TXRUNDISP                        =>      open,
      ------------------------- Transmit Ports - GTX Ports -----------------------
      GTXTEST                          =>      GTXTEST,
      MGTREFCLKFAB                     =>      open,
      TSTCLK0                          =>      tied_to_ground_i,
      TSTCLK1                          =>      tied_to_ground_i,
      TSTIN                            =>      "11111111111111111111" ,
      TSTOUT                           =>      open,
      ------------------ Transmit Ports - TX Data Path interface -----------------
      TXDATA                           =>      txdata_i,
      TXOUTCLK                         =>      TXOUTCLK_OUT ,
      TXOUTCLKPCS                      =>      open,
      TXRESET                          =>      tied_to_ground_i,
      TXUSRCLK                         =>      tied_to_ground_i,
      TXUSRCLK2                        =>      TXUSRCLK2_IN ,
      ---------------- Transmit Ports - TX Driver and OOB signaling --------------
      TXBUFDIFFCTRL                    =>      "100",
      TXDIFFCTRL                       =>      TXDIFFCTRL_IN,
      TXINHIBIT                        =>      tied_to_ground_i,
      TXN                              =>      TXN_OUT,
      TXP                              =>      TXP_OUT,
      TXPOSTEMPHASIS                   =>      TXPOSTEMPHASIS_IN,
      --------------- Transmit Ports - TX Driver and OOB signalling --------------
      TXPREEMPHASIS                    =>      TXPREEMPHASIS_IN,
      ----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
      TXBUFSTATUS                      =>      open,
      -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
      TXDLYALIGNDISABLE                =>      tied_to_vcc_i,
      TXDLYALIGNMONENB                 =>      tied_to_ground_i,
      TXDLYALIGNMONITOR                =>      open,
      TXDLYALIGNOVERRIDE               =>      tied_to_ground_i,
      TXDLYALIGNRESET                  =>      tied_to_ground_i,
      TXDLYALIGNUPDSW                  =>      tied_to_vcc_i,
      TXENPMAPHASEALIGN                =>      tied_to_ground_i,
      TXPMASETPHASE                    =>      tied_to_ground_i,
      ----------------------- Transmit Ports - TX PLL Ports ----------------------
      GREFCLKTX                        =>      tied_to_ground_i,
      GTXTXRESET                       =>      local_gtx_reset,
      MGTREFCLKTX                      =>      MGTREFCLK_IN ,
      NORTHREFCLKTX                    =>      tied_to_ground_vec_i (1 downto 0),
      PERFCLKTX                        =>      tied_to_ground_i,
      PLLTXRESET                       =>      tied_to_ground_i,
      SOUTHREFCLKTX                    =>      tied_to_ground_vec_i (1 downto 0),
      TXPLLLKDET                       =>      TXPLLLKDET,
      TXPLLLKDETEN                     =>      tied_to_vcc_i,
      TXPLLPOWERDOWN                   =>      tied_to_ground_i,
      TXPLLREFSELDY                    =>      tied_to_ground_vec_i (2 downto 0),
      TXRATE                           =>      tied_to_ground_vec_i (1 downto 0),
      TXRATEDONE                       =>      open,
      TXRESETDONE                      =>      TXRESETDONE_OUT,
      --------------------- Transmit Ports - TX PRBS Generator -------------------
      TXENPRBSTST                      =>      tied_to_ground_vec_i (2 downto 0),
      TXPRBSFORCEERR                   =>      tied_to_ground_i,
      -------------------- Transmit Ports - TX Polarity Control ------------------
      TXPOLARITY                       =>      tied_to_ground_i,
      ----------------- Transmit Ports - TX Ports for PCI Express ----------------
      TXDEEMPH                         =>      tied_to_ground_i,
      TXDETECTRX                       =>      tied_to_ground_i,
      TXELECIDLE                       =>      tied_to_ground_i,
      TXMARGIN                         =>      tied_to_ground_vec_i (2 downto 0),
      TXPDOWNASYNCH                    =>      tied_to_ground_i,
      TXSWING                          =>      tied_to_ground_i,
      --------------------- Transmit Ports - TX Ports for SATA -------------------
      COMFINISH                        =>      open,
      TXCOMINIT                        =>      tied_to_ground_i,
      TXCOMSAS                         =>      tied_to_ground_i,
      TXCOMWAKE                        =>      tied_to_ground_i

      );

  
  
end RTL;