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CMX_CTP_output_module Entity Reference
Inheritance diagram for CMX_CTP_output_module:
vme_local_switch vme_inreg_notri Stretch_10 CMX_generic_spy_mem_control_FSM vme_inreg_notri_async vme_outreg_notri_async vme_local_switch vme_inreg_notri vme_outreg_notri_async

Entities

Behavioral  architecture
 

Libraries

IEEE 
UNISIM 
work 

Use Clauses

IEEE.STD_LOGIC_1164.all 
IEEE.NUMERIC_STD.all 
UNISIM.VComponents.all 
work.CMXpackage.all 
work.CMX_VME_defs.all 

Ports

data   in std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )
sdr_data_out   out arr_CTP
buf_clk40   in std_logic
buf_clk40_center   in std_logic
buf_clk200   in std_logic
pll_locked   in std_logic
start_playback   in std_logic
spy_write_inhibit   in std_logic
ncs   in std_logic
rd_nwr   in std_logic
ds   in std_logic
addr_vme   in std_logic_vector ( 15 downto 0 )
data_vme_in   in std_logic_vector ( 15 downto 0 )
data_vme_out   out std_logic_vector ( 15 downto 0 )
bus_drive   out std_logic

Detailed Description

Definition at line 27 of file CMX_CTP_output_module.vhd.

Member Data Documentation

addr_vme in std_logic_vector ( 15 downto 0 )
Port

Definition at line 46 of file CMX_CTP_output_module.vhd.

buf_clk200 in std_logic
Port

Definition at line 38 of file CMX_CTP_output_module.vhd.

buf_clk40 in std_logic
Port

Definition at line 36 of file CMX_CTP_output_module.vhd.

buf_clk40_center in std_logic
Port

Definition at line 37 of file CMX_CTP_output_module.vhd.

bus_drive out std_logic
Port

Definition at line 49 of file CMX_CTP_output_module.vhd.

data in std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )
Port

Definition at line 31 of file CMX_CTP_output_module.vhd.

data_vme_in in std_logic_vector ( 15 downto 0 )
Port

Definition at line 47 of file CMX_CTP_output_module.vhd.

data_vme_out out std_logic_vector ( 15 downto 0 )
Port

Definition at line 48 of file CMX_CTP_output_module.vhd.

ds in std_logic
Port

Definition at line 45 of file CMX_CTP_output_module.vhd.

IEEE
Library

Definition at line 14 of file CMX_CTP_output_module.vhd.

IEEE.NUMERIC_STD.all
Package

Definition at line 16 of file CMX_CTP_output_module.vhd.

IEEE.STD_LOGIC_1164.all
Package

Definition at line 15 of file CMX_CTP_output_module.vhd.

ncs in std_logic
Port

Definition at line 43 of file CMX_CTP_output_module.vhd.

pll_locked in std_logic
Port

Definition at line 39 of file CMX_CTP_output_module.vhd.

rd_nwr in std_logic
Port

Definition at line 44 of file CMX_CTP_output_module.vhd.

sdr_data_out out arr_CTP
Port

Definition at line 34 of file CMX_CTP_output_module.vhd.

spy_write_inhibit in std_logic
Port

Definition at line 41 of file CMX_CTP_output_module.vhd.

start_playback in std_logic
Port

Definition at line 40 of file CMX_CTP_output_module.vhd.

UNISIM
Library

Definition at line 18 of file CMX_CTP_output_module.vhd.

UNISIM.VComponents.all
Package

Definition at line 19 of file CMX_CTP_output_module.vhd.

work
Library

Definition at line 21 of file CMX_CTP_output_module.vhd.

work.CMX_VME_defs.all
Package

Definition at line 23 of file CMX_CTP_output_module.vhd.

work.CMXpackage.all
Package

Definition at line 22 of file CMX_CTP_output_module.vhd.

The documentation for this class was generated from the following file: