Behavioral Architecture Reference

Processes
PROCESS_11	( buf_clk40 , pll_locked )
PROCESS_12	( buf_clk40 )
PROCESS_13	( buf_clk40 , pll_locked )
spy_source_addr_proc	( buf_clk40 )
local_buf_master_inhibit_system	( buf_clk40 , pll_locked )
error_detect_process	( buf_clk40 )
PROCESS_14	( buf_clk40 , pll_locked )
PROCESS_15	( buf_clk40 )
PROCESS_16	( buf_clk40 , pll_locked )
PROCESS_17	( buf_clk40 )

Components
CMX_generic_spy_mem_control_FSM	<Entity CMX_generic_spy_mem_control_FSM>
blk_mem_A8x62_B8x62
Stretch_10	<Entity Stretch_10>
vme_local_switch	<Entity vme_local_switch>
vme_outreg_notri	<Entity vme_outreg_notri>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>

Signals
data_r	std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )
mode_control_CTP_SPY	std_logic_vector ( 3 downto 0 )
ena_CTP_SPY	std_logic
wea_CTP_SPY	std_logic_vector ( 0 downto 0 )
addra_CTP_SPY	std_logic_vector ( 7 downto 0 )
dina_CTP_SPY	std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )
douta_CTP_SPY	std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )
port_b_master_inhibit_CTP_SPY	std_logic
port_b_master_inhibit_CTP_SPY_r	std_logic
spy_write_inhibit_r	std_logic
spy_write_inhibit_rr	std_logic
enb_CTP_SPY	std_logic
web_CTP_SPY	std_logic
enb_CTP_SPY_r	std_logic
web_CTP_SPY_r	std_logic
enb_CTP_SPY_inhibited	std_logic
web_CTP_SPY_inhibited	std_logic_vector ( 0 downto 0 )
addrb_CTP_SPY_counter	unsigned ( 7 downto 0 )
addrb_CTP_SPY	std_logic_vector ( 7 downto 0 )
dinb_CTP_SPY	std_logic_vector ( 61 downto 0 )
doutb_CTP_SPY	std_logic_vector ( 61 downto 0 )
start_playback_r	std_logic
start_playback_rr	std_logic
data_vme_from_below	arr_16 ( 8 downto 0 )
bus_drive_from_below	std_logic_vector ( 8 downto 0 )
bit_error_detect	std_logic_vector ( numbits_in_CTP_connector * 2 - 1 downto 0 )
bit_error_latch	std_logic_vector ( numbits_in_CTP_connector * 2 - 1 downto 0 )
all_null	std_logic_vector ( numbits_in_CTP_connector * 2 - 1 downto 0 )
bit_error_counter	unsigned ( 31 downto 0 )
bit_error_counter_next	unsigned ( 31 downto 0 )
data_to_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
counter_reset	std_logic
counter_reset_unstretched	std_logic
counter_reset_r	std_logic
counter_reset_rr	std_logic
data_to_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_to_vme_reg_ro_ctp_spy_mem_check_error_0	std_logic_vector ( 15 downto 0 )
data_to_vme_reg_ro_ctp_spy_mem_check_error_1	std_logic_vector ( 15 downto 0 )
data_to_vme_reg_ro_ctp_spy_mem_check_error_2	std_logic_vector ( 15 downto 0 )
data_to_vme_reg_ro_ctp_spy_mem_check_error_3	std_logic_vector ( 15 downto 0 )

Attributes
IOB	string
IOB	data_r : signal is " TRUE "

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_inreg_reg_rw_ctp_output_counter_reset	vme_inreg_notri <Entity vme_inreg_notri>
stretch_10_counter_reset	Stretch_10 <Entity Stretch_10>
cmx_generic_spy_mem_control_fsm_inst	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
vme_inreg_reg_rw_ctp_spy_mem_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>
blk_mem_a8x62_b8x62_ctp_spy	blk_mem_a8x62_b8x62
vme_outreg_reg_ro_ctp_spy_mem_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_ctp_spy_mem_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_ctp_spy_mem_check_error_2	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_ctp_spy_mem_check_error_3	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_ctp_spy_mem_noerror_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_ctp_spy_mem_noerror_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>

Detailed Description

Definition at line 54 of file CMX_CTP_output_module.vhd.

Member Function Documentation

error_detect_process (   buf_clk40   )

Process

Definition at line 420 of file CMX_CTP_output_module.vhd.

local_buf_master_inhibit_system (   buf_clk40 ,   pll_locked   )

Process

Definition at line 399 of file CMX_CTP_output_module.vhd.

PROCESS_11	(		buf_clk40 ,
			pll_locked
	)

Definition at line 336 of file CMX_CTP_output_module.vhd.

PROCESS_12 (   buf_clk40   )

Process

Definition at line 344 of file CMX_CTP_output_module.vhd.

PROCESS_13	(		buf_clk40 ,
			pll_locked
	)

Definition at line 376 of file CMX_CTP_output_module.vhd.

PROCESS_14 (   buf_clk40 ,   pll_locked   )

Process

Definition at line 438 of file CMX_CTP_output_module.vhd.

PROCESS_15 (   buf_clk40   )

Process

Definition at line 462 of file CMX_CTP_output_module.vhd.

PROCESS_16 (   buf_clk40 ,   pll_locked   )

Process

Definition at line 468 of file CMX_CTP_output_module.vhd.

PROCESS_17 (   buf_clk40   )

Process

Definition at line 483 of file CMX_CTP_output_module.vhd.

spy_source_addr_proc (   buf_clk40   )

Process

Definition at line 384 of file CMX_CTP_output_module.vhd.

Member Data Documentation

addra_CTP_SPY std_logic_vector ( 7 downto 0 )

Signal

Definition at line 91 of file CMX_CTP_output_module.vhd.

addrb_CTP_SPY std_logic_vector ( 7 downto 0 )

Signal

Definition at line 125 of file CMX_CTP_output_module.vhd.

addrb_CTP_SPY_counter unsigned ( 7 downto 0 )

Signal

Definition at line 124 of file CMX_CTP_output_module.vhd.

all_null std_logic_vector ( numbits_in_CTP_connector * 2 - 1 downto 0 )

Signal

Definition at line 226 of file CMX_CTP_output_module.vhd.

bit_error_counter unsigned ( 31 downto 0 )

Signal

Definition at line 228 of file CMX_CTP_output_module.vhd.

bit_error_counter_next unsigned ( 31 downto 0 )

Signal

Definition at line 229 of file CMX_CTP_output_module.vhd.

bit_error_detect std_logic_vector ( numbits_in_CTP_connector * 2 - 1 downto 0 )

Signal

Definition at line 224 of file CMX_CTP_output_module.vhd.

bit_error_latch std_logic_vector ( numbits_in_CTP_connector * 2 - 1 downto 0 )

Signal

Definition at line 225 of file CMX_CTP_output_module.vhd.

blk_mem_A8x62_B8x62

Component

Definition at line 101 of file CMX_CTP_output_module.vhd.

blk_mem_a8x62_b8x62_ctp_spy blk_mem_a8x62_b8x62

Instantiation

Definition at line 353 of file CMX_CTP_output_module.vhd.

bus_drive_from_below std_logic_vector ( 8 downto 0 )

Signal

Definition at line 152 of file CMX_CTP_output_module.vhd.

CMX_generic_spy_mem_control_FSM

Component

Definition at line 62 of file CMX_CTP_output_module.vhd.

cmx_generic_spy_mem_control_fsm_inst CMX_generic_spy_mem_control_FSM

Instantiation

Definition at line 289 of file CMX_CTP_output_module.vhd.

counter_reset std_logic

Signal

Definition at line 233 of file CMX_CTP_output_module.vhd.

counter_reset_r std_logic

Signal

Definition at line 235 of file CMX_CTP_output_module.vhd.

counter_reset_rr std_logic

Signal

Definition at line 236 of file CMX_CTP_output_module.vhd.

counter_reset_unstretched std_logic

Signal

Definition at line 234 of file CMX_CTP_output_module.vhd.

data_from_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 232 of file CMX_CTP_output_module.vhd.

data_from_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 240 of file CMX_CTP_output_module.vhd.

data_r std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )

Signal

Definition at line 58 of file CMX_CTP_output_module.vhd.

data_to_vme_reg_ro_ctp_spy_mem_check_error_0 std_logic_vector ( 15 downto 0 )

Signal

Definition at line 242 of file CMX_CTP_output_module.vhd.

data_to_vme_reg_ro_ctp_spy_mem_check_error_1 std_logic_vector ( 15 downto 0 )

Signal

Definition at line 243 of file CMX_CTP_output_module.vhd.

data_to_vme_reg_ro_ctp_spy_mem_check_error_2 std_logic_vector ( 15 downto 0 )

Signal

Definition at line 244 of file CMX_CTP_output_module.vhd.

data_to_vme_reg_ro_ctp_spy_mem_check_error_3 std_logic_vector ( 15 downto 0 )

Signal

Definition at line 245 of file CMX_CTP_output_module.vhd.

data_to_vme_REG_RW_CTP_OUTPUT_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 231 of file CMX_CTP_output_module.vhd.

data_to_vme_REG_RW_CTP_SPY_MEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 239 of file CMX_CTP_output_module.vhd.

data_vme_from_below arr_16 ( 8 downto 0 )

Signal

Definition at line 151 of file CMX_CTP_output_module.vhd.

dina_CTP_SPY std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )

Signal

Definition at line 92 of file CMX_CTP_output_module.vhd.

dinb_CTP_SPY std_logic_vector ( 61 downto 0 )

Signal

Definition at line 127 of file CMX_CTP_output_module.vhd.

douta_CTP_SPY std_logic_vector ( ( numbits_in_CTP_connector * 2 ) - 1 downto 0 )

Signal

Definition at line 93 of file CMX_CTP_output_module.vhd.

doutb_CTP_SPY std_logic_vector ( 61 downto 0 )

Signal

Definition at line 128 of file CMX_CTP_output_module.vhd.

ena_CTP_SPY std_logic

Signal

Definition at line 89 of file CMX_CTP_output_module.vhd.

enb_CTP_SPY std_logic

Signal

Definition at line 117 of file CMX_CTP_output_module.vhd.

enb_CTP_SPY_inhibited std_logic

Signal

Definition at line 121 of file CMX_CTP_output_module.vhd.

enb_CTP_SPY_r std_logic

Signal

Definition at line 119 of file CMX_CTP_output_module.vhd.

IOB string

Attribute

Definition at line 56 of file CMX_CTP_output_module.vhd.

IOB data_r : signal is " TRUE "

Attribute

Definition at line 60 of file CMX_CTP_output_module.vhd.

mode_control_CTP_SPY std_logic_vector ( 3 downto 0 )

Signal

Definition at line 88 of file CMX_CTP_output_module.vhd.

port_b_master_inhibit_CTP_SPY std_logic

Signal

Definition at line 94 of file CMX_CTP_output_module.vhd.

port_b_master_inhibit_CTP_SPY_r std_logic

Signal

Definition at line 95 of file CMX_CTP_output_module.vhd.

spy_write_inhibit_r std_logic

Signal

Definition at line 98 of file CMX_CTP_output_module.vhd.

spy_write_inhibit_rr std_logic

Signal

Definition at line 99 of file CMX_CTP_output_module.vhd.

start_playback_r std_logic

Signal

Definition at line 130 of file CMX_CTP_output_module.vhd.

start_playback_rr std_logic

Signal

Definition at line 130 of file CMX_CTP_output_module.vhd.

Stretch_10

Component

Definition at line 134 of file CMX_CTP_output_module.vhd.

stretch_10_counter_reset Stretch_10

Instantiation

Definition at line 282 of file CMX_CTP_output_module.vhd.

vme_inreg_notri

Component

Definition at line 186 of file CMX_CTP_output_module.vhd.

vme_inreg_notri_async

Component

Definition at line 205 of file CMX_CTP_output_module.vhd.

vme_inreg_reg_rw_ctp_output_counter_reset vme_inreg_notri

Instantiation

Definition at line 262 of file CMX_CTP_output_module.vhd.

vme_inreg_reg_rw_ctp_spy_mem_start_address vme_inreg_notri_async

Instantiation

Definition at line 315 of file CMX_CTP_output_module.vhd.

vme_local_switch

Component

Definition at line 142 of file CMX_CTP_output_module.vhd.

vme_local_switch_inst vme_local_switch

Instantiation

Definition at line 254 of file CMX_CTP_output_module.vhd.

vme_outreg_notri

Component

Definition at line 156 of file CMX_CTP_output_module.vhd.

vme_outreg_notri_async

Component

Definition at line 172 of file CMX_CTP_output_module.vhd.

vme_outreg_reg_ro_ctp_spy_mem_check_error_0 vme_outreg_notri_async

Instantiation

Definition at line 509 of file CMX_CTP_output_module.vhd.

vme_outreg_reg_ro_ctp_spy_mem_check_error_1 vme_outreg_notri_async

Instantiation

Definition at line 523 of file CMX_CTP_output_module.vhd.

vme_outreg_reg_ro_ctp_spy_mem_check_error_2 vme_outreg_notri_async

Instantiation

Definition at line 537 of file CMX_CTP_output_module.vhd.

vme_outreg_reg_ro_ctp_spy_mem_check_error_3 vme_outreg_notri_async

Instantiation

Definition at line 550 of file CMX_CTP_output_module.vhd.

vme_outreg_reg_ro_ctp_spy_mem_noerror_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 565 of file CMX_CTP_output_module.vhd.

vme_outreg_reg_ro_ctp_spy_mem_noerror_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 578 of file CMX_CTP_output_module.vhd.

wea_CTP_SPY std_logic_vector ( 0 downto 0 )

Signal

Definition at line 90 of file CMX_CTP_output_module.vhd.

web_CTP_SPY std_logic

Signal

Definition at line 118 of file CMX_CTP_output_module.vhd.

web_CTP_SPY_inhibited std_logic_vector ( 0 downto 0 )

Signal

Definition at line 122 of file CMX_CTP_output_module.vhd.

web_CTP_SPY_r std_logic

Signal

Definition at line 120 of file CMX_CTP_output_module.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_CTP_output_module.vhd