Behavioral Architecture Reference

Processes
rst_ioctrl	( REF_CLK_200 , REF_CLK_READY )

Components
vme_local_switch	<Entity vme_local_switch>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>

Signals
rst_after_clkrdy	std_logic_vector ( num_IDELAYCTRL - 1 downto 0 )
IDELAYCTRL_RDY_sig	std_logic_vector ( num_IDELAYCTRL - 1 downto 0 )
IDELcount_rst_pulse	arr_ctr_16bit ( num_IDELAYCTRL - 1 downto 0 )
IDELcount_rst_pulse_next	arr_ctr_16bit ( num_IDELAYCTRL - 1 downto 0 )
data_to_vme_REG_RO_IDELAYCTRL_RDY	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RO_IDELAYCTRL_RST	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RO_IDELAYCTRL_WAS_RST	std_logic_vector ( 15 downto 0 )
data_vme_from_below	arr_16 ( 2 downto 0 )
bus_drive_from_below	std_logic_vector ( 2 downto 0 )

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_outreg_reg_ro_idelayctrl_rdy	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_idelayctrl_rst	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_idelayctrl_was_rst	vme_outreg_notri_async <Entity vme_outreg_notri_async>
idelayctrl_inst	idelayctrl
iodelaye1_inst_data	iodelaye1
iodelaye1_inst_clkpar	iodelaye1

Detailed Description

Definition at line 56 of file CMX_data_delay.vhd.

Member Function Documentation

rst_ioctrl	(		REF_CLK_200 ,
			REF_CLK_READY
	)

Definition at line 170 of file CMX_data_delay.vhd.

Member Data Documentation

bus_drive_from_below std_logic_vector ( 2 downto 0 )

Signal

Definition at line 79 of file CMX_data_delay.vhd.

data_to_vme_REG_RO_IDELAYCTRL_RDY std_logic_vector ( 15 downto 0 )

Signal

Definition at line 65 of file CMX_data_delay.vhd.

data_to_vme_REG_RO_IDELAYCTRL_RST std_logic_vector ( 15 downto 0 )

Signal

Definition at line 66 of file CMX_data_delay.vhd.

data_to_vme_REG_RO_IDELAYCTRL_WAS_RST std_logic_vector ( 15 downto 0 )

Signal

Definition at line 67 of file CMX_data_delay.vhd.

data_vme_from_below arr_16 ( 2 downto 0 )

Signal

Definition at line 78 of file CMX_data_delay.vhd.

idelayctrl_inst idelayctrl

Instantiation

Definition at line 189 of file CMX_data_delay.vhd.

IDELAYCTRL_RDY_sig std_logic_vector ( num_IDELAYCTRL - 1 downto 0 )

Signal

Definition at line 60 of file CMX_data_delay.vhd.

IDELcount_rst_pulse arr_ctr_16bit ( num_IDELAYCTRL - 1 downto 0 )

Signal

Definition at line 62 of file CMX_data_delay.vhd.

IDELcount_rst_pulse_next arr_ctr_16bit ( num_IDELAYCTRL - 1 downto 0 )

Signal

Definition at line 63 of file CMX_data_delay.vhd.

iodelaye1_inst_clkpar iodelaye1

Instantiation

Definition at line 231 of file CMX_data_delay.vhd.

iodelaye1_inst_data iodelaye1

Instantiation

Definition at line 201 of file CMX_data_delay.vhd.

rst_after_clkrdy std_logic_vector ( num_IDELAYCTRL - 1 downto 0 )

Signal

Definition at line 58 of file CMX_data_delay.vhd.

vme_local_switch

Component

Definition at line 69 of file CMX_data_delay.vhd.

vme_local_switch_inst vme_local_switch

Instantiation

Definition at line 99 of file CMX_data_delay.vhd.

vme_outreg_notri_async

Component

Definition at line 82 of file CMX_data_delay.vhd.

vme_outreg_reg_ro_idelayctrl_rdy vme_outreg_notri_async

Instantiation

Definition at line 107 of file CMX_data_delay.vhd.

vme_outreg_reg_ro_idelayctrl_rst vme_outreg_notri_async

Instantiation

Definition at line 126 of file CMX_data_delay.vhd.

vme_outreg_reg_ro_idelayctrl_was_rst vme_outreg_notri_async

Instantiation

Definition at line 145 of file CMX_data_delay.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_data_delay.vhd