CMX_input_module Entity Reference

Inheritance diagram for CMX_input_module:

Entities
Behavioral	architecture

Libraries
IEEE
UNISIM
work

Use Clauses
IEEE.STD_LOGIC_1164.all
IEEE.NUMERIC_STD.all
UNISIM.VComponents.all
work.CMXpackage.all
work.CMX_VME_defs.all

Ports
P	in mat_var ( numactchan - 1 downto 0 )
buf_clk40	in std_logic
buf_clk40_m180o	in std_logic
buf_clk200	in std_logic
pll_locked	in std_logic
ODATA	out arr_4Xword ( numactchan - 1 downto 0 )
ODATA_first_half	out arr_2Xword ( numactchan - 1 downto 0 )
PAR_ERROR_total	out std_logic
counter_enable_out	out std_logic_vector ( numactchan - 1 downto 0 )
counter_values	out std_logic_vector ( numactchan - 1 downto 0 )
del_register	in del_register_type
upload_delays	in std_logic
quiet	in std_logic
start_playback	in std_logic
spy_write_inhibit	in std_logic
ncs	in std_logic
rd_nwr	in std_logic
ds	in std_logic
addr_vme	in std_logic_vector ( 15 downto 0 )
data_vme_in	in std_logic_vector ( 15 downto 0 )
data_vme_out	out std_logic_vector ( 15 downto 0 )
bus_drive	out std_logic

Detailed Description

Definition at line 25 of file CMX_input_module.vhd.

Member Data Documentation

addr_vme in std_logic_vector ( 15 downto 0 )

Port

Definition at line 60 of file CMX_input_module.vhd.

buf_clk200 in std_logic

Port

Definition at line 30 of file CMX_input_module.vhd.

buf_clk40 in std_logic

Port

Definition at line 28 of file CMX_input_module.vhd.

buf_clk40_m180o in std_logic

Port

Definition at line 29 of file CMX_input_module.vhd.

bus_drive out std_logic

Port

Definition at line 63 of file CMX_input_module.vhd.

counter_enable_out out std_logic_vector ( numactchan - 1 downto 0 )

Port

Definition at line 41 of file CMX_input_module.vhd.

counter_values out std_logic_vector ( numactchan - 1 downto 0 )

Port

Definition at line 42 of file CMX_input_module.vhd.

data_vme_in in std_logic_vector ( 15 downto 0 )

Port

Definition at line 61 of file CMX_input_module.vhd.

data_vme_out out std_logic_vector ( 15 downto 0 )

Port

Definition at line 62 of file CMX_input_module.vhd.

del_register in del_register_type

Port

Definition at line 44 of file CMX_input_module.vhd.

ds in std_logic

Port

Definition at line 59 of file CMX_input_module.vhd.

IEEE

Library

Definition at line 14 of file CMX_input_module.vhd.

IEEE.NUMERIC_STD.all

Package

Definition at line 16 of file CMX_input_module.vhd.

IEEE.STD_LOGIC_1164.all

Package

Definition at line 15 of file CMX_input_module.vhd.

ncs in std_logic

Port

Definition at line 57 of file CMX_input_module.vhd.

ODATA out arr_4Xword ( numactchan - 1 downto 0 )

Port

Definition at line 33 of file CMX_input_module.vhd.

ODATA_first_half out arr_2Xword ( numactchan - 1 downto 0 )

Port

Definition at line 35 of file CMX_input_module.vhd.

P in mat_var ( numactchan - 1 downto 0 )

Port

Definition at line 27 of file CMX_input_module.vhd.

PAR_ERROR_total out std_logic

Port

Definition at line 39 of file CMX_input_module.vhd.

pll_locked in std_logic

Port

Definition at line 31 of file CMX_input_module.vhd.

quiet in std_logic

Port

Definition at line 48 of file CMX_input_module.vhd.

rd_nwr in std_logic

Port

Definition at line 58 of file CMX_input_module.vhd.

spy_write_inhibit in std_logic

Port

Definition at line 54 of file CMX_input_module.vhd.

start_playback in std_logic

Port

Definition at line 51 of file CMX_input_module.vhd.

UNISIM

Library

Definition at line 18 of file CMX_input_module.vhd.

UNISIM.VComponents.all

Package

Definition at line 19 of file CMX_input_module.vhd.

upload_delays in std_logic

Port

Definition at line 45 of file CMX_input_module.vhd.

work

Library

Definition at line 21 of file CMX_input_module.vhd.

work.CMX_VME_defs.all

Package

Definition at line 23 of file CMX_input_module.vhd.

work.CMXpackage.all

Package

Definition at line 22 of file CMX_input_module.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_input_module.vhd