sys_monitor.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;


entity sys_monitor is
  GENERIC(
    ADDR_REG_RO_SYSMON_DATA_BLOCK   : integer := 16#1364#
    
    );
  Port (
    -- Clock 
    clk           : in    std_logic;
    BF_SYSMON_01_P      : in  STD_LOGIC;                         -- Auxiliary Channel 1
    BF_SYSMON_01_N      : in  STD_LOGIC;
    BF_SYSMON_03_P      : in  STD_LOGIC;                         -- Auxiliary Channel 3
    BF_SYSMON_03_N      : in  STD_LOGIC;
    BF_SYSMON_04_P      : in  STD_LOGIC;                         -- Auxiliary Channel 4
    BF_SYSMON_04_N      : in  STD_LOGIC;
    BF_SYSMON_07_P      : in  STD_LOGIC;                         -- Auxiliary Channel 7
    BF_SYSMON_07_N      : in  STD_LOGIC;
    BF_SYSMON_08_P      : in  STD_LOGIC;                         -- Auxiliary Channel 8
    BF_SYSMON_08_N      : in  STD_LOGIC;
    BF_SYSMON_09_P      : in  STD_LOGIC;                         -- Auxiliary Channel 9
    BF_SYSMON_09_N      : in  STD_LOGIC;
    BF_SYSMON_10_P      : in  STD_LOGIC;                         -- Auxiliary Channel 10
    BF_SYSMON_10_N      : in  STD_LOGIC;
    BF_SYSMON_11_P      : in  STD_LOGIC;                         -- Auxiliary Channel 11
    BF_SYSMON_11_N      : in  STD_LOGIC;
    BF_SYSMON_12_P      : in  STD_LOGIC;                         -- Auxiliary Channel 12
    BF_SYSMON_12_N      : in  STD_LOGIC;
    BF_SYSMON_13_P      : in  STD_LOGIC;                         -- Auxiliary Channel 13
    BF_SYSMON_13_N      : in  STD_LOGIC;
    BF_SYSMON_14_P      : in  STD_LOGIC;                         -- Auxiliary Channel 14
    BF_SYSMON_14_N      : in  STD_LOGIC;
    BF_SYSMON_15_P      : in  STD_LOGIC;                         -- Auxiliary Channel 15
    BF_SYSMON_15_N      : in  STD_LOGIC;
    -- VME Control
    ncs           : in    std_logic;   
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );

end sys_monitor;

architecture Behavioral of sys_monitor is

  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;


  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  component sys_mon is
    port (
      DADDR_IN            : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
      DCLK_IN             : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
      DEN_IN              : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
      DI_IN               : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
      DWE_IN              : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
      RESET_IN            : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
      VAUXP1              : in  STD_LOGIC;                         -- Auxiliary Channel 1
      VAUXN1              : in  STD_LOGIC;
      VAUXP3              : in  STD_LOGIC;                         -- Auxiliary Channel 3
      VAUXN3              : in  STD_LOGIC;
      VAUXP4              : in  STD_LOGIC;                         -- Auxiliary Channel 4
      VAUXN4              : in  STD_LOGIC;
      VAUXP7              : in  STD_LOGIC;                         -- Auxiliary Channel 7
      VAUXN7              : in  STD_LOGIC;
      VAUXP8              : in  STD_LOGIC;                         -- Auxiliary Channel 8
      VAUXN8              : in  STD_LOGIC;
      VAUXP9              : in  STD_LOGIC;                         -- Auxiliary Channel 9
      VAUXN9              : in  STD_LOGIC;
      VAUXP10             : in  STD_LOGIC;                         -- Auxiliary Channel 10
      VAUXN10             : in  STD_LOGIC;
      VAUXP11             : in  STD_LOGIC;                         -- Auxiliary Channel 11
      VAUXN11             : in  STD_LOGIC;
      VAUXP12             : in  STD_LOGIC;                         -- Auxiliary Channel 12
      VAUXN12             : in  STD_LOGIC;
      VAUXP13             : in  STD_LOGIC;                         -- Auxiliary Channel 13
      VAUXN13             : in  STD_LOGIC;
      VAUXP14             : in  STD_LOGIC;                         -- Auxiliary Channel 14
      VAUXN14             : in  STD_LOGIC;
      VAUXP15             : in  STD_LOGIC;                         -- Auxiliary Channel 15
      VAUXN15             : in  STD_LOGIC;
      BUSY_OUT            : out  STD_LOGIC;                        -- ADC Busy signal
      CHANNEL_OUT         : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
      DO_OUT              : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
      DRDY_OUT            : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
      EOC_OUT             : out  STD_LOGIC;                        -- End of Conversion Signal
      EOS_OUT             : out  STD_LOGIC;                        -- End of Sequence Signal
      JTAGBUSY_OUT        : out  STD_LOGIC;                        -- JTAG DRP transaction is in progress signal
      JTAGLOCKED_OUT      : out  STD_LOGIC;                        -- DRP port lock request has been made by JTAG
      JTAGMODIFIED_OUT    : out  STD_LOGIC;                        -- Indicates JTAG Write to the DRP has occurred
      OT_OUT              : out  STD_LOGIC;                        -- Over-Temperature alarm output
      VCCAUX_ALARM_OUT    : out  STD_LOGIC;                        -- VCCAUX-sensor alarm output
      VCCINT_ALARM_OUT    : out  STD_LOGIC;                        -- VCCINT-sensor alarm output
      USER_TEMP_ALARM_OUT : out  STD_LOGIC;                        -- Temperature-sensor alarm output
      VP_IN               : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
      VN_IN               : in  STD_LOGIC
      );
  end component;

  -- no more chipscope component sysmon_chipscope_ctrl is
  -- no more chipscope   port (
  -- no more chipscope     CONTROL0: inout std_logic_vector(35 downto 0));
  -- no more chipscope end component;
  -- no more chipscope 
  -- no more chipscope 
  -- no more chipscope component sysmon_chipscope_ila is
  -- no more chipscope   port (
  -- no more chipscope     CONTROL: inout std_logic_vector(35 downto 0);
  -- no more chipscope     CLK: in std_logic;
  -- no more chipscope     DATA: in std_logic_vector(26 downto 0);
  -- no more chipscope     TRIG0: in std_logic_vector(26 downto 0));
  -- no more chipscope end component;
  -- no more chipscope 
  -- no more chipscope 
  -- no more chipscope -- Chipscope
  -- no more chipscope signal control0       : std_logic_vector(35 downto 0);
  -- no more chipscope signal sysmon_trigger : std_logic_vector(26 downto 0);
  -- no more chipscope signal sysmon_data    : std_logic_vector(26 downto 0);
  
  
  -- VME
  signal data_to_vme_REG_RO_SYSMON_DATA_BLOCK : arr_16(14 downto 0);
  signal data_vme_from_below : arr_16(14 downto 0);
  signal bus_drive_from_below : std_logic_vector(14 downto 0);


  -- DRP  
  signal drdy  : std_logic; 
  signal do    : std_logic_vector(15 downto 0);   


  -- Control
  signal busy            : std_logic;                        
  signal channel         : std_logic_vector(4 downto 0);    
  signal eoc             : std_logic;                        
  signal eos             : std_logic;                          
  signal channel_int     : std_logic_vector(6 downto 0);
  
  constant zeros_input   : std_logic_vector(15 downto 0):=(others=>'0');
  
begin

  channel_int <= "00" & channel;

  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_from_below,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_from_below);


  gen_REG_RO_SYSMON_CTRL_BLOCK: for i_reg in 0 to 14 generate
    vme_outreg_notri_async_REG_RO_SYSMON_CTRL_BLOCK : entity work.vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_SYSMON_DATA_BLOCK+(2*i_reg),
        width   => 16)
      port map (
        addr_vme       => addr_vme,
        ncs            => ncs,
        rd_nwr         => rd_nwr,
        ds             => ds,
        data_to_vme    => data_to_vme_REG_RO_SYSMON_DATA_BLOCK(i_reg),
        data_vme       => data_vme_from_below (i_reg),
        bus_drive      => bus_drive_from_below(i_reg));
    
  end generate;

  process(clk)
  begin
    if clk'event and clk = '1' then  -- rising clock edge

      if drdy = '1' and channel = "00000" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(0) <= do;  -- channel 0
      elsif drdy = '1' and channel = "00001" then    
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(1) <= do;   -- channel 1
      elsif drdy = '1' and channel = "00010" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(2) <= do;   -- channel 2
      elsif drdy = '1' and channel = "1001" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(3) <= do;   -- channel 17
      elsif drdy = '1' and channel = "10011" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(4) <= do;   -- channel 19
      elsif drdy = '1' and channel = "10100" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(5) <= do;   -- channel 20
      elsif drdy = '1' and channel = "10111" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(6) <= do;   -- channel 23
      elsif drdy = '1' and channel = "11000" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(7) <= do;   -- channel 24
      elsif drdy = '1' and channel = "11001" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(8) <= do;   -- channel 25
      elsif drdy = '1' and channel = "11010" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(9) <= do;   -- channel 26
      elsif drdy = '1' and channel = "11011" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(10) <= do;  -- channel 27
      elsif drdy = '1' and channel = "11100" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(11) <= do;  -- channel 28
      elsif drdy = '1' and channel = "11101" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(12) <= do;  -- channel 29
      elsif drdy = '1' and channel = "11110" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(13) <= do;  -- channel 30
      elsif drdy = '1' and channel = "11111" then
        data_to_vme_REG_RO_SYSMON_DATA_BLOCK(14) <= do;  -- channel 31
      end if; 
      
      
    end if;
  end process;


  sys_mon_inst : SYS_MON
    port map(
      DADDR_IN             => channel_int,   
      DCLK_IN              => clk,      
      DEN_IN               => eoc,                               
      DI_IN                => zeros_input,                              
      DWE_IN               => '0',                               
      RESET_IN             => '0',                               
      VAUXP1               => BF_SYSMON_01_P,                               
      VAUXN1               => BF_SYSMON_01_N,      
      VAUXP3               => BF_SYSMON_03_P,                               
      VAUXN3               => BF_SYSMON_03_N,      
      VAUXP4               => BF_SYSMON_04_P,                               
      VAUXN4               => BF_SYSMON_04_N,      
      VAUXP7               => BF_SYSMON_07_P,                               
      VAUXN7               => BF_SYSMON_07_N,      
      VAUXP8               => BF_SYSMON_08_P,                               
      VAUXN8               => BF_SYSMON_08_N,      
      VAUXP9               => BF_SYSMON_09_P,                               
      VAUXN9               => BF_SYSMON_09_N,      
      VAUXP10              => BF_SYSMON_10_P,                               
      VAUXN10              => BF_SYSMON_10_N,      
      VAUXP11              => BF_SYSMON_11_P,                               
      VAUXN11              => BF_SYSMON_11_N,      
      VAUXP12              => BF_SYSMON_12_P,                              
      VAUXN12              => BF_SYSMON_12_N,      
      VAUXP13              => BF_SYSMON_13_P,                               
      VAUXN13              => BF_SYSMON_13_N,      
      VAUXP14              => BF_SYSMON_14_P,                               
      VAUXN14              => BF_SYSMON_14_N,      
      VAUXP15              => BF_SYSMON_15_P,                               
      VAUXN15              => BF_SYSMON_15_N,      
      BUSY_OUT             => busy,                               
      CHANNEL_OUT          => channel,           
      DO_OUT               => do,          
      DRDY_OUT             => drdy,                               
      EOC_OUT              => eoc,                               
      EOS_OUT              => eos,                               
      JTAGBUSY_OUT         => open,                              
      JTAGLOCKED_OUT       => open,                            
      JTAGMODIFIED_OUT     => open,                           
      OT_OUT               => open,                           
      VCCAUX_ALARM_OUT     => open,                          
      VCCINT_ALARM_OUT     => open,                          
      USER_TEMP_ALARM_OUT  => open,                        
      VP_IN                => '0',                        
      VN_IN                => '0'
      );

-- no more chipscope   sysmon_chipscope_ctrl_i : sysmon_chipscope_ctrl
-- no more chipscope     port map(
-- no more chipscope       CONTROL0 => control0
-- no more chipscope       );
-- no more chipscope 
-- no more chipscope   sysmon_chipscope_ila_i : sysmon_chipscope_ila 
-- no more chipscope     port map (
-- no more chipscope       CONTROL => control0,
-- no more chipscope       CLK     => clk,
-- no more chipscope       DATA    => sysmon_data,
-- no more chipscope       TRIG0   => sysmon_trigger
-- no more chipscope       );
-- no more chipscope 
-- no more chipscope 
-- no more chipscope -- Chipscope trigger
-- no more chipscope   sysmon_trigger(0) <= ds;
-- no more chipscope   sysmon_trigger(1) <= rd_nwr;
-- no more chipscope   sysmon_trigger(2) <= drdy;
-- no more chipscope   sysmon_trigger(3) <= eoc;
-- no more chipscope   sysmon_trigger(4) <= eos;
-- no more chipscope   sysmon_trigger(5) <= busy;
-- no more chipscope   sysmon_trigger(10 downto 6)   <= channel; 
-- no more chipscope   sysmon_trigger(26 downto 11) <= do;
-- no more chipscope --sysmon_trigger(63 downto 27) <= (others=>'0'); 
-- no more chipscope 
-- no more chipscope -- Chipscope data
-- no more chipscope   sysmon_data <= sysmon_trigger;
  
end Behavioral;