CMX_Memory_spy_inhibit.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


library work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CMX_Memory_spy_inhibit is
  port (
    spy_write_inhibit          : out  std_logic;
    buf_clk40 : in std_logic;
    --VME control:
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;
    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
end CMX_Memory_spy_inhibit;

architecture Behavioral of CMX_Memory_spy_inhibit is
  

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;
  
  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;
  

  signal data_from_vme_REG_RW_SPY_MEM_WRITE_INHIBIT: std_logic_vector(15 downto 0);
  signal   data_to_vme_REG_RW_SPY_MEM_WRITE_INHIBIT: std_logic_vector(15 downto 0);
  
  signal  write_detect_REG_RW_SPY_MEM_WRITE_INHIBIT: std_logic;     

  
  
begin

  vme_inreg_REG_RW_BCID_RESET_VAL: vme_inreg_notri
    generic map (
      ia_vme  => ADDR_REG_RW_SPY_MEM_WRITE_INHIBIT ,
      width   => 16)
    port map (
      clk            => buf_clk40 ,
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out,
      bus_drive      => bus_drive,
      data_from_vme  => data_from_vme_REG_RW_SPY_MEM_WRITE_INHIBIT,
      data_to_vme    => data_to_vme_REG_RW_SPY_MEM_WRITE_INHIBIT,
      read_detect  => open,
      write_detect  => write_detect_REG_RW_SPY_MEM_WRITE_INHIBIT
      );


  process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      if write_detect_REG_RW_SPY_MEM_WRITE_INHIBIT='1' then
        if data_from_vme_REG_RW_SPY_MEM_WRITE_INHIBIT(0)='1' then
          spy_write_inhibit<='1';
        else
          spy_write_inhibit<='0';
        end if;
      end if;
    end if;
  end process;
  
  data_to_vme_REG_RW_SPY_MEM_WRITE_INHIBIT<=data_from_vme_REG_RW_SPY_MEM_WRITE_INHIBIT;

  
end Behavioral;