CMX_rate_counter_inhibit.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


library work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CMX_rate_counter_inhibit is
  port (
    counter_inhibit          : out  std_logic;
    counter_reset            : out  std_logic;
    buf_clk40 : in std_logic;
    --VME control:
    ncs           : in    std_logic;
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
end CMX_rate_counter_inhibit;

architecture Behavioral of CMX_rate_counter_inhibit is
  
  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;
  
  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;

  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;

  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;
  

  signal data_from_vme_REG_RW_RATE_COUNTER_INHIBIT: std_logic_vector(15 downto 0);
  signal   data_to_vme_REG_RW_RATE_COUNTER_INHIBIT: std_logic_vector(15 downto 0);
  signal  write_detect_REG_RW_RATE_COUNTER_INHIBIT: std_logic;     

  signal data_from_vme_REG_RW_RATE_COUNTER_RESET: std_logic_vector(15 downto 0);
  signal   data_to_vme_REG_RW_RATE_COUNTER_RESET: std_logic_vector(15 downto 0);

  
  signal data_vme_out_local : arr_16(3  downto 0);
  signal bus_drive_local : std_logic_vector(3  downto 0);


  signal normalisation_counter : unsigned(32 downto 0);

  signal counter_inhibit_r_local : std_logic;
  signal counter_reset_r_local : std_logic;
  signal counter_inhibit_sig : std_logic;
  signal counter_reset_sig : std_logic;

  signal all_one_thirtythree : std_logic_vector(32 downto 0);
  
  
begin

  all_one_thirtythree<=(others=>'1');

  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local);
  

  vme_inreg_notri_REG_RW_RATE_COUNTER_INHIBIT: entity work.vme_inreg_notri
    generic map (
      ia_vme  => ADDR_REG_RW_RATE_COUNTER_INHIBIT ,
      width   => 16)
    port map (
      clk            => buf_clk40 ,
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(0),
      bus_drive      => bus_drive_local (0),
      data_from_vme  => data_from_vme_REG_RW_RATE_COUNTER_INHIBIT,
      data_to_vme    => data_to_vme_REG_RW_RATE_COUNTER_INHIBIT,
      read_detect    => open,
      write_detect   => write_detect_REG_RW_RATE_COUNTER_INHIBIT);
  data_to_vme_REG_RW_RATE_COUNTER_INHIBIT<=data_from_vme_REG_RW_RATE_COUNTER_INHIBIT;
  
  vme_inreg_notri_async_REG_RW_RATE_COUNTER_RESET: entity work.vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_RATE_COUNTER_RESET ,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(1),
      bus_drive      => bus_drive_local (1),
      data_from_vme  => data_from_vme_REG_RW_RATE_COUNTER_RESET,
      data_to_vme    => data_to_vme_REG_RW_RATE_COUNTER_RESET);
  data_to_vme_REG_RW_RATE_COUNTER_RESET<=data_from_vme_REG_RW_RATE_COUNTER_RESET;

  vme_outreg_notri_async_REG_RO_RATE_NORMALISATION_COUNTER_0: entity work.vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_RATE_NORMALISATION_COUNTER,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme     => data_vme_out_local (2),
      bus_drive    => bus_drive_local (2),
      data_to_vme  => std_logic_vector(normalisation_counter(15 downto 0)));

  
  vme_outreg_notri_async_REG_RO_RATE_NORMALISATION_COUNTER_1: entity work.vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_RATE_NORMALISATION_COUNTER+2,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme     => data_vme_out_local (3),
      bus_drive    => bus_drive_local (3),
      data_to_vme  => std_logic_vector(normalisation_counter(31 downto 16)));


  process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      if write_detect_REG_RW_RATE_COUNTER_INHIBIT='1' then
        if data_from_vme_REG_RW_RATE_COUNTER_INHIBIT(0)='1' then
          counter_inhibit_sig<='1';
        else
          counter_inhibit_sig<='0';
        end if;
      end if;

      
      if data_from_vme_REG_RW_RATE_COUNTER_RESET(0)='1' then
        counter_reset_sig<='1';
      else
        counter_reset_sig<='0';
      end if;

    end if;
      
  end process;

  process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      counter_inhibit_r_local<=counter_inhibit_sig;
      counter_reset_r_local<=counter_reset_sig;
    end if;
  end process;

  counter_inhibit<=counter_inhibit_sig;
  counter_reset<=counter_reset_sig;

  process(buf_clk40)
  begin
    if rising_edge(buf_clk40) then
      if counter_reset_r_local='1' then
        normalisation_counter<=to_unsigned(0,33);
      else
        if normalisation_counter(32)='1' then
          normalisation_counter<=unsigned(all_one_thirtythree);
        else
          if counter_inhibit_r_local /='1' then
            normalisation_counter<=normalisation_counter+1;
          else
            normalisation_counter<=normalisation_counter;
          end if;
        end if;
      end if;
    end if;
  end process;
  

  
end Behavioral;