CMX_pipeline_module.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY unisim ;
USE unisim.VCOMPONENTS.all;



ENTITY CMX_pipeline_module IS
  GENERIC(
    ADDR_REG_RW_PIPELINE_DELAY_LENGTH   : integer := 0
    );
  PORT( 
    clk    : IN     std_logic  ;
    din    : IN     std_logic_vector ;
    dout   : OUT    std_logic_vector ;
    --VME control:
    ncs           : in    std_logic;
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );

-- Declarations

END CMX_pipeline_module ;

-- renoir interface_end
--------------------------------------------------------------------------------
ARCHITECTURE xlx OF CMX_pipeline_module IS
--------------------------------------------------------------------------------
-- variable pipeline, 'width' bits wide of dynamically variable length 0-16,
-- steering address bit 0 selects direct data or through srl if set
-- bits 4-7 control the length of the srl

--------------------------------------------------------------------------------

  constant data_width     : integer := din'length;  --how big is the data port
  constant data_width_out : integer := dout'length;  --how big is the data port


  signal data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RW_PIPELINE_DELAY_LENGTH : std_logic_vector(15 downto 0);
  
  signal delay : std_logic_vector (3 downto 0) ;

  signal enable_srl : std_logic;

  signal dout_srl : std_logic_vector(data_width-1 downto 0);
  
BEGIN

  assert (data_width = data_width_out ) report "input and output port of the pipeline lengths not equal" severity failure;


  vme_inreg_notri_async_REG_RW_PIPELINE_DELAY_LENGTH : entity work.vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_PIPELINE_DELAY_LENGTH ,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out,
      bus_drive      => bus_drive,
      data_from_vme  => data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH ,
      data_to_vme    => data_to_vme_REG_RW_PIPELINE_DELAY_LENGTH);

  data_to_vme_REG_RW_PIPELINE_DELAY_LENGTH<=data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH;

  enable_srl<=data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH(0);
  delay(3 downto 0)<= data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH(7 downto 4);

  gensrl: for i in 0 to (data_width-1) generate
    bit: srl16 port map (
      d =>din(i), clk =>clk, a0 =>delay(0), a1 =>delay(1), 
      a2 =>delay(2), a3 =>delay(3), 
      q =>dout_srl (i)
      );
  end generate gensrl;


  dout<=dout_srl when enable_srl='1' else din;


END xlx;