CMX
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xlx Architecture Reference

Constants

data_width  integer := din ' length
data_width_out  integer := dout ' length

Signals

data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH  std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_PIPELINE_DELAY_LENGTH  std_logic_vector ( 15 downto 0 )
delay  std_logic_vector ( 3 downto 0 )
enable_srl  std_logic
dout_srl  std_logic_vector ( data_width - 1 downto 0 )

Instantiations

vme_inreg_notri_async_reg_rw_pipeline_delay_length  vme_inreg_notri_async <Entity vme_inreg_notri_async>
bit  srl16

Detailed Description

Definition at line 47 of file CMX_pipeline_module.vhd.

Member Data Documentation

bit srl16
Instantiation

Definition at line 94 of file CMX_pipeline_module.vhd.

data_from_vme_REG_RW_PIPELINE_DELAY_LENGTH std_logic_vector ( 15 downto 0 )
Signal

Definition at line 59 of file CMX_pipeline_module.vhd.

data_to_vme_REG_RW_PIPELINE_DELAY_LENGTH std_logic_vector ( 15 downto 0 )
Signal

Definition at line 60 of file CMX_pipeline_module.vhd.

data_width integer := din ' length
Constant

Definition at line 55 of file CMX_pipeline_module.vhd.

data_width_out integer := dout ' length
Constant

Definition at line 56 of file CMX_pipeline_module.vhd.

delay std_logic_vector ( 3 downto 0 )
Signal

Definition at line 62 of file CMX_pipeline_module.vhd.

dout_srl std_logic_vector ( data_width - 1 downto 0 )
Signal

Definition at line 66 of file CMX_pipeline_module.vhd.

enable_srl std_logic
Signal

Definition at line 64 of file CMX_pipeline_module.vhd.

vme_inreg_notri_async_reg_rw_pipeline_delay_length vme_inreg_notri_async
Instantiation

Definition at line 73 of file CMX_pipeline_module.vhd.

The documentation for this class was generated from the following file: