Behavioral Architecture Reference

Processes
PROCESS_46	( buf_clk40 )
PROCESS_47	( buf_clk40 )
PROCESS_48	( buf_clk40 )

Components
vme_local_switch	<Entity vme_local_switch>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>

Signals
data_from_vme_REG_RW_RATE_COUNTER_INHIBIT	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_RATE_COUNTER_INHIBIT	std_logic_vector ( 15 downto 0 )
write_detect_REG_RW_RATE_COUNTER_INHIBIT	std_logic
data_from_vme_REG_RW_RATE_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_RATE_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_vme_out_local	arr_16 ( 3 downto 0 )
bus_drive_local	std_logic_vector ( 3 downto 0 )
normalisation_counter	unsigned ( 32 downto 0 )
counter_inhibit_r_local	std_logic
counter_reset_r_local	std_logic
counter_inhibit_sig	std_logic
counter_reset_sig	std_logic
all_one_thirtythree	std_logic_vector ( 32 downto 0 )

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_inreg_notri_reg_rw_rate_counter_inhibit	vme_inreg_notri <Entity vme_inreg_notri>
vme_inreg_notri_async_reg_rw_rate_counter_reset	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_outreg_notri_async_reg_ro_rate_normalisation_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_notri_async_reg_ro_rate_normalisation_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>

Detailed Description

Definition at line 45 of file CMX_rate_counter_inhibit.vhd.

Member Function Documentation

PROCESS_46

(

buf_clk40

)

Definition at line 202 of file CMX_rate_counter_inhibit.vhd.

PROCESS_47 (   buf_clk40   )

Process

Definition at line 224 of file CMX_rate_counter_inhibit.vhd.

PROCESS_48 (   buf_clk40   )

Process

Definition at line 235 of file CMX_rate_counter_inhibit.vhd.

Member Data Documentation

all_one_thirtythree std_logic_vector ( 32 downto 0 )

Signal

Definition at line 124 of file CMX_rate_counter_inhibit.vhd.

bus_drive_local std_logic_vector ( 3 downto 0 )

Signal

Definition at line 114 of file CMX_rate_counter_inhibit.vhd.

counter_inhibit_r_local std_logic

Signal

Definition at line 119 of file CMX_rate_counter_inhibit.vhd.

counter_inhibit_sig std_logic

Signal

Definition at line 121 of file CMX_rate_counter_inhibit.vhd.

counter_reset_r_local std_logic

Signal

Definition at line 120 of file CMX_rate_counter_inhibit.vhd.

counter_reset_sig std_logic

Signal

Definition at line 122 of file CMX_rate_counter_inhibit.vhd.

data_from_vme_REG_RW_RATE_COUNTER_INHIBIT std_logic_vector ( 15 downto 0 )

Signal

Definition at line 105 of file CMX_rate_counter_inhibit.vhd.

data_from_vme_REG_RW_RATE_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 109 of file CMX_rate_counter_inhibit.vhd.

data_to_vme_REG_RW_RATE_COUNTER_INHIBIT std_logic_vector ( 15 downto 0 )

Signal

Definition at line 106 of file CMX_rate_counter_inhibit.vhd.

data_to_vme_REG_RW_RATE_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 110 of file CMX_rate_counter_inhibit.vhd.

data_vme_out_local arr_16 ( 3 downto 0 )

Signal

Definition at line 113 of file CMX_rate_counter_inhibit.vhd.

normalisation_counter unsigned ( 32 downto 0 )

Signal

Definition at line 117 of file CMX_rate_counter_inhibit.vhd.

vme_inreg_notri

Component

Definition at line 55 of file CMX_rate_counter_inhibit.vhd.

vme_inreg_notri_async

Component

Definition at line 74 of file CMX_rate_counter_inhibit.vhd.

vme_inreg_notri_async_reg_rw_rate_counter_reset vme_inreg_notri_async

Instantiation

Definition at line 158 of file CMX_rate_counter_inhibit.vhd.

vme_inreg_notri_reg_rw_rate_counter_inhibit vme_inreg_notri

Instantiation

Definition at line 139 of file CMX_rate_counter_inhibit.vhd.

vme_local_switch

Component

Definition at line 47 of file CMX_rate_counter_inhibit.vhd.

vme_local_switch_inst vme_local_switch

Instantiation

Definition at line 131 of file CMX_rate_counter_inhibit.vhd.

vme_outreg_notri_async

Component

Definition at line 90 of file CMX_rate_counter_inhibit.vhd.

vme_outreg_notri_async_reg_ro_rate_normalisation_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 174 of file CMX_rate_counter_inhibit.vhd.

vme_outreg_notri_async_reg_ro_rate_normalisation_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 188 of file CMX_rate_counter_inhibit.vhd.

write_detect_REG_RW_RATE_COUNTER_INHIBIT std_logic

Signal

Definition at line 107 of file CMX_rate_counter_inhibit.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_rate_counter_inhibit.vhd