CRC_CALC.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CRC_CALC is
   port (
    DATA_in          : in  std_logic_vector(17 downto 0);
    DATA_out         : out  std_logic_vector(17 downto 0);
    clk              : in std_logic;
    subtick_counter  : in unsigned(2 downto 0));
end CRC_CALC;

architecture Behavioral of CRC_CALC is

  --attribute RLOC: string;
  attribute keep_hierarchy : string;
  
  
  signal b0, b1 : std_logic_vector(7 downto 0);
  signal r0, r1, r2, r3, r4, r5, r6 : std_logic_vector(11 downto 0);  
                                        -- crc register at varoius stages of the computation

  signal subtick_counter_reg_local : unsigned(2 downto 0);  -- local copy of the subtick counter to ease timing
  
  

--  component crc_lut
--    port (
--      addr : in  std_logic_vector(7 downto 0);
--      data : out std_logic_vector(11 downto 0));
--  end component;
--

  COMPONENT crc_distmem
  PORT (
    a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  );
  
  END COMPONENT;

  --attribute RLOC of crc_distmem: component is "X0Y0";
  --attribute RLOC of r0: signal is "X0Y0 X0Y0 X0Y0 X0Y0 X0Y0 X0Y0 X0Y0 X0Y0 X0Y1 X0Y1 X0Y1 X0Y1"; 


  --attribute RLOC of lut_0: entity is "X1Y0";  -- ERROR:HDLCompiler:69 - "/home/wfedorko/L1Calo/Base/Test_2b_Backplane_Capture/trunk/sources/CRC_CALC.vhd" Line 67: <lut_0> is not declared.
  
  --attribute RLOC of lut_0: component is "X1Y0";  --ERROR:HDLCompiler:69 - "/home/wfedorko/L1Calo/Base/Test_2b_Backplane_Capture/trunk/sources/CRC_CALC.vhd" Line 66: <lut_0> is not declared.
  --attribute RLOC of r2: signal is "X1Y0";
  
  --attribute RLOC of lut_0: label is "X1Y0";

  --attribute RLOC of lut_0: label is "R0C1.S0"; --ERROR:Map:201 - Illegal format for RLOC constraint on crc_distmem symbol
   --"Topo_Data_TX_inst/txdatagen_grp[1].txdatagen_fifo[11].CRC_CALC_inst/lut_0". 
   --The value specified is "R0C1.S0".
  --Map:91 - crc_distmem symbol "Topo_Data_TX_inst/txdatagen_grp[0].txdatagen_fifo[0].CRC_CALC_inst/lut_0" has an RLOC attribute but the attribute will be ignored because the hierarchy contains no symbols with RLOC attributes.

    attribute keep_hierarchy of Behavioral : architecture is "TRUE";

begin

  b0<=DATA_in(7 downto 0);
  b1<=DATA_in(15 downto 8);

  r1(11 downto 8)<=r0(3 downto 0);
  r1(7 downto 0)<=b1;

--  lut_0: crc_lut
--    port map (
--        addr => r0(11 downto 4),
--        data => r2);
--

  --attribute RLOC of lut_0: component is "X1Y0";
  
  lut_0: crc_distmem
    port map (
        a    => r0(11 downto 4),
        spo  => r2);

  
  
  r3<=r1 xor r2;

  r4(11 downto 8)<=r3(3 downto 0);
  r4(7 downto 0)<=b0;

--  lut_1: crc_lut
--    port map (
--        addr => r3(11 downto 4),
--        data => r5);
--

  lut_1: crc_distmem
    port map (
        a    => r3(11 downto 4),
        spo  => r5);
  
  r6<= r5 xor r4;

  process (clk)
  begin  -- process
    if rising_edge(clk) then  -- rising clock edge
      if subtick_counter_reg_local=to_unsigned(7,3) then --=to_unsigned(0,3) then
        DATA_out(11 downto 0)<=r6;
        DATA_out(17 downto 12)<=DATA_in(17 downto 12);
        r0<=(others=>'0');
      else
        DATA_out<=DATA_in;
        r0<=r6;
      end if;
      subtick_counter_reg_local<=subtick_counter;
    end if;
  end process;
  
end Behavioral;