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Topo_Data_TX.vhd
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1 -------------------------------------------------------------------------------
7 -------------------------------------------------------------------------------
8 
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.std_logic_misc.all;
12 use ieee.numeric_std.all;
13 library UNISIM;
14 use UNISIM.VCOMPONENTS.ALL;
15 
16 
17 library work;
18 use work.CMXpackage.all;
19 use work.CMX_VME_defs.all;
20 
21 
22 
23 entity Topo_Data_TX is
24 
25  port
26  (
27  MGTREFCLK_PAD_N_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
28  MGTREFCLK_PAD_P_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
29  GTXTXRESET_IN : in std_logic;
30  GTXRXRESET_IN : in std_logic;
31  GTX_TX_READY_OUT : out std_logic;
32  GTX_RX_READY_OUT : out std_logic;
33  --GTXRXRESET_IN : in std_logic;
34  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
35  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
36  TXN_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
37  TXP_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
38  clk40 : in std_logic;
39  clk320 : in std_logic;
40  pll_locked : in std_logic;
41  send_align : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
42  BCID : in std_logic_vector(11 downto 0);
43  --TXUSRCLK2_IN_bufferedG_out : out std_logic_vector((num_GTX_groups)-1 downto 0);
44  --RXUSRCLK2_IN_out : out std_logic_vector((num_GTX_groups*num_GTX_per_group)-1 downto 0);
45  --RX_ERROR_OUT : out std_logic;
46  --RX_COMMA_RECEIVED : out std_logic_vector ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
47  --ila_trigger_held20_out : out std_logic;
48  indata : in std_logic_vector(TX_indata_length-1 downto 0);
49 
50  ext_trigger :in std_logic;
51  --VME control:
52  ncs : in std_logic;
53  rd_nwr : in std_logic;
54  ds : in std_logic;
55  addr_vme : in std_logic_vector (15 downto 0);
56  data_vme_in : in std_logic_vector (15 downto 0);
57  data_vme_out : out std_logic_vector (15 downto 0);
58  bus_drive : out std_logic
59  );
60 
61 
62 end Topo_Data_TX;
63 
64 
65 
66 architecture RTL of Topo_Data_TX is
67 
68  attribute keep : string;
69 
70  attribute BUFFER_TYPE : string;
71 
72  ----------------------------- Reference Clocks ----------------------------
73 
74  signal q1_clk0_refclk_i : std_logic;
75  signal q4_clk0_refclk_i : std_logic;
76  signal refclk_i : std_logic_vector(num_GTX_groups-1 downto 0);
77 
78 
79 -- signals for the fifos crossing from system to MGT clock domains
80 -- signal wr_en : std_logic_vector(num_GTX_groups - 1 downto 0);
81 -- signal rd_en : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
82 -- signal full : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
83 -- signal overflow : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
84 -- signal underflow : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
85 -- signal almost_full : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
86 -- signal empty : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
87 -- signal almost_empty : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
88 -- signal rd_data_count: arr_rd_data_count(num_GTX_groups*num_fifos_per_group - 1 downto 0);
89 -- signal wr_data_count: arr_wr_data_count(num_GTX_groups*num_fifos_per_group - 1 downto 0);
90  signal fifo_dout: std_logic_vector(num_GTX_groups*num_GTX_per_group*(GTX_data_word_width+2)-1 downto 0);
91 
92 
93  signal time_multiplex_data_in: arr_time_multiplex_data_in(num_GTX_groups*num_fifos_per_group - 1 downto 0);
94  signal time_multiplex_data_out: arr_time_multiplex_data_out(num_GTX_groups*num_fifos_per_group - 1 downto 0);
95  signal time_multiplex_data_out_CRC: arr_time_multiplex_data_out(num_GTX_groups*num_fifos_per_group - 1 downto 0);
96  signal subtick_counter : arr_ctr_3bit(num_GTX_groups*num_fifos_per_group - 1 downto 0);
97 
98  signal RXDATA_OUT_reg : arr_GTX_data; --delayed once for the CRC_CHECK input
99  signal subtick_counter_rx_reg : arr_ctr_3bit(num_GTX_groups*num_fifos_per_group - 1 downto 0);
100 
101  signal subtick_counter_rx : arr_ctr_3bit(num_GTX_groups*num_fifos_per_group - 1 downto 0);
102  signal subtick_counter_rx_next : arr_ctr_3bit(num_GTX_groups*num_fifos_per_group - 1 downto 0);
103  signal subtick_counter_rx_started : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
104 
105 
106 
107  signal rx_error_not_in_table : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
108  signal rx_error_byterealign : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
109  signal rx_error_eventrealign : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
110  signal rx_error_disparity : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
111  signal rx_error_crc : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
112 
113  signal rx_error_any : std_logic_vector(num_GTX_groups*num_fifos_per_group - 1 downto 0);
114 
115 
116 
117  signal rx_error_not_in_table_all : std_logic;
118  signal rx_error_byterealign_all : std_logic;
119  signal rx_error_eventrealign_all : std_logic;
120  signal rx_error_disparity_all: std_logic;
121  signal rx_error_crc_all : std_logic;
122 
123  --signal RX_ERROR_OUT_sig : std_logic;
124 
125  --signals for GTX ports IN OUT designates input/output to/from the GTX
126 
127  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
128  signal TXCHARISK_IN : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
129  signal TXKERR_OUT : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
130  signal TXKERR_OUT_UPPER : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
131  ------------------ Transmit Ports - TX Data Path interface -----------------
132  signal TXDATA_IN : arr_GTX_data;
133  signal TXOUTCLK_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
134  signal TXUSRCLK2_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
135  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
136  signal TXDIFFCTRL_IN : arr_4((num_GTX_per_group*num_GTX_groups)-1 downto 0);
137  signal TXPOSTEMPHASIS_IN : arr_5((num_GTX_per_group*num_GTX_groups)-1 downto 0);
138  --------------- Transmit Ports - TX Driver and OOB signalling --------------
139  signal TXPREEMPHASIS_IN : arr_4((num_GTX_per_group*num_GTX_groups)-1 downto 0);
140  -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
141  signal TXDLYALIGNDISABLE_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
142  signal TXDLYALIGNMONENB_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
143  signal TXDLYALIGNMONITOR_OUT : arr_8((num_GTX_per_group*num_GTX_groups)-1 downto 0);
144  signal TXDLYALIGNRESET_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
145  signal TXENPMAPHASEALIGN_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
146  signal TXPMASETPHASE_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
147  ----------------------- Transmit Ports - TX PLL Ports ----------------------
148  --signal GTXTXRESET_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
149  signal MGTREFCLKTX_IN : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
150  signal PLLTXRESET_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
151  signal TXPLLLKDET_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
152  signal TXRESETDONE_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
153 
154  ----------------------- Receive Ports - 8b10b Decoder ----------------------
155  signal RXCHARISCOMMA_OUT : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
156  signal RXCHARISK_OUT : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
157  signal RXDISPERR_OUT : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
158  signal RXNOTINTABLE_OUT : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
159  --------------- Receive Ports - Comma Detection and Alignment --------------
160  signal RXBYTEISALIGNED_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
161  signal RXBYTEISALIGNED_OUT_r : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
162  signal RXBYTEREALIGN_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
163  signal RXCOMMADET_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
164  signal RXENMCOMMAALIGN_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
165  signal RXENPCOMMAALIGN_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
166  ------------------- Receive Ports - RX Data Path interface -----------------
167  signal RXDATA_OUT : arr_GTX_data;
168  signal rxdata_i : arr_2GTX_data;
169  signal RXRECCLK_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
170  signal RXUSRCLK2_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
171 
172  ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
173  signal DFECLKDLYADJ : arr_6((num_GTX_per_group*num_GTX_groups)-1 downto 0);
174  signal DFECLKDLYADJMON : arr_6((num_GTX_per_group*num_GTX_groups)-1 downto 0);
175  signal DFEDLYOVRD : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
176  signal DFEEYEDACMON : arr_5((num_GTX_per_group*num_GTX_groups)-1 downto 0);
177  signal DFESENSCAL : arr_3((num_GTX_per_group*num_GTX_groups)-1 downto 0);
178  signal DFETAP1 : arr_5((num_GTX_per_group*num_GTX_groups)-1 downto 0);
179  signal DFETAP1MONITOR : arr_5((num_GTX_per_group*num_GTX_groups)-1 downto 0);
180  signal DFETAP2 : arr_5((num_GTX_per_group*num_GTX_groups)-1 downto 0);
181  signal DFETAP2MONITOR : arr_5((num_GTX_per_group*num_GTX_groups)-1 downto 0);
182  signal DFETAP3 : arr_4((num_GTX_per_group*num_GTX_groups)-1 downto 0);
183  signal DFETAP3MONITOR : arr_4((num_GTX_per_group*num_GTX_groups)-1 downto 0);
184  signal DFETAP4 : arr_4((num_GTX_per_group*num_GTX_groups)-1 downto 0);
185  signal DFETAP4MONITOR : arr_4((num_GTX_per_group*num_GTX_groups)-1 downto 0);
186  signal DFETAPOVRD : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
187 
188  ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
189  signal RXEQMIX_IN : arr_3((num_GTX_per_group*num_GTX_groups)-1 downto 0);
190 
191  -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
192  signal RXDLYALIGNDISABLE_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
193  signal RXDLYALIGNMONENB_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
194  signal RXDLYALIGNMONITOR_OUT : arr_8((num_GTX_per_group*num_GTX_groups)-1 downto 0);
195  signal RXDLYALIGNOVERRIDE_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
196  signal RXDLYALIGNRESET_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
197  signal RXENPMAPHASEALIGN_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
198  signal RXPMASETPHASE_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
199  signal RXBUFSTATUS_OUT : arr_3((num_GTX_per_group*num_GTX_groups)-1 downto 0);
200  ------------------------ Receive Ports - RX PLL Ports ----------------------
201 
202  signal MGTREFCLKRX_IN : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
203  signal PLLRXRESET_IN : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
204  signal RXPLLLKDET_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
205  signal RXRESETDONE_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
206 
207  signal RXRESETDONE_OUT_r : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
208  signal RXRESETDONE_OUT_rr : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
209  signal RXRESETDONE_OUT_rrr : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
210  signal RXRESETDONE_OUT_rrrr : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
211 
212 
213  -- output signals to be left floating
214  signal rxchariscomma_float_i : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
215  signal rxcharisk_float_i : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
216  signal rxdisperr_float_i : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
217  signal rxnotintable_float_i : arr_2((num_GTX_per_group*num_GTX_groups)-1 downto 0);
218 
219 
220  --clocking signals
221  signal mmcm_fback: std_logic_vector(num_GTX_groups-1 downto 0);
222  signal TXUSRCLK2_IN_unbuffered: std_logic_vector(num_GTX_groups-1 downto 0);
223  signal TXUSRCLK2_IN_bufferedG: std_logic_vector(num_GTX_groups-1 downto 0);
224  signal RXUSRCLK2_IN_bufferedR: std_logic_vector( num_GTX_groups-1 downto 0);
225  signal mmcm_locked: std_logic_vector(num_GTX_groups-1 downto 0);
226 
227 
228  -- ground and tied_to_vcc_i signals
229  signal tied_to_ground_i : std_logic;
230  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
231  signal tied_to_vcc_i : std_logic;
232  --signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
233 
234  signal TXPLLLKDET_group : std_logic_vector(num_GTX_groups-1 downto 0);
235  signal RXPLLLKDET_group : std_logic_vector(num_GTX_groups-1 downto 0);
236  signal cTXPLLLKDET_group : std_logic_vector(num_GTX_groups-1 downto 0);
237  signal cRXPLLLKDET_group : std_logic_vector(num_GTX_groups-1 downto 0);
238 
239  --signals for the phase syncronization FSMs
240  signal reset_tx_sync : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
241  signal reset_rx_sync : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
242 
243  signal TXRESETDONE_OUT_r : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
244  signal TXRESETDONE_OUT_rr : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
245 
246  signal rx_sync_done : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
247  signal tx_sync_done : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
248 
249  signal long_counter : long_unsigned_array( (num_GTX_per_group*num_GTX_groups)-1 downto 0);
250  signal short_counter : short_unsigned_array(num_GTX_groups-1 downto 0);
251  signal long_counter_next : long_unsigned_array( (num_GTX_per_group*num_GTX_groups)-1 downto 0);
252  signal short_counter_next : short_unsigned_array(num_GTX_groups-1 downto 0);
253  signal wait_done : std_logic_vector( (num_GTX_per_group*num_GTX_groups)-1 downto 0);
254 
255  signal RXRESETDONE_OUT_group : std_logic_vector( num_GTX_groups-1 downto 0 );
256 
257  --signal GTX_TX_READY_OUT_sig: std_logic;
258  --signal cGTX_TX_READY_OUT_sig: std_logic;
259  signal tx_sync_done_grp : std_logic_vector(num_GTX_groups-1 downto 0);
260  signal tx_sync_done_grp_r : std_logic_vector(num_GTX_groups-1 downto 0);
261  signal c_tx_sync_done_grp : std_logic_vector(num_GTX_groups-1 downto 0);
262  signal c_tx_sync_done_grp_r : std_logic_vector(num_GTX_groups-1 downto 0);
263  signal c_tx_sync_done_grp_shiftreg : arr_20(num_GTX_groups-1 downto 0);
264 
265  signal c_tx_sync_done_grp_r_held20 : std_logic_vector(num_GTX_groups-1 downto 0);
266  --this will be used as a reset for
267  --wr_en; hold for 20 cycles to avoid
268  --timing violation
269  signal c_tx_sync_done_grp_r_held20_r : std_logic_vector(num_GTX_groups-1 downto 0);
270  -- same as above registered in the
271  -- gtx (bufg) domain
272 -- signal wr_en_delay : arr_4(num_GTX_groups-1 downto 0);
273 
274 
275 
276  -- --these two sync the signal to the system domain
277  -- signal c_tx_sync_done_grp_r_held20_r_clk320 : std_logic_vector(num_GTX_groups-1 downto 0);
278  -- signal c_tx_sync_done_grp_r_held20_rr_clk320 : std_logic_vector(num_GTX_groups-1 downto 0);
279  --
280  -- --this delays once more so that there is the same delay in the system and gtx
281  -- --domain
282  -- signal c_tx_sync_done_grp_r_held20_rrr_clk320 : std_logic_vector(num_GTX_groups-1 downto 0);
283  --
284  -- --synchronise the signal back into the gtx domain
285  -- signal c_tx_sync_done_grp_r_held20_r_clk320_r_clkgtx : std_logic_vector(num_GTX_groups-1 downto 0);
286 
287  signal GTX_RX_READY_OUT_sig: std_logic;
288 
289  --ATTRIBUTE buffer_type OF cGTX_TX_READY_OUT_sig : SIGNAL IS "none";
290 
291  component and_all
292  generic
293  (
294  numbits : integer
295  );
296  port(
297  DATA : in std_logic_vector(numbits - 1 downto 0);
298  and_all : out std_logic);
299  end component;
300 
301  component or_all
302  generic (
303  numbits : integer);
304  port (
305  DATA : in std_logic_vector(numbits - 1 downto 0);
306  or_all : out std_logic);
307  end component;
308 
309  component tx_sync
310  generic (
311  SIM_TXPMASETPHASE_SPEEDUP : integer);
312  port (
313  TXENPMAPHASEALIGN : out std_logic;
314  TXPMASETPHASE : out std_logic;
315  TXDLYALIGNDISABLE : out std_logic;
316  TXDLYALIGNRESET : out std_logic;
317  SYNC_DONE : out std_logic;
318  USER_CLK : in std_logic;
319  RESET : in std_logic);
320  end component;
321 
322 
323  component rx_sync
324  port
325  (
326  RXENPMAPHASEALIGN : out std_logic;
327  RXPMASETPHASE : out std_logic;
328  RXDLYALIGNDISABLE : out std_logic;
329  RXDLYALIGNOVERRIDE : out std_logic;
330  RXDLYALIGNRESET : out std_logic;
331  SYNC_DONE : out std_logic;
332  USER_CLK : in std_logic;
333  RESET : in std_logic
334  );
335  end component;
336 
337  component prng24
338  generic (
339  seed : integer);
340  port (
341  clk : in std_logic;
342  rst : in std_logic;
343  rand : out std_logic_vector(23 downto 0));
344  end component;
345 
346  component mini_fifo_synchroniser
347  port (
348  set_mem_ctr_i_out : out std_logic;
349  set_mem_ctr_o_out : out std_logic;
350  clk_i_dom : in std_logic;
351  clk_o_dom : in std_logic;
352  set : in std_logic);
353  end component;
354 
355  signal set_mem_ctr_i, set_mem_ctr_o : std_logic_vector(num_GTX_groups - 1 downto 0);
356 
357  component CRC_CALC
358  port (
359  DATA_in : in std_logic_vector(17 downto 0);
360  DATA_out : out std_logic_vector(17 downto 0);
361  clk : in std_logic;
362  subtick_counter : in unsigned(2 downto 0));
363  end component;
364 
365  component CRC_CHECK
366  port (
367  DATA_in : in std_logic_vector(15 downto 0);
368  CRC_ERR : out std_logic;
369  clk : in std_logic;
370  rx_subtick_counter : in unsigned(2 downto 0));
371  end component;
372 
373  component mini_fifo
374  generic (
375  numbits : integer := TX_fifo_indata_length);
376  port (
377  DATA_in : in std_logic_vector(numbits-1 downto 0);
378  DATA_out : out std_logic_vector(numbits-1 downto 0);
379  clk_i_dom : in std_logic;
380  clk_o_dom : in std_logic;
381  set_mem_ctr_i : in std_logic;
382  set_mem_ctr_o : in std_logic);
383  end component;
384 
385 -- component block_mem
386 -- port (
387 -- clka : IN STD_LOGIC;
388 -- ena : IN STD_LOGIC;
389 -- wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
390 -- addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
391 -- dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
392 -- clkb : IN STD_LOGIC;
393 -- enb : IN STD_LOGIC;
394 -- addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
395 -- doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0));
396 -- end component;
397 --
398 -- component TopoTX_fifo
399 -- port (
400 -- rst : IN STD_LOGIC;
401 -- wr_clk : IN STD_LOGIC;
402 -- rd_clk : IN STD_LOGIC;
403 -- din : IN STD_LOGIC_VECTOR(TX_fifo_indata_length-1 DOWNTO 0);
404 -- wr_en : IN STD_LOGIC;
405 -- rd_en : IN STD_LOGIC;
406 -- dout : OUT STD_LOGIC_VECTOR(TX_fifo_indata_length-1 DOWNTO 0);
407 -- full : OUT STD_LOGIC;
408 -- empty : OUT STD_LOGIC);
409 -- end component;
410 
411  -- COMPONENT TopoTX_fifo
412  -- PORT (
413  -- rst : IN STD_LOGIC;
414  -- wr_clk : IN STD_LOGIC;
415  -- rd_clk : IN STD_LOGIC;
416  -- din : IN STD_LOGIC_VECTOR( TX_fifo_indata_length-1 DOWNTO 0);
417  -- wr_en : IN STD_LOGIC;
418  -- rd_en : IN STD_LOGIC;
419  -- dout : OUT STD_LOGIC_VECTOR( TX_fifo_odata_length-1 DOWNTO 0);
420  -- full : OUT STD_LOGIC;
421  -- almost_full : OUT STD_LOGIC;
422  -- overflow : OUT STD_LOGIC;
423  -- empty : OUT STD_LOGIC;
424  -- almost_empty : OUT STD_LOGIC;
425  -- underflow : OUT STD_LOGIC;
426  -- rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
427  -- wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
428  -- );
429  -- end component;
430 
431 
432 
433 
434  component time_multiplex_8to1
435  port (
436  DATA_in : in std_logic_vector;
437  send_align : in std_logic;
438  BCID : in std_logic_vector(11 downto 0);
439  DATA_out : out std_logic_vector;
440  subtick_counter_out : out unsigned(2 downto 0);
441  clk_slow : in std_logic;
442  clk_fast : in std_logic;
443  pll_locked : in std_logic);
444  end component;
445 
446 
447 
448  component vme_local_switch is
449  port (
450  data_vme_up : out std_logic_vector (15 downto 0);
451  data_vme_from_below : in arr_16;
452  bus_drive_up : out std_logic;
453  bus_drive_from_below : in std_logic_vector);
454  end component vme_local_switch;
455 
456 
457  signal data_vme_from_below : arr_16(5 downto 0);
458  signal bus_drive_from_below : std_logic_vector(5 downto 0);
459 
460 
461  component vme_inreg_notri_async is
462  generic (
463  ia_vme : integer;
464  width : integer);
465  port (
466  ncs : in std_logic;
467  rd_nwr : in std_logic;
468  ds : in std_logic;
469  addr_vme : in std_logic_vector (15 downto 0);
470  data_vme_in : in std_logic_vector (15 downto 0);
471  data_vme_out : out std_logic_vector (15 downto 0);
472  bus_drive : out std_logic;
473  data_from_vme : out std_logic_vector (width-1 downto 0);
474  data_to_vme : in std_logic_vector (width-1 downto 0));
475  end component vme_inreg_notri_async;
476 
477 
478 
479  --
480  signal rand: arr_24((num_GTX_per_group*num_GTX_groups)-1 downto 0);
481 
482  constant SIM_GTXRESET_SPEEDUP: integer := 0; -- speedup the sync procedure?
483 
484 
485  signal tx_polarity, rx_polarity: std_logic_vector(47 downto 0);
486 
487  --attribute keep of TXDATA_IN, RXDATA_OUT, RXCHARISK_OUT, TXCHARISK_IN, RXCHARISCOMMA_OUT : signal is "TRUE";
488 
489  attribute keep of rx_error_crc, RXDATA_OUT, RXCHARISK_OUT : signal is "TRUE";
490 
491  -----------------------------------------------------------------------
492  ----
493  ---- ICON component declaration
494  ----
495  -----------------------------------------------------------------------
496  --
497  --component chipscope_icon_Topo_Data_TX
498  -- port (
499  -- CONTROL0 : inout std_logic_vector(35 downto 0)
500  -- );
501  --end component;
502  --
503  --
504  -----------------------------------------------------------------------
505  ----
506  ---- ILA component declaration
507  ----
508  -----------------------------------------------------------------------
509  --
510  --component chipscope_ila_Topo_Data_TX
511  -- port (
512  -- CONTROL : inout std_logic_vector(35 downto 0);
513  -- CLK : in std_logic;
514  -- DATA : in std_logic_vector(46 downto 0);
515  -- TRIG0 : in std_logic_vector(15 downto 0);
516  -- TRIG_OUT : OUT STD_LOGIC
517  -- );
518  --end component;
519  --
520  --signal CONTROL0 : std_logic_vector(35 downto 0);
521  --signal TRIG_OUT : std_logic;
522  --
523  --attribute keep of TRIG_OUT : signal is "TRUE";
524  --attribute keep of full, almost_full, overflow, almost_empty, underflow, rd_data_count, wr_data_count : signal is "TRUE";
525 
526 
527  --------------------------------------------------------------------------------
528  -- New ICON/ILA cores
529  --------------------------------------------------------------------------------
530 
531 --WTF NO CS 20141112 -- component chipscope_icon_TopoTXRX_u3_15
532 --WTF NO CS 20141112 -- port (
533 --WTF NO CS 20141112 -- CONTROL0 : inout std_logic_vector(35 downto 0);
534 --WTF NO CS 20141112 -- CONTROL1 : inout std_logic_vector(35 downto 0);
535 --WTF NO CS 20141112 -- CONTROL2 : inout std_logic_vector(35 downto 0);
536 --WTF NO CS 20141112 -- CONTROL3 : inout std_logic_vector(35 downto 0);
537 --WTF NO CS 20141112 -- CONTROL4 : inout std_logic_vector(35 downto 0);
538 --WTF NO CS 20141112 -- CONTROL5 : inout std_logic_vector(35 downto 0);
539 --WTF NO CS 20141112 -- CONTROL6 : inout std_logic_vector(35 downto 0);
540 --WTF NO CS 20141112 -- CONTROL7 : inout std_logic_vector(35 downto 0);
541 --WTF NO CS 20141112 -- CONTROL8 : inout std_logic_vector(35 downto 0);
542 --WTF NO CS 20141112 -- CONTROL9 : inout std_logic_vector(35 downto 0);
543 --WTF NO CS 20141112 -- CONTROL10 : inout std_logic_vector(35 downto 0);
544 --WTF NO CS 20141112 -- CONTROL11 : inout std_logic_vector(35 downto 0);
545 --WTF NO CS 20141112 -- CONTROL12 : inout std_logic_vector(35 downto 0);
546 --WTF NO CS 20141112 -- CONTROL13 : inout std_logic_vector(35 downto 0);
547 --WTF NO CS 20141112 -- CONTROL14 : inout std_logic_vector(35 downto 0));
548 --WTF NO CS 20141112 -- end component;
549 --WTF NO CS 20141112 --
550 --WTF NO CS 20141112 -- component chipscope_icon_TopoTXRX_u2_15
551 --WTF NO CS 20141112 -- port (
552 --WTF NO CS 20141112 -- CONTROL0 : inout std_logic_vector(35 downto 0);
553 --WTF NO CS 20141112 -- CONTROL1 : inout std_logic_vector(35 downto 0);
554 --WTF NO CS 20141112 -- CONTROL2 : inout std_logic_vector(35 downto 0);
555 --WTF NO CS 20141112 -- CONTROL3 : inout std_logic_vector(35 downto 0);
556 --WTF NO CS 20141112 -- CONTROL4 : inout std_logic_vector(35 downto 0);
557 --WTF NO CS 20141112 -- CONTROL5 : inout std_logic_vector(35 downto 0);
558 --WTF NO CS 20141112 -- CONTROL6 : inout std_logic_vector(35 downto 0);
559 --WTF NO CS 20141112 -- CONTROL7 : inout std_logic_vector(35 downto 0);
560 --WTF NO CS 20141112 -- CONTROL8 : inout std_logic_vector(35 downto 0);
561 --WTF NO CS 20141112 -- CONTROL9 : inout std_logic_vector(35 downto 0);
562 --WTF NO CS 20141112 -- CONTROL10 : inout std_logic_vector(35 downto 0);
563 --WTF NO CS 20141112 -- CONTROL11 : inout std_logic_vector(35 downto 0);
564 --WTF NO CS 20141112 -- CONTROL12 : inout std_logic_vector(35 downto 0);
565 --WTF NO CS 20141112 -- CONTROL13 : inout std_logic_vector(35 downto 0);
566 --WTF NO CS 20141112 -- CONTROL14 : inout std_logic_vector(35 downto 0));
567 --WTF NO CS 20141112 -- end component;
568 --WTF NO CS 20141112 --
569 --WTF NO CS 20141112 -- component chipscope_icon_TopoTXRX_u4_14
570 --WTF NO CS 20141112 -- port (
571 --WTF NO CS 20141112 -- CONTROL0 : inout std_logic_vector(35 downto 0);
572 --WTF NO CS 20141112 -- CONTROL1 : inout std_logic_vector(35 downto 0);
573 --WTF NO CS 20141112 -- CONTROL2 : inout std_logic_vector(35 downto 0);
574 --WTF NO CS 20141112 -- CONTROL3 : inout std_logic_vector(35 downto 0);
575 --WTF NO CS 20141112 -- CONTROL4 : inout std_logic_vector(35 downto 0);
576 --WTF NO CS 20141112 -- CONTROL5 : inout std_logic_vector(35 downto 0);
577 --WTF NO CS 20141112 -- CONTROL6 : inout std_logic_vector(35 downto 0);
578 --WTF NO CS 20141112 -- CONTROL7 : inout std_logic_vector(35 downto 0);
579 --WTF NO CS 20141112 -- CONTROL8 : inout std_logic_vector(35 downto 0);
580 --WTF NO CS 20141112 -- CONTROL9 : inout std_logic_vector(35 downto 0);
581 --WTF NO CS 20141112 -- CONTROL10 : inout std_logic_vector(35 downto 0);
582 --WTF NO CS 20141112 -- CONTROL11 : inout std_logic_vector(35 downto 0);
583 --WTF NO CS 20141112 -- CONTROL12 : inout std_logic_vector(35 downto 0);
584 --WTF NO CS 20141112 -- CONTROL13 : inout std_logic_vector(35 downto 0));
585 --WTF NO CS 20141112 -- end component;
586 --WTF NO CS 20141112 --
587 --WTF NO CS 20141112 --
588 --WTF NO CS 20141112 -- component chipscope_icon_TopoTXRX_u3_6
589 --WTF NO CS 20141112 -- port (
590 --WTF NO CS 20141112 -- CONTROL0 : inout std_logic_vector(35 downto 0);
591 --WTF NO CS 20141112 -- CONTROL1 : inout std_logic_vector(35 downto 0);
592 --WTF NO CS 20141112 -- CONTROL2 : inout std_logic_vector(35 downto 0);
593 --WTF NO CS 20141112 -- CONTROL3 : inout std_logic_vector(35 downto 0);
594 --WTF NO CS 20141112 -- CONTROL4 : inout std_logic_vector(35 downto 0);
595 --WTF NO CS 20141112 -- CONTROL5 : inout std_logic_vector(35 downto 0));
596 --WTF NO CS 20141112 -- end component;
597 
598  ---
599  --- component chipscope_icon_TopoTXRX
600  --- port (
601  --- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
602  --- CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
603  --- CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
604  --- CONTROL3 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
605  --- CONTROL4 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
606  --- CONTROL5 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
607  --- CONTROL6 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
608  --- CONTROL7 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
609  --- CONTROL8 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
610  --- CONTROL9 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
611  --- CONTROL10 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
612  --- CONTROL11 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
613  --- end component;
614 
615 --WTF NO CS 20141112 -- signal CONTROLBUS : arr_36(2+num_vio_groups+(num_GTX_groups*num_GTX_per_group) -1 downto 0);
616 --WTF NO CS 20141112 --
617 -- 8 channels
618 
619  ---component chipscope_ila_TopoTXRX_40sys
620  ---PORT (
621  --- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
622  --- CLK : IN STD_LOGIC;
623  --- DATA : IN STD_LOGIC_VECTOR(789 DOWNTO 0);
624  --- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
625  ---end component;
626 
627 --WTF NO CS 20141112 -- component chipscope_ila_TopoTXRX_40sys
628 --WTF NO CS 20141112 -- port (
629 --WTF NO CS 20141112 -- CONTROL : inout std_logic_vector(35 downto 0);
630 --WTF NO CS 20141112 -- CLK : in std_logic;
631 --WTF NO CS 20141112 -- DATA : in std_logic_vector(3109 downto 0);
632 --WTF NO CS 20141112 -- TRIG0 : in std_logic_vector(1 downto 0));
633 --WTF NO CS 20141112 -- end component;
634 --WTF NO CS 20141112 --
635 --WTF NO CS 20141112 -- component chipscope_ila_320sys
636 --WTF NO CS 20141112 -- port (
637 --WTF NO CS 20141112 -- CONTROL : inout std_logic_vector(35 downto 0);
638 --WTF NO CS 20141112 -- CLK : in std_logic;
639 --WTF NO CS 20141112 -- DATA : in std_logic_vector(997 downto 0);
640 --WTF NO CS 20141112 -- TRIG0 : in std_logic_vector(1 downto 0));
641 --WTF NO CS 20141112 -- end component;
642  ---component chipscope_ila_320sys
643  ---PORT (
644  --- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
645  --- CLK : IN STD_LOGIC;
646  --- DATA : IN STD_LOGIC_VECTOR(1109 DOWNTO 0);
647  --- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
648  ---end component;
649 
650 --WTF NO CS 20141112 -- signal DATA_ila_320sys : STD_LOGIC_VECTOR(997 DOWNTO 0);
651 --WTF NO CS 20141112 -- --signal DATA_ila_320sys : STD_LOGIC_VECTOR(1109 DOWNTO 0);
652 --WTF NO CS 20141112 --
653 --WTF NO CS 20141112 --
654 --WTF NO CS 20141112 -- component chipscope_ila_320tx is
655 --WTF NO CS 20141112 -- port (
656 --WTF NO CS 20141112 -- CONTROL : inout std_logic_vector(35 downto 0);
657 --WTF NO CS 20141112 -- CLK : in std_logic;
658 --WTF NO CS 20141112 -- DATA : in std_logic_vector(314 downto 0);
659 --WTF NO CS 20141112 -- TRIG0 : in std_logic_vector(98 downto 0));
660 --WTF NO CS 20141112 -- end component chipscope_ila_320tx;
661 
662  --component chipscope_ila_320tx
663  -- port (
664  -- CONTROL : inout std_logic_vector(35 downto 0);
665  -- CLK : in std_logic;
666  -- DATA : in std_logic_vector(457 downto 0);
667  -- TRIG0 : in std_logic_vector(1 downto 0));
668  --end component;
669 
670 ---component chipscope_ila_320tx
671  ---PORT (
672  --- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
673  --- CLK : IN STD_LOGIC;
674  --- DATA : IN STD_LOGIC_VECTOR(153 DOWNTO 0);
675  --- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
676  ---end component;
677 
678 --WTF NO CS 20141112 -- signal TRIG0_ila_320tx : arr_99(num_GTX_groups-1 DOWNTO 0);
679 --WTF NO CS 20141112 -- signal DATA_ila_320tx : arr_315(num_GTX_groups-1 DOWNTO 0);
680 --WTF NO CS 20141112 -- --signal DATA_ila_320tx : STD_LOGIC_VECTOR(457 DOWNTO 0);
681 --WTF NO CS 20141112 -- --signal DATA_ila_320tx : STD_LOGIC_VECTOR(153 DOWNTO 0);
682 --WTF NO CS 20141112 --
683 --WTF NO CS 20141112 -- component chipscope_ila_320rx
684 --WTF NO CS 20141112 -- PORT (
685 --WTF NO CS 20141112 -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
686 --WTF NO CS 20141112 -- CLK : IN STD_LOGIC;
687 --WTF NO CS 20141112 -- DATA : IN STD_LOGIC_VECTOR(34 DOWNTO 0);
688 --WTF NO CS 20141112 -- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
689 --WTF NO CS 20141112 -- TRIG_OUT : OUT STD_LOGIC);
690 --WTF NO CS 20141112 -- end component;
691 --WTF NO CS 20141112 --
692 --WTF NO CS 20141112 -- signal DATA_ila_320rx : arr_35((num_GTX_per_group*num_GTX_groups)-1 downto 0);
693 --WTF NO CS 20141112 --
694 --WTF NO CS 20141112 -- signal ila_trigger : STD_LOGIC_VECTOR((num_GTX_per_group*num_GTX_groups)-1 downto 0);
695 --WTF NO CS 20141112 --
696 --WTF NO CS 20141112 --
697 --WTF NO CS 20141112 -- component chipscope_TopoTXRX_vio
698 --WTF NO CS 20141112 -- PORT (
699 --WTF NO CS 20141112 -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
700 --WTF NO CS 20141112 -- CLK : IN STD_LOGIC;
701 --WTF NO CS 20141112 -- ASYNC_OUT : OUT STD_LOGIC_VECTOR(143 DOWNTO 0);
702 --WTF NO CS 20141112 -- SYNC_IN : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
703 --WTF NO CS 20141112 -- SYNC_OUT : OUT STD_LOGIC_VECTOR(207 DOWNTO 0));
704 --WTF NO CS 20141112 -- end component;
705 --WTF NO CS 20141112 --
706 --WTF NO CS 20141112 -- signal vio_async_out : std_logic_vector( ((num_vio_groups * 144)-1) DOWNTO 0);
707 --WTF NO CS 20141112 -- signal vio_sync_in : std_logic_vector( ((num_vio_groups * 256)-1) DOWNTO 0);
708 --WTF NO CS 20141112 -- signal vio_sync_out : std_logic_vector( ((num_vio_groups * 208)-1) DOWNTO 0);
709 
710 
711  --1 channel
712  --component chipscope_ila_TopoTXRX_40sys
713  --PORT (
714  -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
715  -- CLK : IN STD_LOGIC;
716  -- DATA : IN STD_LOGIC_VECTOR(94 DOWNTO 0);
717  -- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
718  --end component;
719  --
720  --
721  --component chipscope_ila_320sys
722  --PORT (
723  -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
724  -- CLK : IN STD_LOGIC;
725  -- DATA : IN STD_LOGIC_VECTOR(134 DOWNTO 0);
726  -- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
727  --end component;
728  --
729  --signal DATA_ila_320sys : STD_LOGIC_VECTOR(134 DOWNTO 0);
730  --
731  --component chipscope_ila_320tx
732  --PORT (
733  -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
734  -- CLK : IN STD_LOGIC;
735  -- DATA : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
736  -- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
737  --end component;
738  --
739  --signal DATA_ila_320tx : STD_LOGIC_VECTOR(20 DOWNTO 0);
740  --
741  --component chipscope_ila_320rx
742  --PORT (
743  -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
744  -- CLK : IN STD_LOGIC;
745  -- DATA : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
746  -- TRIG0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
747  -- TRIG_OUT : OUT STD_LOGIC);
748  --end component;
749  --
750  --signal DATA_ila_320rx : STD_LOGIC_VECTOR(35 DOWNTO 0);
751  --
752  --signal ila_trigger : STD_LOGIC;
753  --
754  --component chipscope_TopoTXRX_vio
755  --PORT (
756  -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
757  -- CLK : IN STD_LOGIC;
758  -- ASYNC_OUT : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
759  -- SYNC_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
760  -- SYNC_OUT : OUT STD_LOGIC_VECTOR(25 DOWNTO 0));
761  --end component;
762  --
763  --signal vio_async_out : STD_LOGIC_VECTOR(17 DOWNTO 0);
764  --signal vio_sync_out : STD_LOGIC_VECTOR(25 DOWNTO 0);
765  --signal vio_sync_in : STD_LOGIC_VECTOR(31 DOWNTO 0);
766 
767  signal GTXRXRESET : STD_LOGIC_VECTOR((num_GTX_per_group*num_GTX_groups)-1 downto 0);
768  signal GTXTXRESET : STD_LOGIC_VECTOR((num_GTX_per_group*num_GTX_groups)-1 downto 0);
769 
770  signal ila_trigger_shiftreg : arr_20((num_GTX_per_group*num_GTX_groups)-1 downto 0);
771  signal ila_trigger_held20 : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
772  signal ila_trigger_held20_all : std_logic;
773 
774 begin
775 
776 --WTF NO CS 20141112 --
777 --WTF NO CS 20141112 -- ila_trigger<=(others=>'0');
778  --for the purpose of debugging in ML605
779  --TXUSRCLK2_IN_bufferedG_out<=TXUSRCLK2_IN_bufferedG;
780 
781 
782  vme_local_switch_inst: entity work.vme_local_switch
783  port map (
784  data_vme_up => data_vme_out,
785  data_vme_from_below => data_vme_from_below,
786  bus_drive_up => bus_drive,
787  bus_drive_from_below => bus_drive_from_below);
788 
789 
790  tied_to_ground_i <= '0';
791  tied_to_ground_vec_i <= x"0000000000000000";
792  tied_to_vcc_i <= '1';
793  --tied_to_vcc_vec_i <= x"ff";
794 
795  --chipscope_icon_1: chipscope_icon_Topo_Data_TX
796  -- port map (
797  -- CONTROL0 => CONTROL0);
798  --
799  --chipscope_ila_Topo_Data_TX_inst: chipscope_ila_Topo_Data_TX
800  -- port map (
801  -- CONTROL => CONTROL0,
802  -- CLK => RXUSRCLK2_IN_bufferedR(0),
803  -- DATA(0) => GTXTXRESET_IN,
804  -- DATA(1) => GTXRXRESET_IN,
805  -- DATA(2) => TXRESETDONE_OUT(0),
806  -- DATA(3) => RXRESETDONE_OUT(0),
807  -- DATA(4) => GTX_TX_READY_OUT_sig,
808  -- DATA(5) => GTX_RX_READY_OUT_sig,
809  -- DATA(7 downto 6) => TXCHARISK_IN(0),
810  -- DATA(9 downto 8) => RXCHARISK_OUT(0),
811  -- DATA(11 downto 10) => RXCHARISCOMMA_OUT(0),
812  -- DATA(12) => RXENMCOMMAALIGN_IN(0),
813  -- DATA(13) => RXENPCOMMAALIGN_IN(0),
814  -- DATA(14) => RXBYTEREALIGN_OUT(0),
815  -- DATA(30 downto 15) => TXDATA_IN(0),
816  -- DATA(46 downto 31) => RXDATA_OUT(0),
817  -- TRIG0(0) => GTXTXRESET_IN,
818  -- TRIG0(1) => GTXRXRESET_IN,
819  -- TRIG0(2) => TXRESETDONE_OUT(0),
820  -- TRIG0(3) => RXRESETDONE_OUT(0),
821  -- TRIG0(4) => GTX_TX_READY_OUT_sig,
822  -- TRIG0(5) => GTX_RX_READY_OUT_sig,
823  -- TRIG0(7 downto 6) => TXCHARISK_IN(0),
824  -- TRIG0(9 downto 8) => RXCHARISK_OUT(0),
825  -- TRIG0(11 downto 10)=> RXCHARISCOMMA_OUT(0),
826  -- TRIG0(12) => RXENMCOMMAALIGN_IN(0),
827  -- TRIG0(13) => RXENPCOMMAALIGN_IN(0),
828  -- TRIG0(14) => RXBYTEREALIGN_OUT(0),
829  -- TRIG0(15) => RXPLLLKDET_OUT(0),
830  -- TRIG_OUT => TRIG_OUT
831  -- );
832 
833 --WTF NO CS 20141112 -- gen_Topo_TX_chipscope_icon_ila_vio: if gen_Topo_TX_chipscope='1' generate
834 --WTF NO CS 20141112 --
835 --WTF NO CS 20141112 -- gen_icon_RX_on: if gen_RX='1' generate
836 --WTF NO CS 20141112 -- -- chipscope_icon_TopoTXRX_u3_15_inst: chipscope_icon_TopoTXRX_u3_15
837 --WTF NO CS 20141112 -- -- port map (
838 --WTF NO CS 20141112 -- -- CONTROL0 => CONTROLBUS(0),
839 --WTF NO CS 20141112 -- -- CONTROL1 => CONTROLBUS(1),
840 --WTF NO CS 20141112 -- -- CONTROL2 => CONTROLBUS(2),
841 --WTF NO CS 20141112 -- -- CONTROL3 => CONTROLBUS(3),
842 --WTF NO CS 20141112 -- -- CONTROL4 => CONTROLBUS(4),
843 --WTF NO CS 20141112 -- -- CONTROL5 => CONTROLBUS(5),
844 --WTF NO CS 20141112 -- -- CONTROL6 => CONTROLBUS(6),
845 --WTF NO CS 20141112 -- -- CONTROL7 => CONTROLBUS(7),
846 --WTF NO CS 20141112 -- -- CONTROL8 => CONTROLBUS(8),
847 --WTF NO CS 20141112 -- -- CONTROL9 => CONTROLBUS(9),
848 --WTF NO CS 20141112 -- -- CONTROL10 => CONTROLBUS(10),
849 --WTF NO CS 20141112 -- -- CONTROL11 => CONTROLBUS(11),
850 --WTF NO CS 20141112 -- -- CONTROL12 => CONTROLBUS(12),
851 --WTF NO CS 20141112 -- -- CONTROL13 => CONTROLBUS(13),
852 --WTF NO CS 20141112 -- -- CONTROL14 => CONTROLBUS(14));
853 --WTF NO CS 20141112 -- --
854 --WTF NO CS 20141112 -- --
855 --WTF NO CS 20141112 --
856 --WTF NO CS 20141112 -- -- chipscope_icon_TopoTXRX_u2_15_inst: chipscope_icon_TopoTXRX_u2_15
857 --WTF NO CS 20141112 -- -- port map (
858 --WTF NO CS 20141112 -- -- CONTROL0 => CONTROLBUS(15),
859 --WTF NO CS 20141112 -- -- CONTROL1 => CONTROLBUS(16),
860 --WTF NO CS 20141112 -- -- CONTROL2 => CONTROLBUS(17),
861 --WTF NO CS 20141112 -- -- CONTROL3 => CONTROLBUS(18),
862 --WTF NO CS 20141112 -- -- CONTROL4 => CONTROLBUS(19),
863 --WTF NO CS 20141112 -- -- CONTROL5 => CONTROLBUS(20),
864 --WTF NO CS 20141112 -- -- CONTROL6 => CONTROLBUS(21),
865 --WTF NO CS 20141112 -- -- CONTROL7 => CONTROLBUS(22),
866 --WTF NO CS 20141112 -- -- CONTROL8 => CONTROLBUS(23),
867 --WTF NO CS 20141112 -- -- CONTROL9 => CONTROLBUS(24),
868 --WTF NO CS 20141112 -- -- CONTROL10 => CONTROLBUS(25),
869 --WTF NO CS 20141112 -- -- CONTROL11 => CONTROLBUS(26),
870 --WTF NO CS 20141112 -- -- CONTROL12 => CONTROLBUS(27),
871 --WTF NO CS 20141112 -- -- CONTROL13 => CONTROLBUS(28),
872 --WTF NO CS 20141112 -- -- CONTROL14 => CONTROLBUS(29));
873 --WTF NO CS 20141112 --
874 --WTF NO CS 20141112 -- -- chipscope_icon_TopoTXRX_u4_14_inst: chipscope_icon_TopoTXRX_u4_14
875 --WTF NO CS 20141112 -- -- port map (
876 --WTF NO CS 20141112 -- -- CONTROL0 => CONTROLBUS(15),
877 --WTF NO CS 20141112 -- -- CONTROL1 => CONTROLBUS(16),
878 --WTF NO CS 20141112 -- -- CONTROL2 => CONTROLBUS(17),
879 --WTF NO CS 20141112 -- -- CONTROL3 => CONTROLBUS(18),
880 --WTF NO CS 20141112 -- -- CONTROL4 => CONTROLBUS(19),
881 --WTF NO CS 20141112 -- -- CONTROL5 => CONTROLBUS(20),
882 --WTF NO CS 20141112 -- -- CONTROL6 => CONTROLBUS(21),
883 --WTF NO CS 20141112 -- -- CONTROL7 => CONTROLBUS(22),
884 --WTF NO CS 20141112 -- -- CONTROL8 => CONTROLBUS(23),
885 --WTF NO CS 20141112 -- -- CONTROL9 => CONTROLBUS(24),
886 --WTF NO CS 20141112 -- -- CONTROL10 => CONTROLBUS(25),
887 --WTF NO CS 20141112 -- -- CONTROL11 => CONTROLBUS(26),
888 --WTF NO CS 20141112 -- -- CONTROL12 => CONTROLBUS(27),
889 --WTF NO CS 20141112 -- -- CONTROL13 => CONTROLBUS(28));
890 --WTF NO CS 20141112 --
891 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- chipscope_icon_TopoTXRX_u3_6_inst: chipscope_icon_TopoTXRX_u3_6
892 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
893 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL0 => CONTROLBUS(0),
894 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL1 => CONTROLBUS(1),
895 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL2 => CONTROLBUS(2),
896 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL3 => CONTROLBUS(3),
897 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL4 => CONTROLBUS(4),
898 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL5 => CONTROLBUS(5));
899 --WTF NO CS 20141112 --
900 --WTF NO CS 20141112 --
901 --WTF NO CS 20141112 -- end generate gen_icon_RX_on;
902 --WTF NO CS 20141112 --
903 --WTF NO CS 20141112 -- gen_icon_RX_off: if gen_RX='0' generate
904 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- chipscope_icon_TopoTXRX_u3_6_inst: chipscope_icon_TopoTXRX_u3_6
905 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
906 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL0 => CONTROLBUS(0),
907 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL1 => CONTROLBUS(1),
908 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL2 => CONTROLBUS(2),
909 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL3 => CONTROLBUS(3),
910 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL4 => CONTROLBUS(4),
911 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL5 => CONTROLBUS(5));
912 --WTF NO CS 20141112 -- end generate gen_icon_RX_off;
913 --WTF NO CS 20141112 --
914 --WTF NO CS 20141112 --
915 --WTF NO CS 20141112 --
916 --WTF NO CS 20141112 -- --- chipscope_icon_TopoTXRX_inst: chipscope_icon_TopoTXRX
917 --WTF NO CS 20141112 -- --- port map (
918 --WTF NO CS 20141112 -- --- CONTROL0=> CONTROLBUS(0),
919 --WTF NO CS 20141112 -- --- CONTROL1=> CONTROLBUS(1),
920 --WTF NO CS 20141112 -- --- CONTROL2=> CONTROLBUS(2),
921 --WTF NO CS 20141112 -- --- CONTROL3=> CONTROLBUS(3),
922 --WTF NO CS 20141112 -- --- CONTROL4=> CONTROLBUS(4),
923 --WTF NO CS 20141112 -- --- CONTROL5=> CONTROLBUS(5),
924 --WTF NO CS 20141112 -- --- CONTROL6=> CONTROLBUS(6),
925 --WTF NO CS 20141112 -- --- CONTROL7=> CONTROLBUS(7),
926 --WTF NO CS 20141112 -- --- CONTROL8=> CONTROLBUS(8),
927 --WTF NO CS 20141112 -- --- CONTROL9=> CONTROLBUS(9),
928 --WTF NO CS 20141112 -- --- CONTROL10=> CONTROLBUS(10),
929 --WTF NO CS 20141112 -- --- CONTROL11=> CONTROLBUS(11));
930 --WTF NO CS 20141112 --
931 --WTF NO CS 20141112 --
932 --WTF NO CS 20141112 -- -- 24 channel
933 --WTF NO CS 20141112 -- chipscope_ila_TopoTXRX_40sys_inst: chipscope_ila_TopoTXRX_40sys
934 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
935 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL => CONTROLBUS(0),
936 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CLK => clk40,
937 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA(0) => ila_trigger_held20_all,--RX_ERROR_OUT_sig,
938 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA(1) => GTX_RX_READY_OUT_sig,
939 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA(13 downto 2) => BCID,
940 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA(37 downto 14) => send_align,
941 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA(3109 downto 38) => indata,
942 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0(0) => ila_trigger_held20_all,
943 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0(1) => GTX_RX_READY_OUT_sig);
944 --WTF NO CS 20141112 --
945 --WTF NO CS 20141112 -- --1 channel
946 --WTF NO CS 20141112 -- --chipscope_ila_TopoTXRX_40sys_inst: chipscope_ila_TopoTXRX_40sys
947 --WTF NO CS 20141112 -- -- port map (
948 --WTF NO CS 20141112 -- -- CONTROL => CONTROL0,
949 --WTF NO CS 20141112 -- -- CLK => clk40,
950 --WTF NO CS 20141112 -- -- DATA(0) => RX_ERROR_OUT_sig,
951 --WTF NO CS 20141112 -- -- DATA(1) => GTX_RX_READY_OUT_sig,
952 --WTF NO CS 20141112 -- -- DATA(13 downto 2) => BCID,
953 --WTF NO CS 20141112 -- -- DATA(14 downto 14) => send_align,
954 --WTF NO CS 20141112 -- -- DATA(94 downto 15) => indata,
955 --WTF NO CS 20141112 -- -- TRIG0(0) => ila_trigger_held20,
956 --WTF NO CS 20141112 -- -- TRIG0(1) => GTX_RX_READY_OUT_sig);
957 --WTF NO CS 20141112 --
958 --WTF NO CS 20141112 --
959 --WTF NO CS 20141112 --
960 --WTF NO CS 20141112 -- --chipscope_ila_320sys_inst: chipscope_ila_320sys
961 --WTF NO CS 20141112 -- -- port map (
962 --WTF NO CS 20141112 -- -- CONTROL => CONTROLBUS(1),
963 --WTF NO CS 20141112 -- -- CLK => clk320,
964 --WTF NO CS 20141112 -- -- DATA => DATA_ila_320sys,
965 --WTF NO CS 20141112 -- -- TRIG0(0) => ila_trigger_held20_all,
966 --WTF NO CS 20141112 -- -- TRIG0(1) => GTX_RX_READY_OUT_sig);
967 --WTF NO CS 20141112 --
968 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- ila_320tx_gen_grp: for group_i in 0 to num_GTX_groups-1 generate
969 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
970 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- chipscope_ila_320tx_inst: chipscope_ila_320tx
971 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
972 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL => CONTROLBUS(1+group_i),
973 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CLK => TXUSRCLK2_IN_bufferedG(group_i),
974 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA => DATA_ila_320tx(group_i),
975 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0 => TRIG0_ila_320tx(group_i));
976 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- --TRIG0(0) => ila_trigger_held20_all or ext_trigger,
977 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- --TRIG0(1) => GTX_RX_READY_OUT_sig);
978 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
979 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(0)<=ext_trigger;
980 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(1)<=set_mem_ctr_o(group_i);
981 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(2)<=c_tx_sync_done_grp_r_held20(group_i);
982 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
983 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(0)<=ext_trigger;
984 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(1)<=set_mem_ctr_o(group_i);
985 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(2)<=c_tx_sync_done_grp_r_held20(group_i);
986 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
987 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
988 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- ila_320tx_gen_gtx: for gtx_i in 0 to num_GTX_per_group-1 generate
989 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
990 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +3) <= TXENPMAPHASEALIGN_IN(group_i*num_GTX_per_group+gtx_i);
991 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +4) <= TXPMASETPHASE_IN(group_i*num_GTX_per_group+gtx_i);
992 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +5) <= TXDLYALIGNDISABLE_IN(group_i*num_GTX_per_group+gtx_i);
993 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +6) <= TXDLYALIGNRESET_IN(group_i*num_GTX_per_group+gtx_i);
994 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +7) <= tx_sync_done(group_i*num_GTX_per_group+gtx_i);
995 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +8) <= reset_tx_sync(group_i*num_GTX_per_group+gtx_i);
996 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +9) <= TXPLLLKDET_OUT((group_i*num_GTX_per_group)+gtx_i);
997 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 +10) <= TXRESETDONE_OUT((group_i*num_GTX_per_group)+gtx_i);
998 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320tx(group_i)(gtx_i*26 + 11 + 17 downto gtx_i*26 + 11) <= fifo_dout(18*(gtx_i+1)-1 downto 18*gtx_i);
999 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1000 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +3) <= TXENPMAPHASEALIGN_IN(group_i*num_GTX_per_group+gtx_i);
1001 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +4) <= TXPMASETPHASE_IN(group_i*num_GTX_per_group+gtx_i);
1002 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +5) <= TXDLYALIGNDISABLE_IN(group_i*num_GTX_per_group+gtx_i);
1003 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +6) <= TXDLYALIGNRESET_IN(group_i*num_GTX_per_group+gtx_i);
1004 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +7) <= tx_sync_done(group_i*num_GTX_per_group+gtx_i);
1005 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +8) <= reset_tx_sync(group_i*num_GTX_per_group+gtx_i);
1006 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +9) <= TXPLLLKDET_OUT((group_i*num_GTX_per_group)+gtx_i);
1007 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- TRIG0_ila_320tx(group_i)(gtx_i*8 +10) <= TXRESETDONE_OUT((group_i*num_GTX_per_group)+gtx_i);
1008 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1009 --WTF NO CS 20141112 --
1010 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end generate ila_320tx_gen_gtx;
1011 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1012 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end generate ila_320tx_gen_grp;
1013 --WTF NO CS 20141112 --
1014 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- vio_gen: for vio_i in 0 to num_vio_groups-1 generate
1015 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- chipscope_TopoTXRX_vio_inst: chipscope_TopoTXRX_vio
1016 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
1017 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CONTROL => CONTROLBUS(3+vio_i),
1018 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- CLK => clk40,--RXUSRCLK2_IN(vio_i*(num_GTX_groups*num_GTX_per_group)/num_vio_groups),
1019 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- ASYNC_OUT => vio_async_out( (144*(vio_i+1))-1 downto (144*vio_i) ),
1020 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- SYNC_OUT => vio_sync_out( (208*(vio_i+1))-1 downto (208*vio_i) ),
1021 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- SYNC_IN => vio_sync_in( (256*(vio_i+1))-1 downto (256*vio_i) ) );
1022 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end generate vio_gen;
1023 --WTF NO CS 20141112 --
1024 --WTF NO CS 20141112 --
1025 --WTF NO CS 20141112 -- --we ensure that the trigger pulse generated is at least 20 cycles (320MHz RX)
1026 --WTF NO CS 20141112 -- --long so that the other cores have to pick it up
1027 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- ila_trigger_held20_gen: for gtx_i in 0 to num_GTX_groups*num_GTX_per_group - 1 generate
1028 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1029 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- ila_trigger_shiftreg(gtx_i)(0)<=ila_trigger(gtx_i);
1030 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- shiftreggen_ila_trigger: for bit_i in 19 downto 1 generate
1031 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- process(RXUSRCLK2_IN(gtx_i))
1032 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- begin
1033 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- if rising_edge(RXUSRCLK2_IN(gtx_i)) then
1034 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- ila_trigger_shiftreg(gtx_i)(bit_i)<=ila_trigger_shiftreg(gtx_i)(bit_i-1);
1035 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end if;
1036 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end process;
1037 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end generate shiftreggen_ila_trigger;
1038 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1039 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- or_all_ila_trigger_shiftreg: or_all
1040 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- generic map (
1041 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- numbits => 20)
1042 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
1043 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA => ila_trigger_shiftreg(gtx_i),
1044 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- or_all => ila_trigger_held20(gtx_i)
1045 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- );
1046 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1047 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- end generate ila_trigger_held20_gen;
1048 --WTF NO CS 20141112 ----WTF NO CS 20141112 --
1049 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- or_all_ila_trigger_held20: or_all
1050 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- generic map (
1051 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- numbits => num_GTX_per_group*num_GTX_groups)
1052 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- port map (
1053 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA => ila_trigger_held20,
1054 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- or_all => ila_trigger_held20_all
1055 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- );
1056 --WTF NO CS 20141112 --
1057 --WTF NO CS 20141112 --
1058 --WTF NO CS 20141112 ---- ila_trigger_held20_out<=ila_trigger_held20_all;
1059 --WTF NO CS 20141112 --
1060 --WTF NO CS 20141112 --
1061 --WTF NO CS 20141112 -- --DATA_ila_320sys(0)<=ila_trigger_held20_all;--RX_ERROR_OUT_sig;
1062 --WTF NO CS 20141112 -- --DATA_ila_320sys(1)<=GTX_RX_READY_OUT_sig;
1063 --WTF NO CS 20141112 -- --DATA_ila_320sys(13 downto 2) <= BCID;
1064 --WTF NO CS 20141112 --
1065 --WTF NO CS 20141112 -- -- DATA_ila_320tx(0)<=ila_trigger_held20_all or ext_trigger;--RX_ERROR_OUT_sig;
1066 --WTF NO CS 20141112 -- -- DATA_ila_320tx(1)<=GTX_RX_READY_OUT_sig;
1067 --WTF NO CS 20141112 --
1068 --WTF NO CS 20141112 --
1069 --WTF NO CS 20141112 -- DATA_ila_RX_gen: for gtx_i in 0 to num_GTX_groups*num_GTX_per_group - 1 generate
1070 --WTF NO CS 20141112 --
1071 --WTF NO CS 20141112 --
1072 --WTF NO CS 20141112 --
1073 --WTF NO CS 20141112 --
1074 --WTF NO CS 20141112 -- --DATA_ila_320sys(16 + gtx_i*41 downto 14 + gtx_i*41) <= std_logic_vector(subtick_counter(gtx_i));
1075 --WTF NO CS 20141112 -- --DATA_ila_320sys(17 + gtx_i*41) <= send_align(gtx_i);
1076 --WTF NO CS 20141112 -- ----DATA_ila_320sys(12+85+16 + gtx_i*41 downto 12+6 + gtx_i*41) <= time_multiplex_data_in(gtx_i);
1077 --WTF NO CS 20141112 -- --DATA_ila_320sys(35 + gtx_i*41 downto 18 + gtx_i*41) <= time_multiplex_data_out(gtx_i);
1078 --WTF NO CS 20141112 -- --DATA_ila_320sys(53 + gtx_i*41 downto 36 + gtx_i*41) <= time_multiplex_data_out_CRC(gtx_i);
1079 --WTF NO CS 20141112 -- --DATA_ila_320sys(54 + gtx_i*41) <= set_mem_ctr_i(0);
1080 --WTF NO CS 20141112 --
1081 --WTF NO CS 20141112 --
1082 --WTF NO CS 20141112 -- --DATA_ila_320tx(19 + gtx_i*19 downto 2 + gtx_i*19) <= fifo_dout(18*(gtx_i+1)-1 downto 18*gtx_i);
1083 --WTF NO CS 20141112 -- --DATA_ila_320tx(20 + gtx_i*19) <= set_mem_ctr_o(0);
1084 --WTF NO CS 20141112 --
1085 --WTF NO CS 20141112 --
1086 --WTF NO CS 20141112 --
1087 --WTF NO CS 20141112 -- ila_RX_gen: if gen_RX='1' generate
1088 --WTF NO CS 20141112 --
1089 --WTF NO CS 20141112 -- -- chipscope_ila_320rx_inst: chipscope_ila_320rx
1090 --WTF NO CS 20141112 -- -- port map (
1091 --WTF NO CS 20141112 -- -- CONTROL => CONTROLBUS(3+num_vio_groups+gtx_i),
1092 --WTF NO CS 20141112 -- -- CLK => RXUSRCLK2_IN(gtx_i),
1093 --WTF NO CS 20141112 -- -- DATA => DATA_ila_320rx(gtx_i),
1094 --WTF NO CS 20141112 -- -- TRIG0(0) => rx_error_any(gtx_i),
1095 --WTF NO CS 20141112 -- -- TRIG0(1) => RXBYTEREALIGN_OUT(gtx_i),
1096 --WTF NO CS 20141112 -- -- TRIG_OUT => ila_trigger(gtx_i));
1097 --WTF NO CS 20141112 --
1098 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(0) <=rx_error_any(gtx_i);--rx_error_eventrealign(gtx_i) or rx_error_crc(gtx_i) or RXNOTINTABLE_OUT(gtx_i)(0) or RXNOTINTABLE_OUT(gtx_i)(1) or RXDISPERR_OUT(gtx_i)(0) or RXDISPERR_OUT(gtx_i)(1) or RXBYTEREALIGN_OUT(gtx_i); --rx_error_any(gtx_i);
1099 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(1) <= ila_trigger(gtx_i);
1100 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(2) <= ila_trigger_held20(gtx_i);
1101 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(3) <= RXBYTEISALIGNED_OUT_r(gtx_i);
1102 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(5 downto 4) <= RXNOTINTABLE_OUT(gtx_i);
1103 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(6) <= RXBYTEREALIGN_OUT(gtx_i);
1104 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(8 downto 7) <= RXDISPERR_OUT(gtx_i);
1105 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(10 downto 9) <= RXCHARISK_OUT(gtx_i);
1106 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(12 downto 11) <= RXCHARISCOMMA_OUT(gtx_i);
1107 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(13) <= rx_error_crc(gtx_i);
1108 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(14) <= rx_error_eventrealign(gtx_i);
1109 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(15) <= subtick_counter_rx_started(gtx_i);
1110 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(18 downto 16) <= std_logic_vector(subtick_counter_rx(gtx_i));
1111 --WTF NO CS 20141112 ----WTF NO CS 20141112 -- DATA_ila_320rx(gtx_i)(34 downto 19) <= RXDATA_OUT(gtx_i);
1112 --WTF NO CS 20141112 --
1113 --WTF NO CS 20141112 -- end generate ila_RX_gen;
1114 --WTF NO CS 20141112 --
1115 --WTF NO CS 20141112 -- end generate DATA_ila_RX_gen;
1116 --WTF NO CS 20141112 --
1117 --WTF NO CS 20141112 -- end generate gen_Topo_TX_chipscope_icon_ila_vio;
1118 
1119 
1120  wait_for_cdr_gen: if gen_RX='1' generate
1121  wait_for_cdr_gen_gtx: for gtx_i in (num_GTX_groups*num_GTX_per_group-1) downto 0 generate
1122  long_counter_next(gtx_i)<=long_counter(gtx_i)+to_unsigned(1,long_counter(gtx_i)'length);
1123  process(RXUSRCLK2_IN(gtx_i),RXRESETDONE_OUT(gtx_i))
1124  begin
1125  if RXRESETDONE_OUT(gtx_i)='0' then
1126  wait_done(gtx_i)<='0';
1127  long_counter(gtx_i)<=(others=>'0');
1128  else
1129  if rising_edge(RXUSRCLK2_IN(gtx_i)) then
1130  long_counter(gtx_i)<=long_counter_next(gtx_i);
1131  if long_counter(gtx_i)(long_counter(gtx_i)'length -1)='1' then
1132  wait_done(gtx_i)<='1';
1133  end if;
1134  end if;
1135  end if;
1136  end process;
1137  end generate wait_for_cdr_gen_gtx;
1138  end generate wait_for_cdr_gen;
1139 
1140  --just a hack for now
1141  txdatagen_grp: for group_i in (num_GTX_groups-1) downto 0 generate
1142 
1143  short_counter_next(group_i)<=short_counter(group_i)+to_unsigned(1,short_counter(group_i)'length);
1144  --process(TXUSRCLK2_IN_bufferedG(group_i),GTX_TX_READY_OUT_sig) --tx_sync_done_grp_r(group_i)) --GTX_TX_READY_OUT_sig)
1145  --begin
1146  -- if GTX_TX_READY_OUT_sig='0' then --tx_sync_done_grp_r(group_i)='0' then --GTX_TX_READY_OUT_sig='0' then
1147  -- short_counter(group_i)<=(others=>'0');
1148  -- else
1149  -- if rising_edge(TXUSRCLK2_IN_bufferedG(group_i)) then
1150  -- short_counter(group_i)<=short_counter_next(group_i);
1151  -- end if;
1152  -- end if;
1153  --end process;
1154 
1155  --process(TXUSRCLK2_IN_bufferedG(group_i),tx_sync_done_grp_r(group_i))
1156  ----GTX_TX_READY_OUT_sig) --oops wrong sensitivity list
1157  --begin
1158  -- if rising_edge(TXUSRCLK2_IN_bufferedG(group_i)) then
1159  -- if tx_sync_done_grp_r(group_i)='0' then --GTX_TX_READY_OUT_sig='0' then
1160  -- short_counter(group_i)<=(others=>'0');
1161  -- else
1162  -- short_counter(group_i)<=short_counter_next(group_i);
1163  -- end if;
1164  -- end if;
1165  --end process;
1166 
1167 
1168  --we ensure that the reset pulse generated is at least 20 cycles (320 MHz)
1169  --long
1170  c_tx_sync_done_grp_shiftreg(group_i)(0)<=c_tx_sync_done_grp_r(group_i);
1171  shiftreggen_c_tx_sync_done_grp: for bit_i in 19 downto 1 generate
1172  process(TXUSRCLK2_IN_bufferedG(group_i))
1173  begin
1174  if rising_edge(TXUSRCLK2_IN_bufferedG(group_i)) then
1175  c_tx_sync_done_grp_shiftreg(group_i)(bit_i)<=c_tx_sync_done_grp_shiftreg(group_i)(bit_i-1);
1176  end if;
1177  end process;
1178  end generate shiftreggen_c_tx_sync_done_grp;
1179 
1180  or_all_c_tx_sync_done_grp_shiftreg: or_all
1181  generic map (
1182  numbits => 20)
1183  port map (
1184  DATA => c_tx_sync_done_grp_shiftreg (group_i),
1185  or_all => c_tx_sync_done_grp_r_held20 (group_i)
1186  );
1187 
1188  process(TXUSRCLK2_IN_bufferedG(group_i))
1189  begin
1190  if rising_edge(TXUSRCLK2_IN_bufferedG(group_i)) then
1191  c_tx_sync_done_grp_r_held20_r(group_i)<=c_tx_sync_done_grp_r_held20(group_i);
1192  end if;
1193  end process;
1194 
1195  -- --this delays setting of wr_en 4 clock (clk40) cycles after the reset is cleared
1196  -- process(clk40, c_tx_sync_done_grp_r_held20(group_i))
1197  -- begin
1198  -- if c_tx_sync_done_grp_r_held20(group_i)='1' then
1199  -- wr_en(group_i)<='0';
1200  -- wr_en_delay(group_i)<=(others => '0');
1201  -- else
1202  -- if rising_edge(clk40) then
1203  -- wr_en_delay(group_i)(0)<='1';
1204  -- wr_en_delay(group_i)(1)<=wr_en_delay(group_i)(0);
1205  -- wr_en_delay(group_i)(2)<=wr_en_delay(group_i)(1);
1206  -- wr_en_delay(group_i)(3)<=wr_en_delay(group_i)(2);
1207  -- wr_en(group_i)<=wr_en_delay(group_i)(3);
1208  -- end if;
1209  -- end if;
1210  -- end process;
1211 
1212  mini_fifo_synchroniser_i: mini_fifo_synchroniser
1213  port map (
1214  set_mem_ctr_i_out => set_mem_ctr_i(group_i),
1215  set_mem_ctr_o_out => set_mem_ctr_o(group_i),
1216  clk_i_dom => clk320,
1217  clk_o_dom => TXUSRCLK2_IN_bufferedG(group_i),
1218  set => c_tx_sync_done_grp_r_held20_r (group_i));
1219 
1220  txdatagen_fifo: for fifo_i in (num_fifos_per_group-1) downto 0 generate
1221 
1222  time_multiplex_data_in(group_i*num_fifos_per_group+fifo_i)<=
1223  indata((group_i*num_fifos_per_group+fifo_i+1)*TX_time_multiplex_indata_length - 1
1224  downto
1225  (group_i*num_fifos_per_group+fifo_i)*TX_time_multiplex_indata_length);
1226 
1227  time_multiplex_i: time_multiplex_8to1
1228  port map (
1229  DATA_in => time_multiplex_data_in(group_i*num_fifos_per_group+fifo_i),
1230  send_align => send_align(group_i*num_fifos_per_group+fifo_i),
1231  BCID => BCID,
1232  DATA_out => time_multiplex_data_out (group_i*num_fifos_per_group+fifo_i),
1233  subtick_counter_out => subtick_counter(group_i*num_fifos_per_group+fifo_i),
1234  clk_slow => clk40,
1235  clk_fast => clk320 ,
1236  pll_locked => pll_locked);
1237 
1238  CRC_CALC_inst: CRC_CALC
1239  port map (
1240  DATA_in => time_multiplex_data_out (group_i*num_fifos_per_group+fifo_i),
1241  DATA_out => time_multiplex_data_out_CRC (group_i*num_fifos_per_group+fifo_i),
1242  clk => clk320,
1243  subtick_counter => subtick_counter(group_i*num_fifos_per_group+fifo_i) );
1244 
1245  mini_fifo_i: mini_fifo
1246  port map (
1247  DATA_in => time_multiplex_data_out_CRC (group_i*num_fifos_per_group+fifo_i),
1248  DATA_out => fifo_dout((group_i*num_fifos_per_group+fifo_i+1)*TX_fifo_odata_length - 1
1249  downto
1250  (group_i*num_fifos_per_group+fifo_i)*TX_fifo_odata_length),
1251  clk_i_dom => clk320 ,
1252  clk_o_dom => TXUSRCLK2_IN_bufferedG(group_i),
1253  set_mem_ctr_i => set_mem_ctr_i(group_i),
1254  set_mem_ctr_o => set_mem_ctr_o(group_i));
1255 
1256  --- fifo_dout((group_i*num_fifos_per_group+fifo_i+1)*TX_fifo_odata_length - 1
1257  --- downto
1258  --- (group_i*num_fifos_per_group+fifo_i)*TX_fifo_odata_length)
1259  --- <= time_multiplex_data_out(group_i*num_fifos_per_group+fifo_i);
1260 
1261 -- rd_en(group_i*num_fifos_per_group+fifo_i)<=not empty(group_i*num_fifos_per_group+fifo_i);
1262 --
1263 -- TopoTX_fifo_i : TopoTX_fifo
1264 -- PORT MAP (
1265 -- rst => c_tx_sync_done_grp_r_held20(group_i),
1266 -- wr_clk => clk320,
1267 -- rd_clk => TXUSRCLK2_IN_bufferedG(group_i),
1268 -- --din => indata(group_i*num_GTX_per_group * (GTX_data_word_width+2) * 8 + (fifo_i+1)*(TX_indata_length/(num_fifos_per_group*num_GTX_groups)) - 1
1269 -- -- downto
1270 -- -- group_i*num_GTX_per_group * (GTX_data_word_width+2) * 8 + fifo_i*(TX_indata_length/(num_fifos_per_group*num_GTX_groups)) )
1271 -- --
1272 -- din => time_multiplex_data_out(group_i*num_fifos_per_group+fifo_i),
1273 -- wr_en => wr_en(group_i),
1274 -- rd_en => rd_en(group_i*num_fifos_per_group+fifo_i),
1275 -- dout => fifo_dout((group_i*num_fifos_per_group+fifo_i+1)*TX_fifo_odata_length - 1
1276 -- downto
1277 -- (group_i*num_fifos_per_group+fifo_i)*TX_fifo_odata_length),
1278 -- full => full(group_i*num_fifos_per_group+fifo_i),
1279 -- --almost_full => almost_full(group_i*num_fifos_per_group+fifo_i),
1280 -- --overflow => overflow(group_i*num_fifos_per_group+fifo_i),
1281 -- empty => empty(group_i*num_fifos_per_group+fifo_i)
1282 -- --almost_empty => almost_empty(group_i*num_fifos_per_group+fifo_i),
1283 -- --underflow => underflow(group_i*num_fifos_per_group+fifo_i),
1284 -- --rd_data_count => rd_data_count(group_i*num_fifos_per_group+fifo_i),
1285 -- --wr_data_count => wr_data_count(group_i*num_fifos_per_group+fifo_i)
1286 -- );
1287 --
1288  txdatagen_gtx: for gtx_i in (num_GTX_per_fifo-1) downto 0 generate
1289 
1290  --TXDATA_IN((group_i*num_GTX_per_group)+gtx_i)<="0000000010111100";
1291  --TXCHARISK_IN((group_i*num_GTX_per_group)+gtx_i) <= "01";
1292  TXDATA_IN(((group_i*num_fifos_per_group)+fifo_i)*num_GTX_per_fifo+gtx_i)<=
1293  fifo_dout( (((group_i*num_fifos_per_group)+fifo_i)*num_GTX_per_fifo+gtx_i+1)*(GTX_data_word_width+2)-1-2
1294  downto
1295  (((group_i*num_fifos_per_group)+fifo_i)*num_GTX_per_fifo+gtx_i)*(GTX_data_word_width+2) );
1296  TXCHARISK_IN(((group_i*num_fifos_per_group)+fifo_i)*num_GTX_per_fifo+gtx_i)<=
1297  fifo_dout( (((group_i*num_fifos_per_group)+fifo_i)*num_GTX_per_fifo+gtx_i+1)*(GTX_data_word_width+2)-1
1298  downto
1299  (((group_i*num_fifos_per_group)+fifo_i)*num_GTX_per_fifo+gtx_i)*(GTX_data_word_width+2)+GTX_data_word_width );
1300 
1301 
1302  end generate txdatagen_gtx;
1303  end generate txdatagen_fifo;
1304  end generate txdatagen_grp;
1305 
1306  txparamgen_grp: for group_i in (num_GTX_groups-1) downto 0 generate
1307  txparamgen_gtx: for gtx_i in (num_GTX_per_group-1) downto 0 generate
1308  --TXPREEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i) <= "0000";
1309  --TXPOSTEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i) <= "00001";
1310  --TXDIFFCTRL_IN((group_i*num_GTX_per_group)+gtx_i) <= "1010";
1311 
1312  --TXPREEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i) <= "0000";
1313  --TXPOSTEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i) <= "00000";
1314  --TXDIFFCTRL_IN((group_i*num_GTX_per_group)+gtx_i) <= "1010";
1315 
1316  TXDIFFCTRL_IN((group_i*num_GTX_per_group)+gtx_i) <= "0110"; --WTF NO CS 20141112 --vio_async_out(3 + 18*((group_i*num_GTX_per_group)+gtx_i) downto 0 + 18*((group_i*num_GTX_per_group)+gtx_i) );
1317  TXPREEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i) <= "0000"; --WTF NO CS 20141112 --vio_async_out(7 + 18*((group_i*num_GTX_per_group)+gtx_i) downto 4 + 18*((group_i*num_GTX_per_group)+gtx_i) );
1318  TXPOSTEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i) <= "00000"; --WTF NO CS 20141112 --vio_async_out(12 + 18*((group_i*num_GTX_per_group)+gtx_i) downto 8 + 18*((group_i*num_GTX_per_group)+gtx_i) );
1319 
1320 
1321 
1322  GTXTXRESET((group_i*num_GTX_per_group)+gtx_i) <= GTXTXRESET_IN; --WTF NO CS 20141112 -- or vio_async_out(17 + 18*((group_i*num_GTX_per_group)+gtx_i) );
1323  --WTF NO CS 20141112 --
1324  TXDLYALIGNMONENB_IN((group_i*num_GTX_per_group)+gtx_i) <= '1';
1325 
1326 
1327 
1328  RXDLYALIGNMONENB_IN((group_i*num_GTX_per_group)+gtx_i) <= '1';
1329  PLLRXRESET_IN((group_i*num_GTX_per_group)+gtx_i)<='0';
1330 
1331  PLLTXRESET_IN<= (others=>'0');
1332  end generate txparamgen_gtx;
1333  end generate txparamgen_grp;
1334 
1335 
1336  --rx_param_data_gen: if gen_RX='1' generate
1337  rx_param_data_gen_grp: for group_i in (num_GTX_groups-1) downto 0 generate
1338  rx_param_data_gen_gtx: for gtx_i in (num_GTX_per_group-1) downto 0 generate
1339 
1340  GTXRXRESET((group_i*num_GTX_per_group)+gtx_i) <= GTXRXRESET_IN; --WTF NO CS 20141112 --or vio_async_out(16 + 18*((group_i*num_GTX_per_group)+gtx_i) );
1341  RXEQMIX_IN((group_i*num_GTX_per_group)+gtx_i) <="000"; --WTF NO CS 20141112 -- vio_async_out(15 + 18*((group_i*num_GTX_per_group)+gtx_i) downto 13 + 18*((group_i*num_GTX_per_group)+gtx_i) );
1342  --RXEQMIX_IN((group_i*num_GTX_per_group)+gtx_i) <= "001";
1343  RXDATA_OUT((group_i*num_GTX_per_group)+gtx_i)<=rxdata_i((group_i*num_GTX_per_group)+gtx_i)(15 downto 0);
1344 
1345  --WTF NO CS 20141112 --vio_sync_in(5+32*((group_i*num_GTX_per_group)+gtx_i) downto 0+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFECLKDLYADJMON((group_i*num_GTX_per_group)+gtx_i); --[5:0]
1346  --WTF NO CS 20141112 --vio_sync_in(10+32*((group_i*num_GTX_per_group)+gtx_i) downto 6+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFEEYEDACMON((group_i*num_GTX_per_group)+gtx_i); --[4:0]
1347  --WTF NO CS 20141112 --vio_sync_in(13+32*((group_i*num_GTX_per_group)+gtx_i) downto 11+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFESENSCAL((group_i*num_GTX_per_group)+gtx_i); --[2:0]
1348  --WTF NO CS 20141112 --vio_sync_in(18+32*((group_i*num_GTX_per_group)+gtx_i) downto 14+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFETAP1MONITOR((group_i*num_GTX_per_group)+gtx_i); --[4:0]
1349  --WTF NO CS 20141112 --vio_sync_in(23+32*((group_i*num_GTX_per_group)+gtx_i) downto 19+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFETAP2MONITOR((group_i*num_GTX_per_group)+gtx_i); --[4:0]
1350  --WTF NO CS 20141112 --vio_sync_in(27+32*((group_i*num_GTX_per_group)+gtx_i) downto 24+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFETAP3MONITOR((group_i*num_GTX_per_group)+gtx_i); --[3:0]
1351  --WTF NO CS 20141112 --vio_sync_in(31+32*((group_i*num_GTX_per_group)+gtx_i) downto 28+32*((group_i*num_GTX_per_group)+gtx_i)) <= DFETAP4MONITOR((group_i*num_GTX_per_group)+gtx_i); --[3:0]
1352 
1353 
1354  DFEDLYOVRD((group_i*num_GTX_per_group)+gtx_i) <= '0'; --WTF NO CS 20141112 --vio_sync_out( 0+26*((group_i*num_GTX_per_group)+gtx_i));
1355  DFECLKDLYADJ((group_i*num_GTX_per_group)+gtx_i) <= (others=>'0'); --WTF NO CS 20141112 --vio_sync_out( 6+26*((group_i*num_GTX_per_group)+gtx_i) downto 1+26*((group_i*num_GTX_per_group)+gtx_i)); -- [5:0]
1356  DFETAPOVRD((group_i*num_GTX_per_group)+gtx_i) <= '1'; --WTF NO CS 20141112 --vio_sync_out( 7+26*((group_i*num_GTX_per_group)+gtx_i));
1357  DFETAP1((group_i*num_GTX_per_group)+gtx_i) <= (others=>'0'); --WTF NO CS 20141112 --vio_sync_out( 12+26*((group_i*num_GTX_per_group)+gtx_i) downto 8+26*((group_i*num_GTX_per_group)+gtx_i)); -- [4:0]
1358  DFETAP2((group_i*num_GTX_per_group)+gtx_i) <= (others=>'0'); --WTF NO CS 20141112 --vio_sync_out( 17+26*((group_i*num_GTX_per_group)+gtx_i) downto 13+26*((group_i*num_GTX_per_group)+gtx_i)); -- [4:0]
1359  DFETAP3((group_i*num_GTX_per_group)+gtx_i) <= (others=>'0'); --WTF NO CS 20141112 --vio_sync_out( 21+26*((group_i*num_GTX_per_group)+gtx_i) downto 18+26*((group_i*num_GTX_per_group)+gtx_i)); -- [3:0]
1360  DFETAP4((group_i*num_GTX_per_group)+gtx_i) <= (others=>'0'); --WTF NO CS 20141112 --vio_sync_out( 25+26*((group_i*num_GTX_per_group)+gtx_i) downto 22+26*((group_i*num_GTX_per_group)+gtx_i)); -- [3:0]
1361 
1362  end generate rx_param_data_gen_gtx;
1363  end generate rx_param_data_gen_grp;
1364  --end generate rx_param_data_gen;
1365 
1366 
1367 
1368  ibufds_gtxe1_gen: for group_i in (num_GTX_groups-1) downto 0 generate
1369  q1_clk0_refclk_ibufds_i : IBUFDS_GTXE1
1370  port map
1371  (
1372  O => refclk_i(group_i),
1373  ODIV2 => open,
1374  CEB => tied_to_ground_i,
1375  I => MGTREFCLK_PAD_P_IN(group_i),
1376  IB => MGTREFCLK_PAD_N_IN(group_i)
1377  );
1378  end generate ibufds_gtxe1_gen;
1379 
1380 --- --- q1_clk0_refclk_ibufds_i : IBUFDS_GTXE1
1381 --- --- port map
1382 --- --- (
1383 --- --- O => q1_clk0_refclk_i,
1384 --- --- ODIV2 => open,
1385 --- --- CEB => tied_to_ground_i,
1386 --- --- I => Q1_CLK0_MGTREFCLK_PAD_P_IN,
1387 --- --- IB => Q1_CLK0_MGTREFCLK_PAD_N_IN
1388 --- --- );
1389 --- ---
1390 --- ---
1391 --- --- q4_clk0_refclk_ibufds_i : IBUFDS_GTXE1
1392 --- --- port map
1393 --- --- (
1394 --- --- O => q4_clk0_refclk_i,
1395 --- --- ODIV2 => open,
1396 --- --- CEB => tied_to_ground_i,
1397 --- --- I => Q4_CLK0_MGTREFCLK_PAD_P_IN,
1398 --- --- IB => Q4_CLK0_MGTREFCLK_PAD_N_IN
1399 --- --- );
1400 --- ---
1401 --- --- refclk_i(0)<=q1_clk0_refclk_i;
1402 --- --- refclk_i(1)<=q4_clk0_refclk_i;
1403 
1404  --rx_clk_nets_gen: if gen_RX='1' generate
1405  -- rx_clk_nets_gen_gtx: for gtx_i in (num_GTX_groups*num_GTX_per_group-1) downto 0 generate
1406  --
1407  -- RXUSRCLK2_IN(gtx_i)<=RXRECCLK_OUT(gtx_i); --this seems to automatically
1408  -- --infer a BUFG
1409  --
1410  -- --not enough BUFRs per region
1411  -- --rxrecclk_bufr_i : BUFR
1412  -- -- generic map
1413  -- -- (
1414  -- -- BUFR_DIVIDE => "BYPASS",
1415  -- -- SIM_DEVICE => "VIRTEX6"
1416  -- -- )
1417  -- -- port map
1418  -- -- (
1419  -- -- CE => '1',
1420  -- -- CLR => '0',
1421  -- -- I => RXRECCLK_OUT(gtx_i),
1422  -- -- O => RXUSRCLK2_IN_bufferedR(gtx_i)
1423  -- -- );
1424  -- --
1425  --
1426  -- --BUFHs can not be driven by the
1427  -- --rxrecclk_bufh_i : BUFH
1428  -- -- port map
1429  -- -- (
1430  -- -- I => RXRECCLK_OUT(gtx_i),
1431  -- -- O => RXUSRCLK2_IN_bufferedR(gtx_i)
1432  -- -- );
1433  -- --
1434  -- --
1435  -- --RXUSRCLK2_IN(gtx_i) <= RXUSRCLK2_IN_bufferedR(gtx_i);
1436  --
1437  -- end generate rx_clk_nets_gen_gtx;
1438  --end generate rx_clk_nets_gen;
1439 
1440 
1441  clk_nets_gen: for group_i in (num_GTX_groups-1) downto 0 generate
1442 
1443  rx_bufr_gen: if gen_RX='1' generate
1444  rxrecclk_bufr1_i : BUFR
1445  generic map
1446  (
1447  BUFR_DIVIDE => "BYPASS",
1448  SIM_DEVICE => "VIRTEX6"
1449  )
1450  port map
1451  (
1452  CE => '1',
1453  CLR => '0',
1454  I => RXRECCLK_OUT (group_i*num_GTX_per_group+rx_clk_source_offset),
1455  O => RXUSRCLK2_IN_bufferedR (group_i)
1456  );
1457  end generate rx_bufr_gen;
1458 
1459  rx_plllk_andall_gen: if gen_RX='1' generate
1460  and_all_inst_rx: and_all
1461  generic map (
1462  numbits => num_GTX_per_group
1463  )
1464  port map (
1465  DATA =>RXPLLLKDET_OUT ( ((group_i+1)*num_GTX_per_group-1) downto (group_i*num_GTX_per_group)),
1466  and_all =>RXPLLLKDET_group(group_i)
1467  );
1468  cRXPLLLKDET_group(group_i) <= not RXPLLLKDET_group(group_i);
1469  end generate rx_plllk_andall_gen;
1470 
1471  and_all_inst_tx: and_all
1472  generic map (
1473  numbits => num_GTX_per_group
1474  )
1475  port map (
1476  DATA =>TXPLLLKDET_OUT( ((group_i+1)*num_GTX_per_group-1) downto (group_i*num_GTX_per_group)),
1477  and_all =>TXPLLLKDET_group (group_i)
1478  );
1479  cTXPLLLKDET_group(group_i) <= not TXPLLLKDET_group(group_i);
1480 
1481  mmcm_adv_usrclk : MMCM_ADV
1482  generic map
1483  (
1484  COMPENSATION => "ZHOLD",
1485  CLKFBOUT_MULT_F => gtx_mmcm_CLKFBOUT_MULT_F ,
1486  DIVCLK_DIVIDE => gtx_mmcm_DIVCLK_DIVIDE,
1487  CLKFBOUT_PHASE => 0.0,
1488  CLKIN1_PERIOD => gtx_mmcm_CLKIN1_PERIOD,
1489  CLKIN2_PERIOD => 10.0, -- Not used
1490  CLKOUT0_DIVIDE_F => gtx_mmcm_CLKOUT0_DIVIDE_F ,
1491  CLKOUT0_PHASE => 0.0,
1492  CLKOUT1_DIVIDE => 1,
1493  CLKOUT1_PHASE => 0.0,
1494  CLKOUT2_DIVIDE => 1,
1495  CLKOUT2_PHASE => 0.0,
1496  CLKOUT3_DIVIDE => 1,
1497  CLKOUT3_PHASE => 0.0,
1498  CLOCK_HOLD => TRUE
1499  )
1500  port map
1501  (
1502  CLKIN1 => TXOUTCLK_OUT(group_i*num_GTX_per_group),
1503  CLKIN2 => tied_to_ground_i ,
1504  CLKINSEL => tied_to_vcc_i,
1505  CLKFBIN => mmcm_fback(group_i),
1506  CLKOUT0 => TXUSRCLK2_IN_unbuffered (group_i),
1507  CLKOUT0B => open,
1508  CLKOUT1 => open,
1509  CLKOUT1B => open,
1510  CLKOUT2 => open,
1511  CLKOUT2B => open,
1512  CLKOUT3 => open,
1513  CLKOUT3B => open,
1514  CLKOUT4 => open,
1515  CLKOUT5 => open,
1516  CLKOUT6 => open,
1517  CLKFBOUT => mmcm_fback(group_i),
1518  CLKFBOUTB => open,
1519  CLKFBSTOPPED => open,
1520  CLKINSTOPPED => open,
1521  DO => open,
1522  DRDY => open,
1523  DADDR => tied_to_ground_vec_i(6 downto 0),
1524  DCLK => tied_to_ground_i ,
1525  DEN => tied_to_ground_i ,
1526  DI => tied_to_ground_vec_i (15 downto 0),
1527  DWE => tied_to_ground_i ,
1528  LOCKED => mmcm_locked(group_i),
1529  PSCLK => tied_to_ground_i ,
1530  PSEN => tied_to_ground_i ,
1531  PSINCDEC => tied_to_ground_i ,
1532  PSDONE => open,
1533  PWRDWN => tied_to_ground_i ,
1534  RST => cTXPLLLKDET_group(group_i)
1535  );
1536 
1537 
1538  clkout0_bufg_i : BUFG
1539  port map
1540  (
1541  O => TXUSRCLK2_IN_bufferedG (group_i),
1542  I => TXUSRCLK2_IN_unbuffered (group_i)
1543  );
1544 
1545  mgtclk_gen: for gtx_i in (num_GTX_per_group - 1) downto 0 generate
1546  TXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i)<=TXUSRCLK2_IN_bufferedG(group_i);
1547  MGTREFCLKTX_IN((group_i*num_GTX_per_group)+gtx_i)<=(tied_to_ground_i & refclk_i(group_i));
1548 
1549  rxclk_gen: if gen_RX='1' generate
1550  RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i)<=RXUSRCLK2_IN_bufferedR(group_i);
1551  --RXUSRCLK2_IN_out( (group_i*num_GTX_per_group)+gtx_i )<=RXUSRCLK2_IN( (group_i*num_GTX_per_group)+gtx_i );
1552  MGTREFCLKRX_IN((group_i*num_GTX_per_group)+gtx_i)<=(tied_to_ground_i & refclk_i(group_i));
1553  end generate rxclk_gen;
1554  norxclk_gen: if gen_RX='0' generate
1555  RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i)<='0';
1556  MGTREFCLKRX_IN((group_i*num_GTX_per_group)+gtx_i)<=(others=>'0');
1557  end generate norxclk_gen;
1558 
1559  end generate mgtclk_gen;
1560 
1561  end generate clk_nets_gen;
1562 
1563 
1564  sync_gen_grp: for group_i in (num_GTX_groups-1) downto 0 generate
1565 
1566  process(mmcm_locked(group_i), TXUSRCLK2_IN_bufferedG(group_i))
1567  begin
1568  if mmcm_locked(group_i)='0' then
1569  TXRESETDONE_OUT_r( ((group_i+1)*num_GTX_per_group-1) downto group_i*num_GTX_per_group ) <= (others=>'0');
1570  TXRESETDONE_OUT_rr( ((group_i+1)*num_GTX_per_group-1) downto group_i*num_GTX_per_group ) <= (others=>'0');
1571  elsif rising_edge(TXUSRCLK2_IN_bufferedG(group_i)) then
1572  TXRESETDONE_OUT_r( ((group_i+1)*num_GTX_per_group-1) downto group_i*num_GTX_per_group )<=TXRESETDONE_OUT( ((group_i+1)*num_GTX_per_group-1) downto group_i*num_GTX_per_group );
1573  TXRESETDONE_OUT_rr( ((group_i+1)*num_GTX_per_group-1) downto group_i*num_GTX_per_group )<=TXRESETDONE_OUT_r( ((group_i+1)*num_GTX_per_group-1) downto group_i*num_GTX_per_group );
1574  end if;
1575  end process;
1576 
1577 
1578  rxreset_gen: if gen_RX='1' generate
1579 
1580  and_all_rxreset_done: and_all
1581  generic map (
1582  numbits => num_GTX_per_group
1583  )
1584  port map (
1585  DATA =>RXRESETDONE_OUT ( ((group_i+1)*num_GTX_per_group-1) downto (group_i*num_GTX_per_group)),
1586  and_all =>RXRESETDONE_OUT_group (group_i)
1587  );
1588 
1589  end generate rxreset_gen;
1590 
1591 
1592  sync_gen_gtx: for gtx_i in (num_GTX_per_group-1) downto 0 generate
1593 
1594  no_rxreseten_rxsync_rxalign_gen: if gen_RX='0' generate
1595  RXENPMAPHASEALIGN_IN<=(others => '0');
1596  RXPMASETPHASE_IN<=(others => '0');
1597  RXDLYALIGNDISABLE_IN<=(others => '0');
1598  RXDLYALIGNOVERRIDE_IN<=(others => '1');
1599  RXDLYALIGNRESET_IN<=(others => '0');
1600  RXENPCOMMAALIGN_IN<=(others => '0');
1601  RXENMCOMMAALIGN_IN<=(others => '0');
1602  rx_sync_done<= (others => '1');
1603  end generate no_rxreseten_rxsync_rxalign_gen;
1604 
1605  rxreseten_rxsync_rxalign_gen: if gen_RX='1' generate
1606 
1607  --I don't know why the rx reset is registered with reset in the middle two
1608  --and not the begin and end register - following the example code
1609  process(RXUSRCLK2_IN( (group_i*num_GTX_per_group)+gtx_i ))
1610  begin
1611  if rising_edge(RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i)) then
1612  RXRESETDONE_OUT_r( (group_i*num_GTX_per_group)+gtx_i ) <= RXRESETDONE_OUT( (group_i*num_GTX_per_group)+gtx_i );
1613  RXRESETDONE_OUT_rrrr( (group_i*num_GTX_per_group)+gtx_i ) <= RXRESETDONE_OUT_rrr( (group_i*num_GTX_per_group)+gtx_i );
1614  end if;
1615  end process;
1616 
1617  process(RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i),RXRESETDONE_OUT((group_i*num_GTX_per_group)+gtx_i))
1618  begin
1619  if rising_edge(RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i)) then
1620  RXRESETDONE_OUT_rrr((group_i*num_GTX_per_group)+gtx_i) <= RXRESETDONE_OUT_rr((group_i*num_GTX_per_group)+gtx_i);
1621  RXRESETDONE_OUT_rr((group_i*num_GTX_per_group)+gtx_i) <= RXRESETDONE_OUT_r((group_i*num_GTX_per_group)+gtx_i);
1622  end if;
1623  end process;
1624 
1625  reset_rx_sync((group_i*num_GTX_per_group)+gtx_i)<= not (RXRESETDONE_OUT_rrrr((group_i*num_GTX_per_group)+gtx_i) and RXPLLLKDET_group(group_i) and wait_done((group_i*num_GTX_per_group)+gtx_i) );
1626 
1627  use_RX_phasealign_gen: if use_RX_elastic=FALSE generate
1628 
1629  gtx0_rxsync_i : rx_sync
1630  port map
1631  (
1632  RXENPMAPHASEALIGN => RXENPMAPHASEALIGN_IN ((group_i*num_GTX_per_group)+gtx_i),
1633  RXPMASETPHASE => RXPMASETPHASE_IN((group_i*num_GTX_per_group)+gtx_i),
1634  RXDLYALIGNDISABLE => RXDLYALIGNDISABLE_IN ((group_i*num_GTX_per_group)+gtx_i),
1635  RXDLYALIGNOVERRIDE => RXDLYALIGNOVERRIDE_IN ((group_i*num_GTX_per_group)+gtx_i),
1636  RXDLYALIGNRESET => RXDLYALIGNRESET_IN((group_i*num_GTX_per_group)+gtx_i),
1637  SYNC_DONE => rx_sync_done ((group_i*num_GTX_per_group)+gtx_i),
1638  USER_CLK => RXUSRCLK2_IN (group_i),
1639  RESET => reset_rx_sync ((group_i*num_GTX_per_group)+gtx_i)
1640  );
1641 
1642  end generate use_RX_phasealign_gen;
1643 
1644  use_RX_elastic_gen: if use_RX_elastic=TRUE generate
1645 
1646  RXENPMAPHASEALIGN_IN((group_i*num_GTX_per_group)+gtx_i)<=tied_to_ground_i;
1647  RXPMASETPHASE_IN((group_i*num_GTX_per_group)+gtx_i)<=tied_to_ground_i;
1648  RXDLYALIGNDISABLE_IN((group_i*num_GTX_per_group)+gtx_i)<=tied_to_ground_i;
1649  RXDLYALIGNOVERRIDE_IN((group_i*num_GTX_per_group)+gtx_i)<=tied_to_vcc_i;
1650  RXDLYALIGNRESET_IN((group_i*num_GTX_per_group)+gtx_i)<=tied_to_ground_i;
1651  rx_sync_done((group_i*num_GTX_per_group)+gtx_i)<= not reset_rx_sync((group_i*num_GTX_per_group)+gtx_i);
1652  end generate use_RX_elastic_gen;
1653 
1654 
1655  -- after the rx sync is done comma alignment must be performed
1656  process( RXUSRCLK2_IN_bufferedR(group_i) )
1657  begin
1658  if rising_edge(RXUSRCLK2_IN_bufferedR(group_i)) then
1659  if(rx_sync_done((group_i*num_GTX_per_group)+gtx_i) = '0') then
1660  RXENMCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i) <= '0';
1661  RXENPCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i) <= '0';
1662  else
1663  if RXBYTEISALIGNED_OUT_r((group_i*num_GTX_per_group)+gtx_i) = '0' then
1664  RXENMCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i) <= '1';
1665  RXENPCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i) <= '1';
1666  else
1667  RXENMCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i) <= '0';
1668  RXENPCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i) <= '0';
1669  end if;
1670  end if;
1671  RXBYTEISALIGNED_OUT_r((group_i*num_GTX_per_group)+gtx_i)<=RXBYTEISALIGNED_OUT((group_i*num_GTX_per_group)+gtx_i);
1672  end if;
1673  end process;
1674 
1675 
1676 
1677  --align receivers to the commas
1678  --and check if the comma is in the right place if alignment has been
1679  --done before
1680 
1681  --also check for valid characters and realignment events
1682 
1683  --note that zeroing at cycle 6 is for ML605
1684  subtick_counter_rx_next((group_i*num_GTX_per_group)+gtx_i)<=subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)+1;-- when subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)/=to_unsigned(5,3) else to_unsigned(0,3) ;
1685 
1686  process( RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i) ) --RXUSRCLK2_IN_bufferedR(group_i) )
1687  begin
1688  if rising_edge(RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i) ) then --RXUSRCLK2_IN_bufferedR(group_i)) then
1689  if RXBYTEISALIGNED_OUT_r((group_i*num_GTX_per_group)+gtx_i) = '0' then
1690  subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)<=to_unsigned(3,3);
1691  subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i)<='0';
1692  rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)<='0';
1693  else
1694  if subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i) = '0' then
1695  if RXCHARISK_OUT((group_i*num_GTX_per_group)+gtx_i)(0)='1' and RXDATA_OUT((group_i*num_GTX_per_group)+gtx_i)(7 downto 0) = x"BC" then
1696  subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i) <= '1';
1697  subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)<=to_unsigned(5,3); --ML605 WTF thk ok for target (8 cycle)
1698  rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)<='0';
1699  else
1700  subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i) <= '0';
1701  subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)<=to_unsigned(3,3);
1702  rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)<='0';
1703  end if;
1704  else
1705  if RXCHARISK_OUT((group_i*num_GTX_per_group)+gtx_i)(0)='1' and RXDATA_OUT((group_i*num_GTX_per_group)+gtx_i)(7 downto 0) = x"BC" then
1706  if subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i) /= to_unsigned(4,3) then --ML605 WTF thk ok for target (8 cycle)
1707  subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)<=to_unsigned(5,3); --ML605 WTF thk ok for target (8 cycle)
1708  rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)<='1';
1709  subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i) <= '1';
1710  else
1711  subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)<=subtick_counter_rx_next((group_i*num_GTX_per_group)+gtx_i);
1712  rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)<='0';
1713  subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i) <= '1';
1714  end if;
1715  else
1716  subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i)<=subtick_counter_rx_next((group_i*num_GTX_per_group)+gtx_i);
1717  rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)<='0';
1718  subtick_counter_rx_started((group_i*num_GTX_per_group)+gtx_i) <= '1';
1719  end if;
1720  end if;
1721  end if;
1722 
1723  rx_error_not_in_table((group_i*num_GTX_per_group)+gtx_i)<=RXNOTINTABLE_OUT((group_i*num_GTX_per_group)+gtx_i)(0) or
1724  RXNOTINTABLE_OUT((group_i*num_GTX_per_group)+gtx_i)(1);
1725 
1726  rx_error_byterealign((group_i*num_GTX_per_group)+gtx_i)<=RXBYTEREALIGN_OUT((group_i*num_GTX_per_group)+gtx_i);
1727 
1728  rx_error_disparity((group_i*num_GTX_per_group)+gtx_i)<=RXDISPERR_OUT((group_i*num_GTX_per_group)+gtx_i)(0) or
1729  RXDISPERR_OUT((group_i*num_GTX_per_group)+gtx_i)(1);
1730 
1731  rx_error_any((group_i*num_GTX_per_group)+gtx_i)<=rx_error_disparity((group_i*num_GTX_per_group)+gtx_i)
1732  or rx_error_byterealign((group_i*num_GTX_per_group)+gtx_i)
1733  or rx_error_not_in_table((group_i*num_GTX_per_group)+gtx_i)
1734  or rx_error_eventrealign((group_i*num_GTX_per_group)+gtx_i)
1735  or rx_error_crc((group_i*num_GTX_per_group)+gtx_i);
1736 
1737  RXDATA_OUT_reg((group_i*num_GTX_per_group)+gtx_i)<=RXDATA_OUT((group_i*num_GTX_per_group)+gtx_i);
1738  subtick_counter_rx_reg((group_i*num_GTX_per_group)+gtx_i)<=subtick_counter_rx((group_i*num_GTX_per_group)+gtx_i);
1739 
1740  --RX_COMMA_RECEIVED((group_i*num_GTX_per_group)+gtx_i)<=RXCHARISK_OUT((group_i*num_GTX_per_group)+gtx_i)(0) or
1741  -- RXCHARISK_OUT((group_i*num_GTX_per_group)+gtx_i)(1);
1742 
1743  end if;
1744  end process;
1745 
1746  --delay every input by one tick so that the timing closes
1747  CRC_CHECK_inst: CRC_CHECK
1748  port map (
1749  DATA_in => RXDATA_OUT_reg((group_i*num_GTX_per_group)+gtx_i),
1750  CRC_ERR => rx_error_crc((group_i*num_GTX_per_group)+gtx_i),
1751  clk => RXUSRCLK2_IN((group_i*num_GTX_per_group)+gtx_i),
1752  rx_subtick_counter => subtick_counter_rx_reg((group_i*num_GTX_per_group)+gtx_i));
1753 
1754 
1755 
1756 
1757  end generate rxreseten_rxsync_rxalign_gen;
1758 
1759 
1760 
1761  reset_tx_sync((group_i*num_GTX_per_group)+gtx_i)<= not TXRESETDONE_OUT_rr((group_i*num_GTX_per_group)+gtx_i);
1762 
1763  tx_sync_i: tx_sync
1764  generic map (
1765  SIM_TXPMASETPHASE_SPEEDUP => SIM_GTXRESET_SPEEDUP)
1766  port map (
1767  TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_IN((group_i*num_GTX_per_group)+gtx_i),
1768  TXPMASETPHASE => TXPMASETPHASE_IN ((group_i*num_GTX_per_group)+gtx_i),
1769  TXDLYALIGNDISABLE => TXDLYALIGNDISABLE_IN((group_i*num_GTX_per_group)+gtx_i),
1770  TXDLYALIGNRESET => TXDLYALIGNRESET_IN((group_i*num_GTX_per_group)+gtx_i),
1771  SYNC_DONE => tx_sync_done((group_i*num_GTX_per_group)+gtx_i),
1772  USER_CLK => TXUSRCLK2_IN_bufferedG(group_i),
1773  RESET => reset_tx_sync((group_i*num_GTX_per_group)+gtx_i)
1774  );
1775 
1776 
1777 
1778  end generate sync_gen_gtx;
1779  end generate sync_gen_grp;
1780 
1781  --if RX is instantiated or all the error flags and or that to generate the
1782  --output signal RX_ERROR_OUT
1783  ---rxreseten_rxsync_rxalign_all_gen: if gen_RX='1' generate
1784  --- or_all_rx_error_not_in_table: or_all
1785  --- generic map (
1786  --- numbits => num_GTX_groups*num_fifos_per_group)
1787  --- port map (
1788  --- DATA => rx_error_not_in_table,
1789  --- or_all => rx_error_not_in_table_all);
1790  ---
1791  --- or_all_rx_error_byterealign: or_all
1792  --- generic map (
1793  --- numbits => num_GTX_groups*num_fifos_per_group)
1794  --- port map (
1795  --- DATA => rx_error_byterealign,
1796  --- or_all => rx_error_byterealign_all);
1797  ---
1798  --- or_all_rx_error_eventrealign: or_all
1799  --- generic map (
1800  --- numbits => num_GTX_groups*num_fifos_per_group)
1801  --- port map (
1802  --- DATA => rx_error_eventrealign,
1803  --- or_all => rx_error_eventrealign_all);
1804  ---
1805  --- or_all_rx_error_crc: or_all
1806  --- generic map (
1807  --- numbits => num_GTX_groups*num_fifos_per_group)
1808  --- port map (
1809  --- DATA => rx_error_crc,
1810  --- or_all => rx_error_crc_all);
1811  ---
1812  --- or_all_rx_error_disparity: or_all
1813  --- generic map (
1814  --- numbits => num_GTX_groups*num_fifos_per_group)
1815  --- port map (
1816  --- DATA => rx_error_disparity,
1817  --- or_all => rx_error_disparity_all);
1818  ---
1819  --- RX_ERROR_OUT_sig<= rx_error_crc_all or rx_error_eventrealign_all or rx_error_byterealign_all or rx_error_not_in_table_all or rx_error_disparity_all;
1820  ---
1821  ---end generate rxreseten_rxsync_rxalign_all_gen;
1822 
1823  --rxreseten_rxsync_rxalign_all_no_gen: if gen_RX='0' generate
1824  -- RX_ERROR_OUT_sig<='0';
1825  --end generate rxreseten_rxsync_rxalign_all_no_gen;
1826 
1827  --RX_ERROR_OUT<=RX_ERROR_OUT_sig;
1828 
1829  and_all_tx_sync_done_grp_gen: for group_i in (num_GTX_groups-1) downto 0 generate
1830 
1831  and_all_tx_sync_done_grp: and_all
1832  generic map (
1833  numbits => num_GTX_per_group )
1834  port map (
1835  DATA => tx_sync_done ((group_i+1)*num_GTX_per_group-1 downto group_i*num_GTX_per_group),
1836  and_all => tx_sync_done_grp (group_i));
1837 
1838  c_tx_sync_done_grp(group_i)<=not tx_sync_done_grp(group_i);
1839 
1840 
1841  process(TXUSRCLK2_IN_bufferedG(group_i))
1842  begin
1843  if rising_edge(TXUSRCLK2_IN_bufferedG(group_i)) then
1844  c_tx_sync_done_grp_r(group_i)<=c_tx_sync_done_grp(group_i);
1845  tx_sync_done_grp_r(group_i)<=tx_sync_done_grp(group_i);
1846  end if;
1847  end process;
1848 
1849  end generate and_all_tx_sync_done_grp_gen;
1850 
1851  and_all_tx_sync_done: and_all
1852  generic map (
1853  numbits => num_GTX_groups )
1854  port map (
1855  DATA =>tx_sync_done_grp_r ,
1856  and_all =>GTX_TX_READY_OUT);
1857 
1858  --and_all_tx_sync_done: and_all
1859  -- generic map (
1860  -- numbits => num_GTX_per_group*num_GTX_groups)
1861  -- port map (
1862  -- DATA => tx_sync_done,
1863  -- and_all => GTX_TX_READY_OUT_sig);
1864  --
1865  --GTX_TX_READY_OUT<=GTX_TX_READY_OUT_sig;
1866  --cGTX_TX_READY_OUT_sig<=not GTX_TX_READY_OUT_sig;
1867 
1868 
1869 
1870 
1871  and_all_rx_aligned_gen: if gen_RX='1' generate
1872  and_all_rx_aligned: and_all
1873  generic map (
1874  numbits => num_GTX_per_group*num_GTX_groups)
1875  port map (
1876  DATA => RXBYTEISALIGNED_OUT_r ,
1877  and_all => GTX_RX_READY_OUT_sig );
1878  GTX_RX_READY_OUT<=GTX_RX_READY_OUT_sig;
1879  end generate and_all_rx_aligned_gen;
1880  gen_no_rx_rx_ready: if gen_RX='0' generate
1881  GTX_RX_READY_OUT_sig<='0';
1882  GTX_RX_READY_OUT<=GTX_RX_READY_OUT_sig;
1883  end generate gen_no_rx_rx_ready;
1884 
1885 
1886  vme_inreg_REG_RW_RX_POLARITY_0: vme_inreg_notri_async
1887  generic map (
1888  ia_vme => ADDR_REG_RW_RX_POLARITY ,
1889  width => 16)
1890  port map (
1891  ncs => ncs,
1892  rd_nwr => rd_nwr,
1893  ds => ds,
1894  data_from_vme => rx_polarity(15 downto 0),
1895  data_to_vme => rx_polarity(15 downto 0),
1896  addr_vme => addr_vme,
1897  data_vme_in => data_vme_in,
1898  data_vme_out => data_vme_from_below (0),
1899  bus_drive => bus_drive_from_below (0) );
1900 
1901  vme_inreg_REG_RW_RX_POLARITY_1: vme_inreg_notri_async
1902  generic map (
1903  ia_vme => ADDR_REG_RW_RX_POLARITY+2 ,
1904  width => 16)
1905  port map (
1906  ncs => ncs,
1907  rd_nwr => rd_nwr,
1908  ds => ds,
1909  data_from_vme => rx_polarity(31 downto 16),
1910  data_to_vme => rx_polarity(31 downto 16),
1911  addr_vme => addr_vme,
1912  data_vme_in => data_vme_in,
1913  data_vme_out => data_vme_from_below (1),
1914  bus_drive => bus_drive_from_below (1) );
1915 
1916  vme_inreg_REG_RW_RX_POLARITY_2: vme_inreg_notri_async
1917  generic map (
1918  ia_vme => ADDR_REG_RW_RX_POLARITY+4 ,
1919  width => 16)
1920  port map (
1921  ncs => ncs,
1922  rd_nwr => rd_nwr,
1923  ds => ds,
1924  data_from_vme => rx_polarity(47 downto 32),
1925  data_to_vme => rx_polarity(47 downto 32),
1926  addr_vme => addr_vme,
1927  data_vme_in => data_vme_in,
1928  data_vme_out => data_vme_from_below (2),
1929  bus_drive => bus_drive_from_below (2) );
1930 
1931 
1932 
1933  vme_inreg_REG_RW_TX_POLARITY_0: vme_inreg_notri_async
1934  generic map (
1935  ia_vme => ADDR_REG_RW_TX_POLARITY ,
1936  width => 16)
1937  port map (
1938  ncs => ncs,
1939  rd_nwr => rd_nwr,
1940  ds => ds,
1941  data_from_vme => tx_polarity(15 downto 0),
1942  data_to_vme => tx_polarity(15 downto 0),
1943  addr_vme => addr_vme,
1944  data_vme_in => data_vme_in,
1945  data_vme_out => data_vme_from_below (3),
1946  bus_drive => bus_drive_from_below (3) );
1947 
1948  vme_inreg_REG_RW_TX_POLARITY_1: vme_inreg_notri_async
1949  generic map (
1950  ia_vme => ADDR_REG_RW_TX_POLARITY+2 ,
1951  width => 16)
1952  port map (
1953  ncs => ncs,
1954  rd_nwr => rd_nwr,
1955  ds => ds,
1956  data_from_vme => tx_polarity(31 downto 16),
1957  data_to_vme => tx_polarity(31 downto 16),
1958  addr_vme => addr_vme,
1959  data_vme_in => data_vme_in,
1960  data_vme_out => data_vme_from_below (4),
1961  bus_drive => bus_drive_from_below (4) );
1962 
1963  vme_inreg_REG_RW_TX_POLARITY_2: vme_inreg_notri_async
1964  generic map (
1965  ia_vme => ADDR_REG_RW_TX_POLARITY+4 ,
1966  width => 16)
1967  port map (
1968  ncs => ncs,
1969  rd_nwr => rd_nwr,
1970  ds => ds,
1971  data_from_vme => tx_polarity(47 downto 32),
1972  data_to_vme => tx_polarity(47 downto 32),
1973  addr_vme => addr_vme,
1974  data_vme_in => data_vme_in,
1975  data_vme_out => data_vme_from_below (5),
1976  bus_drive => bus_drive_from_below (5) );
1977 
1978 
1979 
1980 
1981  MGT_gen_grp: for group_i in (num_GTX_groups-1) downto 0 generate
1982 
1983  MGT_gen_gtx: for gtx_i in (num_GTX_per_group-1) downto 0 generate
1984 
1985  gtxe1_i :GTXE1
1986  generic map
1987  (
1988 
1989  --_______________________ Simulation-Only Attributes ___________________
1990 
1991  SIM_RECEIVER_DETECT_PASS => (TRUE),
1992 
1993  SIM_GTXRESET_SPEEDUP => (SIM_GTXRESET_SPEEDUP),
1994 
1995  SIM_TX_ELEC_IDLE_LEVEL => ("X"),
1996 
1997  SIM_VERSION => ("2.0"),
1998  SIM_TXREFCLK_SOURCE => ("000"),
1999  SIM_RXREFCLK_SOURCE => ("000"),
2000 
2001 
2002  ----------------------------TX PLL----------------------------
2003  TX_CLK_SOURCE => ("TXPLL"),
2004  TX_OVERSAMPLE_MODE => (FALSE),
2005  TXPLL_COM_CFG => (x"21680a"),
2006  TXPLL_CP_CFG => (x"0D"),
2007  TXPLL_DIVSEL_FB => (gtx_PLL_DIVSEL_FB),
2008  TXPLL_DIVSEL_OUT => (gtx_PLL_DIVSEL_OUT),
2009  TXPLL_DIVSEL_REF => (gtx_PLL_DIVSEL_REF),
2010  TXPLL_DIVSEL45_FB => (gtx_DIVSEL45_FB),
2011  TXPLL_LKDET_CFG => ("111"),
2012  TX_CLK25_DIVIDER => (gtx_CLK25_DIVIDER),
2013  TXPLL_SATA => ("00"),
2014  TX_TDCC_CFG => ("11"),
2015  PMA_CAS_CLK_EN => (FALSE),
2016  POWER_SAVE => ("0000110000"),
2017 
2018  -------------------------TX Interface-------------------------
2019  GEN_TXUSRCLK => (TRUE),
2020  TX_DATA_WIDTH => (20),
2021  TX_USRCLK_CFG => (x"00"),
2022  TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV1"),
2023  TXOUTCLK_DLY => ("0000000000"),
2024 
2025  --------------TX Buffering and Phase Alignment----------------
2026  TX_PMADATA_OPT => ('1'),
2027  PMA_TX_CFG => (x"80082"),
2028  TX_BUFFER_USE => (FALSE),
2029  TX_BYTECLK_CFG => (x"00"),
2030  TX_EN_RATE_RESET_BUF => (TRUE),
2031  TX_XCLK_SEL => ("TXUSR"),
2032  TX_DLYALIGN_CTRINC => ("0100"),
2033  TX_DLYALIGN_LPFINC => ("0110"),
2034  TX_DLYALIGN_MONSEL => ("000"),
2035  TX_DLYALIGN_OVRDSETTING => ("10000000"),
2036 
2037  -------------------------TX Gearbox---------------------------
2038  GEARBOX_ENDEC => ("000"),
2039  TXGEARBOX_USE => (FALSE),
2040 
2041  ----------------TX Driver and OOB Signalling------------------
2042  TX_DRIVE_MODE => ("DIRECT"),
2043  TX_IDLE_ASSERT_DELAY => ("100"),
2044  TX_IDLE_DEASSERT_DELAY => ("010"),
2045  TXDRIVE_LOOPBACK_HIZ => (FALSE),
2046  TXDRIVE_LOOPBACK_PD => (FALSE),
2047 
2048  --------------TX Pipe Control for PCI Express/SATA------------
2049  COM_BURST_VAL => ("1111"),
2050 
2051  ------------------TX Attributes for PCI Express---------------
2052  TX_DEEMPH_0 => ("11010"),
2053  TX_DEEMPH_1 => ("10000"),
2054  TX_MARGIN_FULL_0 => ("1001110"),
2055  TX_MARGIN_FULL_1 => ("1001001"),
2056  TX_MARGIN_FULL_2 => ("1000101"),
2057  TX_MARGIN_FULL_3 => ("1000010"),
2058  TX_MARGIN_FULL_4 => ("1000000"),
2059  TX_MARGIN_LOW_0 => ("1000110"),
2060  TX_MARGIN_LOW_1 => ("1000100"),
2061  TX_MARGIN_LOW_2 => ("1000010"),
2062  TX_MARGIN_LOW_3 => ("1000000"),
2063  TX_MARGIN_LOW_4 => ("1000000"),
2064 
2065  ----------------------------RX PLL----------------------------
2066  RX_OVERSAMPLE_MODE => (FALSE),
2067  RXPLL_COM_CFG => (x"21680a"),
2068  RXPLL_CP_CFG => (x"0D"),
2069  RXPLL_DIVSEL_FB => (gtx_PLL_DIVSEL_FB ),
2070  RXPLL_DIVSEL_OUT => (gtx_PLL_DIVSEL_OUT ),
2071  RXPLL_DIVSEL_REF => (gtx_PLL_DIVSEL_REF ),
2072  RXPLL_DIVSEL45_FB => (gtx_DIVSEL45_FB ),
2073  RXPLL_LKDET_CFG => ("111"),
2074  RX_CLK25_DIVIDER => (gtx_CLK25_DIVIDER ),
2075 
2076  -------------------------RX Interface-------------------------
2077  GEN_RXUSRCLK => (TRUE),
2078  RX_DATA_WIDTH => (20),
2079  RXRECCLK_CTRL => ("RXRECCLKPMA_DIV2"),
2080  RXRECCLK_DLY => ("0000000000"),
2081  RXUSRCLK_DLY => (x"0000"),
2082 
2083  ----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
2084  AC_CAP_DIS => (FALSE),
2085  CDR_PH_ADJ_TIME => ("10100"),
2086  OOBDETECT_THRESHOLD => ("011"),
2087  PMA_CDR_SCAN => (x"640404C"),
2088  PMA_RX_CFG => (x"05ce008"),
2089  RCV_TERM_GND => (FALSE),
2090  RCV_TERM_VTTRX => (TRUE),
2091  RX_EN_IDLE_HOLD_CDR => (FALSE),
2092  RX_EN_IDLE_RESET_FR => (FALSE),
2093  RX_EN_IDLE_RESET_PH => (FALSE),
2094  TX_DETECT_RX_CFG => (x"1832"),
2095  TERMINATION_CTRL => ("00000"),
2096  TERMINATION_OVRD => (FALSE),
2097  CM_TRIM => ("01"),
2098  PMA_RXSYNC_CFG => (x"00"),
2099  PMA_CFG => (x"0040000040000000003"),
2100  BGTEST_CFG => ("00"),
2101  BIAS_CFG => (x"00000"),
2102 
2103  --------------RX Decision Feedback Equalizer(DFE)-------------
2104  DFE_CAL_TIME => ("01100"),
2105  DFE_CFG => ("00011011"),
2106  RX_EN_IDLE_HOLD_DFE => (TRUE),
2107  RX_EYE_OFFSET => (x"4C"),
2108  RX_EYE_SCANMODE => ("00"),
2109 
2110  -------------------------PRBS Detection-----------------------
2111  RXPRBSERR_LOOPBACK => ('0'),
2112 
2113  ------------------Comma Detection and Alignment---------------
2114  ALIGN_COMMA_WORD => (2),
2115  COMMA_10B_ENABLE => ("1111111111"),
2116  COMMA_DOUBLE => (FALSE),
2117  DEC_MCOMMA_DETECT => (TRUE),
2118  DEC_PCOMMA_DETECT => (TRUE),
2119  DEC_VALID_COMMA_ONLY => (TRUE),
2120  MCOMMA_10B_VALUE => ("1010000011"),
2121  MCOMMA_DETECT => (TRUE),
2122  PCOMMA_10B_VALUE => ("0101111100"),
2123  PCOMMA_DETECT => (TRUE),
2124  RX_DECODE_SEQ_MATCH => (TRUE),
2125  RX_SLIDE_AUTO_WAIT => (5),
2126  RX_SLIDE_MODE => ("OFF"),
2127  SHOW_REALIGN_COMMA => (FALSE),
2128 
2129  -----------------RX Loss-of-sync State Machine----------------
2130  RX_LOS_INVALID_INCR => (8),
2131  RX_LOS_THRESHOLD => (128),
2132  RX_LOSS_OF_SYNC_FSM => (FALSE),
2133 
2134  -------------------------RX Gearbox---------------------------
2135  RXGEARBOX_USE => (FALSE),
2136 
2137  -------------RX Elastic Buffer and Phase alignment------------
2138  RX_BUFFER_USE => (use_RX_elastic),
2139  RX_EN_IDLE_RESET_BUF => (TRUE),
2140  RX_EN_MODE_RESET_BUF => (TRUE),
2141  RX_EN_RATE_RESET_BUF => (TRUE),
2142  RX_EN_REALIGN_RESET_BUF => (FALSE),
2143  RX_EN_REALIGN_RESET_BUF2 => (FALSE),
2144  RX_FIFO_ADDR_MODE => ("FAST"),
2145  RX_IDLE_HI_CNT => ("1000"),
2146  RX_IDLE_LO_CNT => ("0000"),
2147  RX_XCLK_SEL => ("RXUSR"),
2148  RX_DLYALIGN_CTRINC => ("1110"),
2149  RX_DLYALIGN_EDGESET => ("00010"),
2150  RX_DLYALIGN_LPFINC => ("1110"),
2151  RX_DLYALIGN_MONSEL => ("000"),
2152  RX_DLYALIGN_OVRDSETTING => ("10000000"),
2153 
2154 
2155  ------------------------Clock Correction----------------------
2156  CLK_COR_ADJ_LEN => (1),
2157  CLK_COR_DET_LEN => (1),
2158  CLK_COR_INSERT_IDLE_FLAG => (FALSE),
2159  CLK_COR_KEEP_IDLE => (FALSE),
2160  CLK_COR_MAX_LAT => (3),--(16),
2161  CLK_COR_MIN_LAT => (3),--(14),
2162  CLK_COR_PRECEDENCE => (TRUE),
2163  CLK_COR_REPEAT_WAIT => (0),
2164  CLK_COR_SEQ_1_1 => ("0100000000"),
2165  CLK_COR_SEQ_1_2 => ("0000000000"),
2166  CLK_COR_SEQ_1_3 => ("0000000000"),
2167  CLK_COR_SEQ_1_4 => ("0000000000"),
2168  CLK_COR_SEQ_1_ENABLE => ("1111"),
2169  CLK_COR_SEQ_2_1 => ("0100000000"),
2170  CLK_COR_SEQ_2_2 => ("0000000000"),
2171  CLK_COR_SEQ_2_3 => ("0000000000"),
2172  CLK_COR_SEQ_2_4 => ("0000000000"),
2173  CLK_COR_SEQ_2_ENABLE => ("1111"),
2174  CLK_COR_SEQ_2_USE => (FALSE),
2175  CLK_CORRECT_USE => (FALSE),
2176 
2177  ------------------------Channel Bonding----------------------
2178  CHAN_BOND_1_MAX_SKEW => (1),
2179  CHAN_BOND_2_MAX_SKEW => (1),
2180  CHAN_BOND_KEEP_ALIGN => (FALSE),
2181  CHAN_BOND_SEQ_1_1 => ("0000000000"),
2182  CHAN_BOND_SEQ_1_2 => ("0000000000"),
2183  CHAN_BOND_SEQ_1_3 => ("0000000000"),
2184  CHAN_BOND_SEQ_1_4 => ("0000000000"),
2185  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
2186  CHAN_BOND_SEQ_2_1 => ("0000000000"),
2187  CHAN_BOND_SEQ_2_2 => ("0000000000"),
2188  CHAN_BOND_SEQ_2_3 => ("0000000000"),
2189  CHAN_BOND_SEQ_2_4 => ("0000000000"),
2190  CHAN_BOND_SEQ_2_CFG => ("00000"),
2191  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
2192  CHAN_BOND_SEQ_2_USE => (FALSE),
2193  CHAN_BOND_SEQ_LEN => (1),
2194  PCI_EXPRESS_MODE => (FALSE),
2195 
2196  -------------RX Attributes for PCI Express/SATA/SAS----------
2197  SAS_MAX_COMSAS => (52),
2198  SAS_MIN_COMSAS => (40),
2199  SATA_BURST_VAL => ("100"),
2200  SATA_IDLE_VAL => ("100"),
2201  SATA_MAX_BURST => (7),
2202  SATA_MAX_INIT => (22),
2203  SATA_MAX_WAKE => (7),
2204  SATA_MIN_BURST => (4),
2205  SATA_MIN_INIT => (12),
2206  SATA_MIN_WAKE => (4),
2207  TRANS_TIME_FROM_P2 => (x"03c"),
2208  TRANS_TIME_NON_P2 => (x"19"),
2209  TRANS_TIME_RATE => (x"ff"),
2210  TRANS_TIME_TO_P2 => (x"064")
2211 
2212 
2213  )
2214  port map
2215  (
2216  ------------------------ Loopback and Powerdown Ports ----------------------
2217  LOOPBACK => LOOPBACK ,
2218  RXPOWERDOWN => RXPOWERDOWN ,
2219  TXPOWERDOWN => "00",
2220  -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
2221  RXDATAVALID => open,
2222  RXGEARBOXSLIP => tied_to_ground_i,
2223  RXHEADER => open,
2224  RXHEADERVALID => open,
2225  RXSTARTOFSEQ => open,
2226  ----------------------- Receive Ports - 8b10b Decoder ----------------------
2227  RXCHARISCOMMA(3 downto 2) => rxchariscomma_float_i ((group_i*num_GTX_per_group)+gtx_i),
2228  RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA_OUT((group_i*num_GTX_per_group)+gtx_i),
2229  RXCHARISK(3 downto 2) => rxcharisk_float_i((group_i*num_GTX_per_group)+gtx_i),
2230  RXCHARISK(1 downto 0) => RXCHARISK_OUT((group_i*num_GTX_per_group)+gtx_i),
2231  RXDEC8B10BUSE => tied_to_vcc_i ,
2232  RXDISPERR(3 downto 2) => rxdisperr_float_i((group_i*num_GTX_per_group)+gtx_i),
2233  RXDISPERR(1 downto 0) => RXDISPERR_OUT((group_i*num_GTX_per_group)+gtx_i),
2234  RXNOTINTABLE(3 downto 2) => rxnotintable_float_i((group_i*num_GTX_per_group)+gtx_i),
2235  RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT((group_i*num_GTX_per_group)+gtx_i),
2236  RXRUNDISP => open,
2237  USRCODEERR => tied_to_ground_i,
2238  ------------------- Receive Ports - Channel Bonding Ports ------------------
2239  RXCHANBONDSEQ => open,
2240  RXCHBONDI => tied_to_ground_vec_i (3 downto 0),
2241  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
2242  RXCHBONDMASTER => tied_to_ground_i,
2243  RXCHBONDO => open,
2244  RXCHBONDSLAVE => tied_to_ground_i,
2245  RXENCHANSYNC => tied_to_ground_i,
2246  ------------------- Receive Ports - Clock Correction Ports -----------------
2247  RXCLKCORCNT => open,
2248  --------------- Receive Ports - Comma Detection and Alignment --------------
2249  RXBYTEISALIGNED => RXBYTEISALIGNED_OUT ((group_i*num_GTX_per_group)+gtx_i),
2250  RXBYTEREALIGN => RXBYTEREALIGN_OUT((group_i*num_GTX_per_group)+gtx_i),
2251  RXCOMMADET => RXCOMMADET_OUT((group_i*num_GTX_per_group)+gtx_i),
2252  RXCOMMADETUSE => tied_to_vcc_i,
2253  RXENMCOMMAALIGN => RXENMCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i),
2254  RXENPCOMMAALIGN => RXENPCOMMAALIGN_IN((group_i*num_GTX_per_group)+gtx_i),
2255  RXSLIDE => tied_to_ground_i,
2256  ----------------------- Receive Ports - PRBS Detection ---------------------
2257  PRBSCNTRESET => tied_to_ground_i,
2258  RXENPRBSTST => tied_to_ground_vec_i (2 downto 0),
2259  RXPRBSERR => open,
2260  ------------------- Receive Ports - RX Data Path interface -----------------
2261  RXDATA => rxdata_i((group_i*num_GTX_per_group)+gtx_i),
2262  RXRECCLK => RXRECCLK_OUT ((group_i*num_GTX_per_group)+gtx_i),
2263  RXRECCLKPCS => open,
2264  RXRESET => tied_to_ground_i,
2265  RXUSRCLK => tied_to_ground_i,
2266  RXUSRCLK2 => RXUSRCLK2_IN ((group_i*num_GTX_per_group)+gtx_i),
2267  ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
2268  DFECLKDLYADJ => DFECLKDLYADJ ((group_i*num_GTX_per_group)+gtx_i),
2269  DFECLKDLYADJMON => DFECLKDLYADJMON((group_i*num_GTX_per_group)+gtx_i),
2270  DFEDLYOVRD => DFEDLYOVRD((group_i*num_GTX_per_group)+gtx_i),
2271  DFEEYEDACMON => DFEEYEDACMON ((group_i*num_GTX_per_group)+gtx_i),
2272  DFESENSCAL => DFESENSCAL((group_i*num_GTX_per_group)+gtx_i),
2273  DFETAP1 => DFETAP1((group_i*num_GTX_per_group)+gtx_i),
2274  DFETAP1MONITOR => DFETAP1MONITOR((group_i*num_GTX_per_group)+gtx_i),
2275  DFETAP2 => DFETAP2((group_i*num_GTX_per_group)+gtx_i),
2276  DFETAP2MONITOR => DFETAP2MONITOR((group_i*num_GTX_per_group)+gtx_i),
2277  DFETAP3 => DFETAP3((group_i*num_GTX_per_group)+gtx_i),
2278  DFETAP3MONITOR => DFETAP3MONITOR((group_i*num_GTX_per_group)+gtx_i),
2279  DFETAP4 => DFETAP4((group_i*num_GTX_per_group)+gtx_i),
2280  DFETAP4MONITOR => DFETAP4MONITOR((group_i*num_GTX_per_group)+gtx_i),
2281  DFETAPOVRD => DFETAPOVRD((group_i*num_GTX_per_group)+gtx_i),
2282  ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
2283  GATERXELECIDLE => tied_to_vcc_i,
2284  IGNORESIGDET => tied_to_vcc_i,
2285  RXCDRRESET => tied_to_ground_i,
2286  RXELECIDLE => open,
2287  RXEQMIX(9 downto 3) => tied_to_ground_vec_i (6 downto 0),
2288  RXEQMIX(2 downto 0) => RXEQMIX_IN ((group_i*num_GTX_per_group)+gtx_i),
2289  RXN => RXN_IN((group_i*num_GTX_per_group)+gtx_i),
2290  RXP => RXP_IN((group_i*num_GTX_per_group)+gtx_i),
2291  -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
2292  RXBUFRESET => tied_to_ground_i,
2293  RXBUFSTATUS => RXBUFSTATUS_OUT((group_i*num_GTX_per_group)+gtx_i),
2294  RXCHANISALIGNED => open,
2295  RXCHANREALIGN => open,
2296  RXDLYALIGNDISABLE => RXDLYALIGNDISABLE_IN ((group_i*num_GTX_per_group)+gtx_i),
2297  RXDLYALIGNMONENB => RXDLYALIGNMONENB_IN ((group_i*num_GTX_per_group)+gtx_i),
2298  RXDLYALIGNMONITOR => RXDLYALIGNMONITOR_OUT ((group_i*num_GTX_per_group)+gtx_i),
2299  RXDLYALIGNOVERRIDE => RXDLYALIGNOVERRIDE_IN ((group_i*num_GTX_per_group)+gtx_i),
2300  RXDLYALIGNRESET => RXDLYALIGNRESET_IN((group_i*num_GTX_per_group)+gtx_i),
2301  RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
2302  RXDLYALIGNUPDSW => tied_to_ground_i,
2303  RXENPMAPHASEALIGN => RXENPMAPHASEALIGN_IN ((group_i*num_GTX_per_group)+gtx_i),
2304  RXPMASETPHASE => RXPMASETPHASE_IN((group_i*num_GTX_per_group)+gtx_i),
2305  RXSTATUS => open,
2306  --------------- Receive Ports - RX Loss-of-sync State Machine --------------
2307  RXLOSSOFSYNC => open,--RXLOSSOFSYNC_OUT((group_i*num_GTX_per_group)+gtx_i),
2308  ---------------------- Receive Ports - RX Oversampling ---------------------
2309  RXENSAMPLEALIGN => tied_to_ground_i,
2310  RXOVERSAMPLEERR => open,
2311  ------------------------ Receive Ports - RX PLL Ports ----------------------
2312  GREFCLKRX => tied_to_ground_i,
2313  GTXRXRESET => GTXRXRESET((group_i*num_GTX_per_group)+gtx_i),
2314  MGTREFCLKRX => MGTREFCLKRX_IN((group_i*num_GTX_per_group)+gtx_i),
2315  NORTHREFCLKRX => tied_to_ground_vec_i (1 downto 0),
2316  PERFCLKRX => tied_to_ground_i,
2317  PLLRXRESET => PLLRXRESET_IN ((group_i*num_GTX_per_group)+gtx_i),
2318  RXPLLLKDET => RXPLLLKDET_OUT((group_i*num_GTX_per_group)+gtx_i),
2319  RXPLLLKDETEN => tied_to_vcc_i,
2320  RXPLLPOWERDOWN => not_gen_RX,
2321  RXPLLREFSELDY => tied_to_ground_vec_i (2 downto 0),
2322  RXRATE => tied_to_ground_vec_i (1 downto 0),
2323  RXRATEDONE => open,
2324  RXRESETDONE => RXRESETDONE_OUT((group_i*num_GTX_per_group)+gtx_i),
2325  SOUTHREFCLKRX => tied_to_ground_vec_i (1 downto 0),
2326  -------------- Receive Ports - RX Pipe Control for PCI Express -------------
2327  PHYSTATUS => open,
2328  RXVALID => open,
2329  ----------------- Receive Ports - RX Polarity Control Ports ----------------
2330  RXPOLARITY => rx_polarity ((group_i*num_GTX_per_group)+gtx_i),
2331  --------------------- Receive Ports - RX Ports for SATA --------------------
2332  COMINITDET => open,
2333  COMSASDET => open,
2334  COMWAKEDET => open,
2335  ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
2336  DADDR => tied_to_ground_vec_i (7 downto 0),
2337  DCLK => tied_to_ground_i,
2338  DEN => tied_to_ground_i,
2339  DI => tied_to_ground_vec_i (15 downto 0),
2340  DRDY => open,
2341  DRPDO => open,
2342  DWE => tied_to_ground_i,
2343  -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
2344  TXGEARBOXREADY => open,
2345  TXHEADER => tied_to_ground_vec_i (2 downto 0),
2346  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
2347  TXSTARTSEQ => tied_to_ground_i,
2348  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
2349  TXBYPASS8B10B => tied_to_ground_vec_i (3 downto 0),
2350  TXCHARDISPMODE => tied_to_ground_vec_i (3 downto 0),
2351  TXCHARDISPVAL => tied_to_ground_vec_i (3 downto 0),
2352  TXCHARISK(3 downto 2) => tied_to_ground_vec_i (1 downto 0),
2353  TXCHARISK(1 downto 0) => TXCHARISK_IN ((group_i*num_GTX_per_group)+gtx_i),
2354  TXENC8B10BUSE => tied_to_vcc_i,
2355  TXKERR(3 downto 2) => TXKERR_OUT_UPPER ((group_i*num_GTX_per_group)+gtx_i),
2356  TXKERR(1 downto 0) => TXKERR_OUT ((group_i*num_GTX_per_group)+gtx_i),
2357  TXRUNDISP => open,
2358  ------------------------- Transmit Ports - GTX Ports -----------------------
2359  GTXTEST => "1000000000000",
2360  MGTREFCLKFAB => open,
2361  TSTCLK0 => tied_to_ground_i,
2362  TSTCLK1 => tied_to_ground_i,
2363  TSTIN => "11111111111111111111" ,
2364  TSTOUT => open,
2365  ------------------ Transmit Ports - TX Data Path interface -----------------
2366  TXDATA(15 downto 0) => TXDATA_IN ((group_i*num_GTX_per_group)+gtx_i),
2367  TXDATA(31 downto 16) => tied_to_ground_vec_i (15 downto 0),
2368 
2369  TXOUTCLK => TXOUTCLK_OUT ((group_i*num_GTX_per_group)+gtx_i),
2370  TXOUTCLKPCS => open,
2371  TXRESET => tied_to_ground_i,
2372  TXUSRCLK => tied_to_ground_i,
2373  TXUSRCLK2 => TXUSRCLK2_IN ((group_i*num_GTX_per_group)+gtx_i),
2374  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2375  TXBUFDIFFCTRL => "100",
2376  TXDIFFCTRL => TXDIFFCTRL_IN((group_i*num_GTX_per_group)+gtx_i),
2377  TXINHIBIT => tied_to_ground_i,
2378  TXN => TXN_OUT((group_i*num_GTX_per_group)+gtx_i),
2379  TXP => TXP_OUT((group_i*num_GTX_per_group)+gtx_i),
2380  TXPOSTEMPHASIS => TXPOSTEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i),
2381  --------------- Transmit Ports - TX Driver and OOB signalling --------------
2382  TXPREEMPHASIS => TXPREEMPHASIS_IN((group_i*num_GTX_per_group)+gtx_i),
2383  ----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
2384  TXBUFSTATUS => open,
2385  -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
2386  TXDLYALIGNDISABLE => TXDLYALIGNDISABLE_IN ((group_i*num_GTX_per_group)+gtx_i),
2387  TXDLYALIGNMONENB => TXDLYALIGNMONENB_IN ((group_i*num_GTX_per_group)+gtx_i),
2388  TXDLYALIGNMONITOR => TXDLYALIGNMONITOR_OUT ((group_i*num_GTX_per_group)+gtx_i),
2389  TXDLYALIGNOVERRIDE => tied_to_ground_i,
2390  TXDLYALIGNRESET => TXDLYALIGNRESET_IN((group_i*num_GTX_per_group)+gtx_i),
2391  TXDLYALIGNUPDSW => tied_to_ground_i,
2392  TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_IN ((group_i*num_GTX_per_group)+gtx_i),
2393  TXPMASETPHASE => TXPMASETPHASE_IN((group_i*num_GTX_per_group)+gtx_i),
2394  ----------------------- Transmit Ports - TX PLL Ports ----------------------
2395  GREFCLKTX => tied_to_ground_i,
2396  GTXTXRESET => GTXTXRESET((group_i*num_GTX_per_group)+gtx_i),
2397  MGTREFCLKTX => MGTREFCLKTX_IN((group_i*num_GTX_per_group)+gtx_i),
2398  NORTHREFCLKTX => tied_to_ground_vec_i (1 downto 0),
2399  PERFCLKTX => tied_to_ground_i,
2400  PLLTXRESET => PLLTXRESET_IN ((group_i*num_GTX_per_group)+gtx_i),
2401  SOUTHREFCLKTX => tied_to_ground_vec_i (1 downto 0),
2402  TXPLLLKDET => TXPLLLKDET_OUT((group_i*num_GTX_per_group)+gtx_i),
2403  TXPLLLKDETEN => tied_to_vcc_i,
2404  TXPLLPOWERDOWN => tied_to_ground_i,
2405  TXPLLREFSELDY => tied_to_ground_vec_i (2 downto 0),
2406  TXRATE => tied_to_ground_vec_i (1 downto 0),
2407  TXRATEDONE => open,
2408  TXRESETDONE => TXRESETDONE_OUT((group_i*num_GTX_per_group)+gtx_i),
2409  --------------------- Transmit Ports - TX PRBS Generator -------------------
2410  TXENPRBSTST => tied_to_ground_vec_i (2 downto 0),
2411  TXPRBSFORCEERR => tied_to_ground_i,
2412  -------------------- Transmit Ports - TX Polarity Control ------------------
2413  TXPOLARITY => tx_polarity ((group_i*num_GTX_per_group)+gtx_i),
2414  ----------------- Transmit Ports - TX Ports for PCI Express ----------------
2415  TXDEEMPH => tied_to_ground_i,
2416  TXDETECTRX => tied_to_ground_i,
2417  TXELECIDLE => tied_to_ground_i,
2418  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
2419  TXPDOWNASYNCH => tied_to_ground_i,
2420  TXSWING => tied_to_ground_i,
2421  --------------------- Transmit Ports - TX Ports for SATA -------------------
2422  COMFINISH => open,
2423  TXCOMINIT => tied_to_ground_i,
2424  TXCOMSAS => tied_to_ground_i,
2425  TXCOMWAKE => tied_to_ground_i
2426 
2427  );
2428 
2429  end generate MGT_gen_gtx;
2430  end generate MGT_gen_grp;
2431 
2432 end RTL;
2433 
Topo_Data_TX.RTL.DFETAP4
arr_4 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP4)
Definition: Topo_Data_TX.vhd:184
Topo_Data_TX.RTL.DFETAP3MONITOR
arr_4 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP3MONITOR)
Definition: Topo_Data_TX.vhd:183
Topo_Data_TX.TXN_OUT
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:36
Topo_Data_TX.RTL.rxcharisk_float_i
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) rxcharisk_float_i)
Definition: Topo_Data_TX.vhd:215
tx_sync.TXDLYALIGNRESET
out TXDLYALIGNRESETstd_logic
Definition: tx_sync.vhd:82
Topo_Data_TX.RTL.TXENPMAPHASEALIGN_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXENPMAPHASEALIGN_IN)
Definition: Topo_Data_TX.vhd:145
Topo_Data_TX.RTL.subtick_counter_rx
arr_ctr_3bit (num_GTX_groups * num_fifos_per_group - 1 downto 0) subtick_counter_rx)
Definition: Topo_Data_TX.vhd:101
Topo_Data_TX.RTL.rx_error_eventrealign_all
std_logic rx_error_eventrealign_all
Definition: Topo_Data_TX.vhd:119
and_all
Definition: and_all.vhd:28
Topo_Data_TX.RTL.RXRESETDONE_OUT_group
std_logic_vector (num_GTX_groups - 1 downto 0) RXRESETDONE_OUT_group
Definition: Topo_Data_TX.vhd:255
Topo_Data_TX.RTL.TXPLLLKDET_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXPLLLKDET_OUT)
Definition: Topo_Data_TX.vhd:151
or_all
Definition: or_all.vhd:28
Topo_Data_TX.RTL.vme_inreg_notri_async
vme_inreg_notri_async
Definition: Topo_Data_TX.vhd:461
Topo_Data_TX.RTL.ila_trigger_held20_all
std_logic ila_trigger_held20_all
Definition: Topo_Data_TX.vhd:772
Topo_Data_TX.RTL.time_multiplex_data_in
arr_time_multiplex_data_in (num_GTX_groups * num_fifos_per_group - 1 downto 0) time_multiplex_data_in)
Definition: Topo_Data_TX.vhd:93
Topo_Data_TX.RTL.c_tx_sync_done_grp_r
std_logic_vector (num_GTX_groups - 1 downto 0) c_tx_sync_done_grp_r
Definition: Topo_Data_TX.vhd:262
crc_check_inst
CRC_CHECK crc_check_instcrc_check_inst
Definition: Topo_Data_TX.vhd:1747
tx_sync.SYNC_DONE
out SYNC_DONEstd_logic
Definition: tx_sync.vhd:83
Topo_Data_TX.RTL.TXCHARISK_IN
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXCHARISK_IN)
Definition: Topo_Data_TX.vhd:128
vme_inreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:29
Topo_Data_TX.MGTREFCLK_PAD_N_IN
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:27
Topo_Data_TX.RTL.RXPLLLKDET_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXPLLLKDET_OUT)
Definition: Topo_Data_TX.vhd:204
Topo_Data_TX.RTL.TXDLYALIGNMONENB_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXDLYALIGNMONENB_IN)
Definition: Topo_Data_TX.vhd:142
Topo_Data_TX.RTL.RXBYTEREALIGN_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXBYTEREALIGN_OUT)
Definition: Topo_Data_TX.vhd:162
mini_fifo_synchroniser.set_mem_ctr_i_out
out set_mem_ctr_i_outstd_logic
Definition: mini_fifo_synchroniser.vhd:46
Topo_Data_TX.RTL.RXRECCLK_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXRECCLK_OUT)
Definition: Topo_Data_TX.vhd:169
Topo_Data_TX.RTL.c_tx_sync_done_grp_r_held20_r
std_logic_vector (num_GTX_groups - 1 downto 0) c_tx_sync_done_grp_r_held20_r
Definition: Topo_Data_TX.vhd:269
and_all_inst_tx
and_all and_all_inst_txand_all_inst_tx
Definition: Topo_Data_TX.vhd:1471
time_multiplex_8to1.BCID
in BCIDstd_logic_vector (11 downto 0)
Definition: time_multiplex_8to1.vhd:38
Topo_Data_TX.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:56
Topo_Data_TX.RTL.subtick_counter
arr_ctr_3bit (num_GTX_groups * num_fifos_per_group - 1 downto 0) subtick_counter)
Definition: Topo_Data_TX.vhd:96
Topo_Data_TX.RTL.RXRESETDONE_OUT_rr
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXRESETDONE_OUT_rr)
Definition: Topo_Data_TX.vhd:208
Topo_Data_TX.RTL.subtick_counter_rx_reg
arr_ctr_3bit (num_GTX_groups * num_fifos_per_group - 1 downto 0) subtick_counter_rx_reg)
Definition: Topo_Data_TX.vhd:99
rx_sync.USER_CLK
in USER_CLKstd_logic
Definition: rx_sync.vhd:82
rx_sync.RXPMASETPHASE
out RXPMASETPHASEstd_logic
Definition: rx_sync.vhd:77
Topo_Data_TX.RTL.RXBYTEISALIGNED_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXBYTEISALIGNED_OUT)
Definition: Topo_Data_TX.vhd:160
Topo_Data_TX.RTL.TXRESETDONE_OUT_rr
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXRESETDONE_OUT_rr)
Definition: Topo_Data_TX.vhd:244
Topo_Data_TX.RTL.q4_clk0_refclk_i
std_logic q4_clk0_refclk_i
Definition: Topo_Data_TX.vhd:75
rx_sync.SYNC_DONE
out SYNC_DONEstd_logic
Definition: rx_sync.vhd:81
Topo_Data_TX.RTL.tied_to_vcc_i
std_logic tied_to_vcc_i
Definition: Topo_Data_TX.vhd:231
mini_fifo.set_mem_ctr_i
in set_mem_ctr_istd_logic
Definition: mini_fifo.vhd:40
Topo_Data_TX.RTL.RXEQMIX_IN
arr_3 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXEQMIX_IN)
Definition: Topo_Data_TX.vhd:189
Topo_Data_TX.RTL.RXPLLLKDET_group
std_logic_vector (num_GTX_groups - 1 downto 0) RXPLLLKDET_group
Definition: Topo_Data_TX.vhd:235
Topo_Data_TX.RTL.RXBUFSTATUS_OUT
arr_3 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXBUFSTATUS_OUT)
Definition: Topo_Data_TX.vhd:199
Topo_Data_TX.RTL.long_counter
long_unsigned_array ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) long_counter)
Definition: Topo_Data_TX.vhd:249
Topo_Data_TX.RTL.keep
string keep
Definition: Topo_Data_TX.vhd:68
mmcm_adv_usrclk
mmcm_adv mmcm_adv_usrclkmmcm_adv_usrclk
Definition: Topo_Data_TX.vhd:1481
time_multiplex_8to1.work
_library_ workwork
Definition: time_multiplex_8to1.vhd:17
Topo_Data_TX.RTL.DFESENSCAL
arr_3 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFESENSCAL)
Definition: Topo_Data_TX.vhd:177
Topo_Data_TX.RTL.rxnotintable_float_i
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) rxnotintable_float_i)
Definition: Topo_Data_TX.vhd:217
Topo_Data_TX.RTL.time_multiplex_data_out_CRC
arr_time_multiplex_data_out (num_GTX_groups * num_fifos_per_group - 1 downto 0) time_multiplex_data_out_CRC)
Definition: Topo_Data_TX.vhd:95
Topo_Data_TX.rd_nwr
in rd_nwrstd_logic
Definition: Topo_Data_TX.vhd:53
vme_inreg_notri_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:34
mini_fifo.clk_i_dom
in clk_i_domstd_logic
Definition: mini_fifo.vhd:38
Topo_Data_TX.RTL.data_vme_from_below
arr_16 (5 downto 0) data_vme_from_below
Definition: Topo_Data_TX.vhd:457
Topo_Data_TX.RTL.time_multiplex_data_out
arr_time_multiplex_data_out (num_GTX_groups * num_fifos_per_group - 1 downto 0) time_multiplex_data_out)
Definition: Topo_Data_TX.vhd:94
tx_sync_i
tx_sync tx_sync_itx_sync_i
Definition: Topo_Data_TX.vhd:1763
Topo_Data_TX.RTL.rand
arr_24 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) rand)
Definition: Topo_Data_TX.vhd:480
vme_inreg_reg_rw_tx_polarity_1
vme_inreg_notri_async vme_inreg_reg_rw_tx_polarity_1vme_inreg_reg_rw_tx_polarity_1
Definition: Topo_Data_TX.vhd:1948
mini_fifo_synchroniser.set_mem_ctr_o_out
out set_mem_ctr_o_outstd_logic
Definition: mini_fifo_synchroniser.vhd:47
Topo_Data_TX.RTL.RXDLYALIGNMONITOR_OUT
arr_8 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXDLYALIGNMONITOR_OUT)
Definition: Topo_Data_TX.vhd:194
vme_inreg_notri_async.width
widthinteger :=16
Definition: vme_inreg_rtl_notri_async.vhd:21
Topo_Data_TX.RTL.set_mem_ctr_o
std_logic_vector (num_GTX_groups - 1 downto 0) set_mem_ctr_o
Definition: Topo_Data_TX.vhd:355
tx_sync.USER_CLK
in USER_CLKstd_logic
Definition: tx_sync.vhd:84
Topo_Data_TX.RTL.cTXPLLLKDET_group
std_logic_vector (num_GTX_groups - 1 downto 0) cTXPLLLKDET_group
Definition: Topo_Data_TX.vhd:236
Topo_Data_TX.RTL.tx_sync_done_grp_r
std_logic_vector (num_GTX_groups - 1 downto 0) tx_sync_done_grp_r
Definition: Topo_Data_TX.vhd:260
Topo_Data_TX.RTL.RXDLYALIGNDISABLE_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXDLYALIGNDISABLE_IN)
Definition: Topo_Data_TX.vhd:192
Topo_Data_TX.RTL.TXKERR_OUT
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXKERR_OUT)
Definition: Topo_Data_TX.vhd:129
Topo_Data_TX.RTL.MGTREFCLKTX_IN
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) MGTREFCLKTX_IN)
Definition: Topo_Data_TX.vhd:149
Topo_Data_TX.RTL.TXRESETDONE_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXRESETDONE_OUT)
Definition: Topo_Data_TX.vhd:152
tx_sync.TXENPMAPHASEALIGN
out TXENPMAPHASEALIGNstd_logic
Definition: tx_sync.vhd:79
Topo_Data_TX.RTL.rxchariscomma_float_i
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) rxchariscomma_float_i)
Definition: Topo_Data_TX.vhd:214
Topo_Data_TX.RTL.PLLTXRESET_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) PLLTXRESET_IN)
Definition: Topo_Data_TX.vhd:150
Topo_Data_TX
Definition: Topo_Data_TX.vhd:23
Topo_Data_TX.RTL.c_tx_sync_done_grp_shiftreg
arr_20 (num_GTX_groups - 1 downto 0) c_tx_sync_done_grp_shiftreg
Definition: Topo_Data_TX.vhd:263
Topo_Data_TX.RTL.rx_sync_done
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) rx_sync_done)
Definition: Topo_Data_TX.vhd:246
Topo_Data_TX.RTL.subtick_counter_rx_next
arr_ctr_3bit (num_GTX_groups * num_fifos_per_group - 1 downto 0) subtick_counter_rx_next)
Definition: Topo_Data_TX.vhd:102
Topo_Data_TX.RTL.DFEEYEDACMON
arr_5 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFEEYEDACMON)
Definition: Topo_Data_TX.vhd:176
Topo_Data_TX.RTL.wait_done
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) wait_done)
Definition: Topo_Data_TX.vhd:253
CRC_CHECK.rx_subtick_counter
in rx_subtick_counterunsigned (2 downto 0)
Definition: CRC_CHECK.vhd:33
Topo_Data_TX.RTL.RXCHARISK_OUT
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXCHARISK_OUT)
Definition: Topo_Data_TX.vhd:156
vme_local_switch.data_vme_from_below
in data_vme_from_belowarr_16
--! inputs from local registers and from
Definition: vme_local_switch.vhd:35
Topo_Data_TX.ds
in dsstd_logic
Definition: Topo_Data_TX.vhd:54
gtx0_rxsync_i
rx_sync gtx0_rxsync_igtx0_rxsync_i
Definition: Topo_Data_TX.vhd:1629
Topo_Data_TX.RTL.TXUSRCLK2_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXUSRCLK2_IN)
Definition: Topo_Data_TX.vhd:134
Topo_Data_TX.RTL.tx_polarity
std_logic_vector (47 downto 0) tx_polarity
Definition: Topo_Data_TX.vhd:485
Topo_Data_TX.RTL.rx_polarity
std_logic_vector (47 downto 0) rx_polarity
Definition: Topo_Data_TX.vhd:485
Topo_Data_TX.RTL.DFETAP4MONITOR
arr_4 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP4MONITOR)
Definition: Topo_Data_TX.vhd:185
Topo_Data_TX.RTL.TXUSRCLK2_IN_bufferedG
std_logic_vector (num_GTX_groups - 1 downto 0) TXUSRCLK2_IN_bufferedG
Definition: Topo_Data_TX.vhd:223
Topo_Data_TX.RTL.RXRESETDONE_OUT_rrr
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXRESETDONE_OUT_rrr)
Definition: Topo_Data_TX.vhd:209
mini_fifo_synchroniser.clk_o_dom
in clk_o_domstd_logic
Definition: mini_fifo_synchroniser.vhd:49
vme_inreg_notri_async.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:30
and_all_rxreset_done
and_all and_all_rxreset_doneand_all_rxreset_done
Definition: Topo_Data_TX.vhd:1580
Topo_Data_TX.send_align
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:41
and_all_tx_sync_done_grp
and_all and_all_tx_sync_done_grpand_all_tx_sync_done_grp
Definition: Topo_Data_TX.vhd:1831
Topo_Data_TX.RTL.refclk_i
std_logic_vector (num_GTX_groups - 1 downto 0) refclk_i
Definition: Topo_Data_TX.vhd:76
Topo_Data_TX.RTL.GTX_RX_READY_OUT_sig
std_logic GTX_RX_READY_OUT_sig
Definition: Topo_Data_TX.vhd:287
and_all.numbits
numbitsinteger :=2
Definition: and_all.vhd:31
Topo_Data_TX.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:57
Topo_Data_TX.RTL.rxdata_i
arr_2GTX_data rxdata_i
Definition: Topo_Data_TX.vhd:168
Topo_Data_TX.RTL.RXNOTINTABLE_OUT
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXNOTINTABLE_OUT)
Definition: Topo_Data_TX.vhd:158
Topo_Data_TX.RTL.TXDLYALIGNDISABLE_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXDLYALIGNDISABLE_IN)
Definition: Topo_Data_TX.vhd:141
vme_inreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri_async.vhd:20
time_multiplex_8to1
Definition: time_multiplex_8to1.vhd:30
Topo_Data_TX.RTL.rx_error_byterealign
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) rx_error_byterealign)
Definition: Topo_Data_TX.vhd:108
vme_inreg_reg_rw_tx_polarity_2
vme_inreg_notri_async vme_inreg_reg_rw_tx_polarity_2vme_inreg_reg_rw_tx_polarity_2
Definition: Topo_Data_TX.vhd:1963
rx_sync.RESET
in RESETstd_logic
Definition: rx_sync.vhd:83
mini_fifo.DATA_in
in DATA_instd_logic_vector (numbits - 1 downto 0)
Definition: mini_fifo.vhd:36
rx_sync.RXDLYALIGNDISABLE
out RXDLYALIGNDISABLEstd_logic
Definition: rx_sync.vhd:78
tx_sync.TXPMASETPHASE
out TXPMASETPHASEstd_logic
Definition: tx_sync.vhd:80
mini_fifo.clk_o_dom
in clk_o_domstd_logic
Definition: mini_fifo.vhd:39
and_all.DATA
in DATAstd_logic_vector (numbits - 1 downto 0)
Definition: and_all.vhd:34
time_multiplex_8to1.send_align
in send_alignstd_logic
Definition: time_multiplex_8to1.vhd:37
or_all_c_tx_sync_done_grp_shiftreg
or_all or_all_c_tx_sync_done_grp_shiftregor_all_c_tx_sync_done_grp_shiftreg
Definition: Topo_Data_TX.vhd:1180
Topo_Data_TX.RTL.short_counter_next
short_unsigned_array (num_GTX_groups - 1 downto 0) short_counter_next
Definition: Topo_Data_TX.vhd:252
Topo_Data_TX.RTL.cRXPLLLKDET_group
std_logic_vector (num_GTX_groups - 1 downto 0) cRXPLLLKDET_group
Definition: Topo_Data_TX.vhd:237
Topo_Data_TX.RTL.bus_drive_from_below
std_logic_vector (5 downto 0) bus_drive_from_below
Definition: Topo_Data_TX.vhd:458
Topo_Data_TX.RTL.rx_error_not_in_table
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) rx_error_not_in_table)
Definition: Topo_Data_TX.vhd:107
Topo_Data_TX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:32
time_multiplex_8to1.pll_locked
in pll_lockedstd_logic
Definition: time_multiplex_8to1.vhd:43
vme_inreg_notri_async.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:25
time_multiplex_8to1.subtick_counter_out
out subtick_counter_outunsigned (2 downto 0)
Definition: time_multiplex_8to1.vhd:40
Topo_Data_TX.RTL.TXPLLLKDET_group
std_logic_vector (num_GTX_groups - 1 downto 0) TXPLLLKDET_group
Definition: Topo_Data_TX.vhd:234
Topo_Data_TX.RTL.long_counter_next
long_unsigned_array ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) long_counter_next)
Definition: Topo_Data_TX.vhd:251
CRC_CHECK.DATA_in
in DATA_instd_logic_vector (15 downto 0)
Definition: CRC_CHECK.vhd:30
Topo_Data_TX.RTL.RXBYTEISALIGNED_OUT_r
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXBYTEISALIGNED_OUT_r)
Definition: Topo_Data_TX.vhd:161
vme_inreg_reg_rw_rx_polarity_1
vme_inreg_notri_async vme_inreg_reg_rw_rx_polarity_1vme_inreg_reg_rw_rx_polarity_1
Definition: Topo_Data_TX.vhd:1901
or_all.or_all
out or_allstd_logic
Definition: or_all.vhd:35
tx_sync.RESET
in RESETstd_logic
Definition: tx_sync.vhd:85
Topo_Data_TX.RTL.RXDLYALIGNMONENB_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXDLYALIGNMONENB_IN)
Definition: Topo_Data_TX.vhd:193
Topo_Data_TX.RTL.TXDATA_IN
arr_GTX_data TXDATA_IN
Definition: Topo_Data_TX.vhd:132
Topo_Data_TX.RTL.tx_sync_done_grp
std_logic_vector (num_GTX_groups - 1 downto 0) tx_sync_done_grp
Definition: Topo_Data_TX.vhd:259
or_all.numbits
numbitsinteger :=2
Definition: or_all.vhd:31
Topo_Data_TX.RTL.RXCOMMADET_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXCOMMADET_OUT)
Definition: Topo_Data_TX.vhd:163
CRC_CHECK.CRC_ERR
out CRC_ERRstd_logic
Definition: CRC_CHECK.vhd:31
Topo_Data_TX.RTL.TXUSRCLK2_IN_unbuffered
std_logic_vector (num_GTX_groups - 1 downto 0) TXUSRCLK2_IN_unbuffered
Definition: Topo_Data_TX.vhd:222
Topo_Data_TX.RTL.RXENPCOMMAALIGN_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXENPCOMMAALIGN_IN)
Definition: Topo_Data_TX.vhd:165
vme_inreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:35
Topo_Data_TX.RTL.TXRESETDONE_OUT_r
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXRESETDONE_OUT_r)
Definition: Topo_Data_TX.vhd:243
Topo_Data_TX.RTL.RXRESETDONE_OUT_r
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXRESETDONE_OUT_r)
Definition: Topo_Data_TX.vhd:207
clkout0_bufg_i
bufg clkout0_bufg_iclkout0_bufg_i
Definition: Topo_Data_TX.vhd:1538
Topo_Data_TX.RTL.RXRESETDONE_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXRESETDONE_OUT)
Definition: Topo_Data_TX.vhd:205
Topo_Data_TX.RTL.ila_trigger_held20
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) ila_trigger_held20)
Definition: Topo_Data_TX.vhd:771
tx_sync
Definition: tx_sync.vhd:72
Topo_Data_TX.GTXRXRESET_IN
in GTXRXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:30
Topo_Data_TX.MGTREFCLK_PAD_P_IN
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:28
vme_local_switch.data_vme_up
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
Definition: vme_local_switch.vhd:24
tx_sync.SIM_TXPMASETPHASE_SPEEDUP
SIM_TXPMASETPHASE_SPEEDUPinteger :=0
Definition: tx_sync.vhd:75
Topo_Data_TX.RTL.subtick_counter_rx_started
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) subtick_counter_rx_started)
Definition: Topo_Data_TX.vhd:103
Topo_Data_TX.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:55
Topo_Data_TX.RTL.DFETAP1
arr_5 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP1)
Definition: Topo_Data_TX.vhd:178
Topo_Data_TX.RTL.TXDIFFCTRL_IN
arr_4 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXDIFFCTRL_IN)
Definition: Topo_Data_TX.vhd:136
Topo_Data_TX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:31
Topo_Data_TX.RTL.RXCHARISCOMMA_OUT
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXCHARISCOMMA_OUT)
Definition: Topo_Data_TX.vhd:155
Topo_Data_TX.RTL.short_counter
short_unsigned_array (num_GTX_groups - 1 downto 0) short_counter
Definition: Topo_Data_TX.vhd:250
Topo_Data_TX.RTL.TXPMASETPHASE_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXPMASETPHASE_IN)
Definition: Topo_Data_TX.vhd:146
vme_inreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri_async.vhd:32
Topo_Data_TX.RTL.rx_error_disparity_all
std_logic rx_error_disparity_all
Definition: Topo_Data_TX.vhd:120
gtxe1_i
gtxe1 gtxe1_igtxe1_i
Definition: Topo_Data_TX.vhd:1985
rxrecclk_bufr1_i
bufr rxrecclk_bufr1_irxrecclk_bufr1_i
Definition: Topo_Data_TX.vhd:1444
Topo_Data_TX.RTL.GTXRXRESET
STD_LOGIC_VECTOR ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) GTXRXRESET)
Definition: Topo_Data_TX.vhd:767
Topo_Data_TX.RTL.RXDATA_OUT
arr_GTX_data RXDATA_OUT
Definition: Topo_Data_TX.vhd:167
rx_sync.RXENPMAPHASEALIGN
out RXENPMAPHASEALIGNstd_logic
Definition: rx_sync.vhd:76
Topo_Data_TX.RTL.fifo_dout
std_logic_vector (num_GTX_groups * num_GTX_per_group * (GTX_data_word_width + 2) - 1 downto 0) fifo_dout)
Definition: Topo_Data_TX.vhd:90
Topo_Data_TX.RTL.c_tx_sync_done_grp
std_logic_vector (num_GTX_groups - 1 downto 0) c_tx_sync_done_grp
Definition: Topo_Data_TX.vhd:261
Topo_Data_TX.ext_trigger
in ext_triggerstd_logic
Definition: Topo_Data_TX.vhd:50
mini_fifo_i
mini_fifo mini_fifo_imini_fifo_i
Definition: Topo_Data_TX.vhd:1245
rx_sync.RXDLYALIGNOVERRIDE
out RXDLYALIGNOVERRIDEstd_logic
Definition: rx_sync.vhd:79
vme_local_switch
Definition: vme_local_switch.vhd:22
Topo_Data_TX.RTL.reset_rx_sync
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) reset_rx_sync)
Definition: Topo_Data_TX.vhd:241
Topo_Data_TX.RTL.BUFFER_TYPE
string BUFFER_TYPE
Definition: Topo_Data_TX.vhd:70
Topo_Data_TX.TXP_OUT
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:37
Topo_Data_TX.RTL.RXENMCOMMAALIGN_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXENMCOMMAALIGN_IN)
Definition: Topo_Data_TX.vhd:164
and_all_rx_aligned
and_all and_all_rx_alignedand_all_rx_aligned
Definition: Topo_Data_TX.vhd:1872
rx_sync
Definition: rx_sync.vhd:73
Topo_Data_TX.RTL.DFETAP2MONITOR
arr_5 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP2MONITOR)
Definition: Topo_Data_TX.vhd:181
vme_inreg_reg_rw_rx_polarity_0
vme_inreg_notri_async vme_inreg_reg_rw_rx_polarity_0vme_inreg_reg_rw_rx_polarity_0
Definition: Topo_Data_TX.vhd:1886
Topo_Data_TX.RTL.RXDISPERR_OUT
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXDISPERR_OUT)
Definition: Topo_Data_TX.vhd:157
vme_local_switch.bus_drive_up
out bus_drive_upstd_logic
or of all bus drive requests from below
Definition: vme_local_switch.vhd:38
Topo_Data_TX.RTL.RXENPMAPHASEALIGN_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXENPMAPHASEALIGN_IN)
Definition: Topo_Data_TX.vhd:197
Topo_Data_TX.RTL.tx_sync_done
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) tx_sync_done)
Definition: Topo_Data_TX.vhd:247
Topo_Data_TX.RTL.vme_local_switch
vme_local_switch
Definition: Topo_Data_TX.vhd:448
Topo_Data_TX.RTL.rx_error_crc_all
std_logic rx_error_crc_all
Definition: Topo_Data_TX.vhd:121
Topo_Data_TX.RTL.DFETAP2
arr_5 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP2)
Definition: Topo_Data_TX.vhd:180
Topo_Data_TX.RTL.DFETAP1MONITOR
arr_5 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP1MONITOR)
Definition: Topo_Data_TX.vhd:179
time_multiplex_8to1.DATA_in
in DATA_instd_logic_vector (16 * 8 - 1 downto 0)
Definition: time_multiplex_8to1.vhd:36
vme_inreg_reg_rw_tx_polarity_0
vme_inreg_notri_async vme_inreg_reg_rw_tx_polarity_0vme_inreg_reg_rw_tx_polarity_0
Definition: Topo_Data_TX.vhd:1933
mini_fifo.set_mem_ctr_o
in set_mem_ctr_ostd_logic
Definition: mini_fifo.vhd:41
time_multiplex_8to1.clk_fast
in clk_faststd_logic
Definition: time_multiplex_8to1.vhd:42
Topo_Data_TX.RTL.q1_clk0_refclk_i
std_logic q1_clk0_refclk_i
Definition: Topo_Data_TX.vhd:74
mini_fifo_synchroniser
Definition: mini_fifo_synchroniser.vhd:44
Topo_Data_TX.RTL.PLLRXRESET_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) PLLRXRESET_IN)
Definition: Topo_Data_TX.vhd:203
Topo_Data_TX.RTL.DFECLKDLYADJMON
arr_6 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFECLKDLYADJMON)
Definition: Topo_Data_TX.vhd:174
Topo_Data_TX.RTL.rx_error_crc
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) rx_error_crc)
Definition: Topo_Data_TX.vhd:111
Topo_Data_TX.ncs
in ncsstd_logic
Definition: Topo_Data_TX.vhd:52
CRC_CHECK
Definition: CRC_CHECK.vhd:28
and_all_inst_rx
and_all and_all_inst_rxand_all_inst_rx
Definition: Topo_Data_TX.vhd:1460
Topo_Data_TX.RTL.DFETAPOVRD
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAPOVRD)
Definition: Topo_Data_TX.vhd:186
or_all.DATA
in DATAstd_logic_vector (numbits - 1 downto 0)
Definition: or_all.vhd:34
Topo_Data_TX.clk320
in clk320std_logic
Definition: Topo_Data_TX.vhd:39
time_multiplex_8to1.IEEE
_library_ IEEEIEEE
Definition: time_multiplex_8to1.vhd:14
and_all_tx_sync_done
and_all and_all_tx_sync_doneand_all_tx_sync_done
Definition: Topo_Data_TX.vhd:1851
Topo_Data_TX.RTL.SIM_GTXRESET_SPEEDUP
integer :=0 SIM_GTXRESET_SPEEDUP
Definition: Topo_Data_TX.vhd:482
vme_inreg_notri_async.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:27
vme_inreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:26
Topo_Data_TX.RTL.tied_to_ground_i
std_logic tied_to_ground_i
Definition: Topo_Data_TX.vhd:229
Topo_Data_TX.RTL.RXUSRCLK2_IN_bufferedR
std_logic_vector (num_GTX_groups - 1 downto 0) RXUSRCLK2_IN_bufferedR
Definition: Topo_Data_TX.vhd:224
vme_inreg_notri_async.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:31
mini_fifo
Definition: mini_fifo.vhd:30
time_multiplex_i
time_multiplex_8to1 time_multiplex_itime_multiplex_i
Definition: Topo_Data_TX.vhd:1227
Topo_Data_TX.RTL.TXPREEMPHASIS_IN
arr_4 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXPREEMPHASIS_IN)
Definition: Topo_Data_TX.vhd:139
crc_calc_inst
crc_calc crc_calc_instcrc_calc_inst
Definition: Topo_Data_TX.vhd:1238
Topo_Data_TX.indata
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
Definition: Topo_Data_TX.vhd:48
mini_fifo.DATA_out
out DATA_outstd_logic_vector (numbits - 1 downto 0)
Definition: mini_fifo.vhd:37
Topo_Data_TX.RTL.set_mem_ctr_i
std_logic_vector (num_GTX_groups - 1 downto 0) set_mem_ctr_i
Definition: Topo_Data_TX.vhd:355
Topo_Data_TX.RTL.GTXTXRESET
STD_LOGIC_VECTOR ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) GTXTXRESET)
Definition: Topo_Data_TX.vhd:768
Topo_Data_TX.RTL.TXOUTCLK_OUT
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXOUTCLK_OUT)
Definition: Topo_Data_TX.vhd:133
Topo_Data_TX.RTL.MGTREFCLKRX_IN
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) MGTREFCLKRX_IN)
Definition: Topo_Data_TX.vhd:202
Topo_Data_TX.BCID
in BCIDstd_logic_vector (11 downto 0)
Definition: Topo_Data_TX.vhd:42
and_all.and_all
out and_allstd_logic
Definition: and_all.vhd:35
Topo_Data_TX.RTL.tied_to_ground_vec_i
std_logic_vector (63 downto 0) tied_to_ground_vec_i
Definition: Topo_Data_TX.vhd:230
Topo_Data_TX.RTL.RXDATA_OUT_reg
arr_GTX_data RXDATA_OUT_reg
Definition: Topo_Data_TX.vhd:98
Topo_Data_TX.RTL.TXKERR_OUT_UPPER
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXKERR_OUT_UPPER)
Definition: Topo_Data_TX.vhd:130
Topo_Data_TX.bus_drive
out bus_drivestd_logic
Definition: Topo_Data_TX.vhd:58
Topo_Data_TX.RTL.TXDLYALIGNMONITOR_OUT
arr_8 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXDLYALIGNMONITOR_OUT)
Definition: Topo_Data_TX.vhd:143
time_multiplex_8to1.DATA_out
out DATA_outstd_logic_vector (17 downto 0)
Definition: time_multiplex_8to1.vhd:39
Topo_Data_TX.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:34
Topo_Data_TX.RTL.reset_tx_sync
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) reset_tx_sync)
Definition: Topo_Data_TX.vhd:240
Topo_Data_TX.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:35
CRC_CHECK.clk
in clkstd_logic
Definition: CRC_CHECK.vhd:32
Topo_Data_TX.RTL.RXPMASETPHASE_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXPMASETPHASE_IN)
Definition: Topo_Data_TX.vhd:198
vme_inreg_reg_rw_rx_polarity_2
vme_inreg_notri_async vme_inreg_reg_rw_rx_polarity_2vme_inreg_reg_rw_rx_polarity_2
Definition: Topo_Data_TX.vhd:1916
tx_sync.TXDLYALIGNDISABLE
out TXDLYALIGNDISABLEstd_logic
Definition: tx_sync.vhd:81
Topo_Data_TX.RTL.rx_error_not_in_table_all
std_logic rx_error_not_in_table_all
Definition: Topo_Data_TX.vhd:117
Topo_Data_TX.RTL.TXDLYALIGNRESET_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXDLYALIGNRESET_IN)
Definition: Topo_Data_TX.vhd:144
CMX_VME_defs
test registers
Definition: CMX_VME_defs.vhd:13
Topo_Data_TX.RTL.TXPOSTEMPHASIS_IN
arr_5 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) TXPOSTEMPHASIS_IN)
Definition: Topo_Data_TX.vhd:137
q1_clk0_refclk_ibufds_i
ibufds_gtxe1 q1_clk0_refclk_ibufds_iq1_clk0_refclk_ibufds_i
Definition: Topo_Data_TX.vhd:1369
Topo_Data_TX.RTL.rx_error_any
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) rx_error_any)
Definition: Topo_Data_TX.vhd:113
mini_fifo_synchroniser.set
in setstd_logic
Definition: mini_fifo_synchroniser.vhd:50
mini_fifo.numbits
numbitsinteger :=TX_fifo_indata_length
Definition: mini_fifo.vhd:33
Topo_Data_TX.RTL.c_tx_sync_done_grp_r_held20
std_logic_vector (num_GTX_groups - 1 downto 0) c_tx_sync_done_grp_r_held20
Definition: Topo_Data_TX.vhd:265
mini_fifo_synchroniser.clk_i_dom
in clk_i_domstd_logic
Definition: mini_fifo_synchroniser.vhd:48
Topo_Data_TX.RTL.rx_error_eventrealign
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) rx_error_eventrealign)
Definition: Topo_Data_TX.vhd:109
Topo_Data_TX.RTL.RXDLYALIGNOVERRIDE_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXDLYALIGNOVERRIDE_IN)
Definition: Topo_Data_TX.vhd:195
Topo_Data_TX.clk40
in clk40std_logic
Definition: Topo_Data_TX.vhd:38
Topo_Data_TX.pll_locked
in pll_lockedstd_logic
Definition: Topo_Data_TX.vhd:40
time_multiplex_8to1.clk_slow
in clk_slowstd_logic
Definition: time_multiplex_8to1.vhd:41
mini_fifo_synchroniser_i
mini_fifo_synchroniser mini_fifo_synchroniser_imini_fifo_synchroniser_i
Definition: Topo_Data_TX.vhd:1212
Topo_Data_TX.RTL.RXDLYALIGNRESET_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXDLYALIGNRESET_IN)
Definition: Topo_Data_TX.vhd:196
Topo_Data_TX.RTL.ila_trigger_shiftreg
arr_20 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) ila_trigger_shiftreg)
Definition: Topo_Data_TX.vhd:770
Topo_Data_TX.RTL.RXUSRCLK2_IN
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXUSRCLK2_IN)
Definition: Topo_Data_TX.vhd:170
Topo_Data_TX.RTL.rx_error_disparity
std_logic_vector (num_GTX_groups * num_fifos_per_group - 1 downto 0) rx_error_disparity)
Definition: Topo_Data_TX.vhd:110
Topo_Data_TX.RTL.mmcm_locked
std_logic_vector (num_GTX_groups - 1 downto 0) mmcm_locked
Definition: Topo_Data_TX.vhd:225
Topo_Data_TX.GTXTXRESET_IN
in GTXTXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:29
Topo_Data_TX.RTL.rxdisperr_float_i
arr_2 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) rxdisperr_float_i)
Definition: Topo_Data_TX.vhd:216
Topo_Data_TX.RTL.rx_error_byterealign_all
std_logic rx_error_byterealign_all
Definition: Topo_Data_TX.vhd:118
Topo_Data_TX.RTL.RXRESETDONE_OUT_rrrr
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) RXRESETDONE_OUT_rrrr)
Definition: Topo_Data_TX.vhd:210
Topo_Data_TX.RTL.DFEDLYOVRD
std_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFEDLYOVRD)
Definition: Topo_Data_TX.vhd:175
rx_sync.RXDLYALIGNRESET
out RXDLYALIGNRESETstd_logic
Definition: rx_sync.vhd:80
Topo_Data_TX.RTL.mmcm_fback
std_logic_vector (num_GTX_groups - 1 downto 0) mmcm_fback
Definition: Topo_Data_TX.vhd:221
vme_local_switch.bus_drive_from_below
in bus_drive_from_belowstd_logic_vector
Definition: vme_local_switch.vhd:40
Topo_Data_TX.RTL.DFETAP3
arr_4 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFETAP3)
Definition: Topo_Data_TX.vhd:182
Topo_Data_TX.RTL.DFECLKDLYADJ
arr_6 ((num_GTX_per_group * num_GTX_groups) - 1 downto 0) DFECLKDLYADJ)
Definition: Topo_Data_TX.vhd:173
vme_inreg_notri_async
Definition: vme_inreg_rtl_notri_async.vhd:18