time_multiplex_8to1.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity time_multiplex_8to1 is
  ---generic
  ---  (
  ---    ratio    : integer    := 8        -- input length : output length ratio
  ---    );
  port (
    DATA_in         : in  std_logic_vector(16*8-1 downto 0);
    send_align : in std_logic;
    BCID       : in std_logic_vector(11 downto 0);
    DATA_out        : out std_logic_vector(17 downto 0);
    subtick_counter_out  : out unsigned(2 downto 0);
    clk_slow       : in std_logic;      -- DATA_in is synced to this clock
    clk_fast       : in std_logic;      -- DATA_out is synced to this clock
    pll_locked     : in std_logic);      -- from the MMCM; used to define when
                                        -- to start 
end time_multiplex_8to1;

architecture Behavioral of time_multiplex_8to1 is

  signal subtick_counter : unsigned(2 downto 0);
  signal subtick_counter_next : unsigned(2 downto 0);

 
  signal pll_locked_s1, pll_locked_synced : std_logic;

  signal DATA_out_next : std_logic_vector(16 downto 0);

  signal send_align_reg : std_logic;

  --the select signal that combines the send_align bit and the subtick counter
  signal sel: std_logic_vector(3 downto 0);
  
begin

  DATA_out(17)<='0'; --the K character only possibly appears on the LS byte.
                     --never on the higher byte so the flag for the 

  subtick_counter_next<=subtick_counter+1;


  --combine the two signals into one as the input to the multiplexer
  sel<=send_align_reg& std_logic_vector(subtick_counter);


  --normally when no align data is to be sent the multiplexer picks off the
  --successive chunks of the input data starting with the MS word '0' is added
  --in the front to signify that the data (lower byte) is not a K character
  --however when the align bit is set first 3 words are the same but then
  --a K character is spliced in in st 3 and BCID on st 4, the rest of the data
  --is zeroed
  with sel select
    DATA_out_next <=
    ('0' & DATA_in( 8*16 - 1 downto 7*16))                when "0000",  --subtick: 0 --send_align from previous event
    ('0' & DATA_in( 8*16 - 1 downto 7*16))                when "1000",               --but thats ok sice 
    ('0' & DATA_in( 7*16 - 1 downto 6*16))                when "0001",  --subtick: 1 --till subtick 3 no difference
    ('0' & DATA_in( 7*16 - 1 downto 6*16))                when "1001",               --still old send_align_reg
    ('0' & DATA_in( 6*16 - 1 downto 5*16))                when "0010",  --subtick: 2
    ('0' & DATA_in( 6*16 - 1 downto 5*16))                when "1010",               --still old send_align_reg
    ('0' & DATA_in( 5*16 - 1 downto 4*16))                when "0011",  --subtick: 3
    ('1' & DATA_in( 5*16 - 1 downto 4*16+8) & "10111100") when "1011",  --add K
    ('0' & DATA_in( 4*16 - 1 downto 3*16))                when "0100",  --subtick: 4
    ('0' & BCID & DATA_in( 3*16 + 3 downto 3*16))         when "1100",  --add BCID
    ('0' & DATA_in( 3*16 - 1 downto 2*16))                when "0101",  --subtick: 5
    ('0' & DATA_in( 3*16 - 1 downto 2*16))                when "1101",  --continue sending
    ('0' & DATA_in( 2*16 - 1 downto 1*16))                when "0110",  --subtick: 6
    ('0' & DATA_in( 2*16 - 1 downto 1*16))                when "1110",  
    ('0' & DATA_in( 1*16 - 1 downto 0*16))                when "0111",  --subtick: 7
    ('0' & DATA_in( 1*16 - 1 downto 0*16))                when "1111";  
    
  --process to sync the pll locked signal to the clk_slow
  process (clk_slow, pll_locked)
  begin  -- process
    if pll_locked = '0' then
      pll_locked_s1<='0';
      pll_locked_synced<='0';
    elsif rising_edge(clk_slow) then
      pll_locked_synced<=pll_locked_s1;
      pll_locked_s1<='1';
    end if;
  end process;


  
  
  --process to select a range of the input data and register it into the output
  --data
  process(clk_fast,pll_locked_synced)
  begin
    if rising_edge(clk_fast) then
      if pll_locked_synced /= '1' then
        subtick_counter<=to_unsigned(0,3);
        DATA_out(16 downto 0)<=(others => '0');
        send_align_reg<='0';
      else
        DATA_out(16 downto 0) <= DATA_out_next;
        subtick_counter<=subtick_counter_next;
        if subtick_counter=to_unsigned(2,3) then  --note the 2; alignment word is not used till second half of the serialisation 
          send_align_reg<=send_align;
        end if;
      end if;
    end if;
  end process;

  subtick_counter_out<=subtick_counter;
    
end Behavioral;