CMX_system_cable_input_module.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMX_local_package.all;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;


entity CMX_system_cable_input_module is 

  port(
    --data in ds2 domain, *2 because data is DDR
    data : out std_logic_vector( numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
    parity_error_total : out std_logic;
    ddr_data_in : in arr_RTM(num_RTM_cables-1 downto 0);
    buf_clk40 : in std_logic;
    buf_clk40_ds2 : in std_logic;
    pll_locked : in std_logic;
    pll_locked_ds2 : in std_logic;
    quiet : in std_logic;
    start_playback : in std_logic;
    --inhibit signal for writing to the spy memories
    spy_write_inhibit : in std_logic;
    --VME control:
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;
    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
        
end CMX_system_cable_input_module;


architecture Behavioral of CMX_system_cable_input_module is

  constant mem_select_addr_width : integer := addr_port_width(num_RTM_cables);

  component CMX_cable_clocked_80Mbps_input_module is
    generic (
      numbits_in_cable_connector : integer);
    port (
      data            : out std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
      parity_error    : out std_logic;
      forwarded_clock : out std_logic;
      ddr_data_in     : in  std_logic_vector(numbits_in_cable_connector downto 0);
      buf_clk40       : in  std_logic;
      buf_clk200      : in  std_logic;
      pll_locked      : in  std_logic;
      del_array       : in  cable_del_array_type(numbits_in_cable_connector downto 0);
      upload_delays   : in  std_logic);
  end component CMX_cable_clocked_80Mbps_input_module;


  signal data_sdr_unmasked              : arr_RTM_sdr;
  signal data_sdr                       : arr_RTM_sdr;
  signal data_sdr_r_SOURCE              : arr_RTM_sdr;
  signal data_sdr_r_SYSTEMDS2           : arr_RTM_sdr;
  signal data_sdr_rr_SYSTEMDS2          : arr_RTM_sdr; --need this for
                                                       --comparison to data
                                                       --from RAM
  
  signal data_DS2           : arr_RTM_sdr;      --output of the DS2 domain
  
  signal data_DS2_r_SYSTEM  : arr_RTM_sdr;
  signal data_DS2_rr_SYSTEM  : arr_RTM_sdr; --again needed for comparison in
                                            --VERIFY mode

  signal ch_quiet : std_logic_vector(num_RTM_cables-1 downto 0);

  signal channel_mask : std_logic_vector(num_RTM_cables-1 downto 0);
  
  --parity error calculated using the forwarded clock
  signal parity_error_unmasked_sig       : std_logic_vector(num_RTM_cables -1 downto 0);
  signal parity_error_sig       : std_logic_vector(num_RTM_cables -1 downto 0);
  --then registered in the ds2 an ds1 system domains
  signal parity_error_r_SYSTEMDS2    : std_logic_vector(num_RTM_cables -1 downto 0);
  signal parity_error_r_SYSTEMDS2_r_SYSTEM       : std_logic_vector(num_RTM_cables -1 downto 0);
  signal parity_error_r_SYSTEMDS2_rr_SYSTEM      : std_logic_vector(num_RTM_cables -1 downto 0);

  -- --parity error calculated from data captured in respective domains
  -- signal parity_error_c_SYSTEMDS2    : std_logic_vector(num_RTM_cables -1 downto 0);
  -- signal parity_error_c_SYSTEM       : std_logic_vector(num_RTM_cables -1 downto 0);

  
  signal forwarded_clock : std_logic_vector(num_RTM_cables - 1 downto 0);
  

  component blk_mem_A8x52_B8x52_2clock is
    port (
      clka  : IN  STD_LOGIC;
      ena   : IN  STD_LOGIC;
      wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dina  : IN  STD_LOGIC_VECTOR(51 DOWNTO 0);
      douta : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
      clkb  : IN  STD_LOGIC;
      enb   : IN  STD_LOGIC;
      web   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addrb : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dinb  : IN  STD_LOGIC_VECTOR(51 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(51 DOWNTO 0));
  end component blk_mem_A8x52_B8x52_2clock;

   component blk_mem_A8x52_B8x52_1clock is
    port (
      clka  : IN  STD_LOGIC;
      ena   : IN  STD_LOGIC;
      wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dina  : IN  STD_LOGIC_VECTOR(51 DOWNTO 0);
      douta : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
      clkb  : IN  STD_LOGIC;
      enb   : IN  STD_LOGIC;
      web   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addrb : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dinb  : IN  STD_LOGIC_VECTOR(51 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(51 DOWNTO 0));
  end component blk_mem_A8x52_B8x52_1clock;


  signal counter_reset, counter_reset_unstretched: std_logic;
  component Stretch_10 is
    port (
      unstretched_IN : in  std_logic;
      stretched_OUT  : out std_logic;
      clk            : in  std_logic);
  end component Stretch_10;

  signal counter_reset_r_SYSTEM,counter_reset_rr_SYSTEM,counter_reset_rr_SYSTEM_r_SOURCE,counter_reset_rr_SYSTEM_rr_SOURCE,counter_reset_rr_SYSTEM_r_SYSTEMDS2,counter_reset_rr_SYSTEM_rr_SYSTEMDS2: std_logic_vector(numactchan-1 downto 0);

  signal data_from_vme_REG_RW_RTM_INPUT_COUNTER_RESET : std_logic_vector (15 downto 0);  --actual value is
                                                                               --ignored but
                                                                               --supplied for sw check
  signal data_to_vme_REG_RW_RTM_INPUT_COUNTER_RESET   : std_logic_vector (15 downto 0);


  signal data_from_vme_REG_RW_RTM_INPUT_CHANNEL_MASK : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RW_RTM_INPUT_CHANNEL_MASK : std_logic_vector(15 downto 0);
  
  signal all_null : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);

  component CMX_generic_spy_mem_control_FSM is
    generic (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD    : integer;
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL : integer;
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS  : integer;
      num_external_RAMS                   : positive);
    port (
      clk                   : in    std_logic;
      ncs                   : in    std_logic;
      rd_nwr                : in    std_logic;
      ds                    : in    std_logic;
      addr_vme              : in    std_logic_vector (15 downto 0);
      data_vme_in   : in    std_logic_vector (15 downto 0);
      data_vme_out  : out   std_logic_vector (15 downto 0);
      bus_drive     : out   std_logic;
      mode_control          : out   std_logic_vector(3 downto 0);
      ena                   : out   std_logic;
      wea                   : out   std_logic;
      addra                 : out   std_logic_vector(7 DOWNTO 0);
      mem_select_address    : out   std_logic_vector(addr_port_width(num_external_RAMS)-1 downto 0);
      dina                  : out   std_logic_vector;
      douta                 : in    std_logic_vector;
      port_b_master_inhibit : out   std_logic);
  end component CMX_generic_spy_mem_control_FSM;

  signal mode_control_RTM_SPY_SOURCE : std_logic_vector(3 downto 0);     
  signal ena_RTM_SPY_SOURCE : std_logic;                 
  signal wea_RTM_SPY_SOURCE : std_logic;       
  signal addra_RTM_SPY_SOURCE : std_logic_vector(7 DOWNTO 0);
  signal mem_select_address_RTM_SPY_SOURCE : std_logic_vector(addr_port_width(num_RTM_cables)-1 downto 0);
  signal dina_RTM_SPY_SOURCE : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal douta_RTM_SPY_SOURCE : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal port_b_master_inhibit_RTM_SPY_SOURCE : std_logic;

  signal ena_rtm_spy_source_individual : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal wea_rtm_spy_source_individual : arr_1(num_RTM_cables-1 downto 0);   
  signal douta_rtm_spy_source_individual : arr_RTM_sdr;
  signal clkb_rtm_spy_source_individual  : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source_individual   : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_source_individual   : arr_1(num_RTM_cables-1 downto 0);   
  signal addrb_rtm_spy_source_individual : arr_8(num_RTM_cables-1 downto 0);   
  signal dinb_rtm_spy_source_individual  : arr_RTM_sdr;
  signal doutb_rtm_spy_source_individual : arr_RTM_sdr;

  signal addrb_RTM_SPY_SOURCE_counter : arr_ctr_8bit(num_RTM_cables-1 downto 0);

  
  signal port_b_master_inhibit_rtm_spy_source_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_source_rr_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source_rr_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_source_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal port_b_master_inhibit_rtm_spy_source_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_source_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal port_b_master_inhibit_rtm_spy_source_r_system_rr_source : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal port_b_master_inhibit_rtm_spy_source_r_system_r_source : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_source_rr_source : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_source_r_source : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source_rr_source : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source_r_source : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_source : std_logic;   
  signal web_rtm_spy_source : std_logic;   

  

  
  signal mode_control_RTM_SPY_SYSTEM : std_logic_vector(3 downto 0);     
  signal ena_RTM_SPY_SYSTEM : std_logic;                 
  signal wea_RTM_SPY_SYSTEM : std_logic;       
  signal addra_RTM_SPY_SYSTEM : std_logic_vector(7 DOWNTO 0);
  signal mem_select_address_RTM_SPY_SYSTEM : std_logic_vector(addr_port_width(num_RTM_cables)-1 downto 0);
  signal dina_RTM_SPY_SYSTEM : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal douta_RTM_SPY_SYSTEM : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal port_b_master_inhibit_RTM_SPY_SYSTEM : std_logic;

  signal ena_rtm_spy_system_individual : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal wea_rtm_spy_system_individual : arr_1(num_RTM_cables-1 downto 0);   
  signal douta_rtm_spy_system_individual : arr_RTM_sdr;
  signal enb_rtm_spy_system_individual   : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_system_individual   : arr_1(num_RTM_cables-1 downto 0);   
  signal addrb_rtm_spy_system_individual : arr_8(num_RTM_cables-1 downto 0);   
  signal dinb_rtm_spy_system_individual  : arr_RTM_sdr;
  signal doutb_rtm_spy_system_individual : arr_RTM_sdr;

  signal addrb_RTM_SPY_SYSTEM_counter : arr_ctr_8bit(num_RTM_cables-1 downto 0);

  signal port_b_master_inhibit_rtm_spy_system_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_system_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_system_r_system : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal port_b_master_inhibit_rtm_spy_system_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_system_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_system_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_system : std_logic;
  signal web_rtm_spy_system : std_logic;
  

  signal mode_control_RTM_SPY_SYSTEMDS2 : std_logic_vector(3 downto 0);     
  signal ena_RTM_SPY_SYSTEMDS2 : std_logic;                 
  signal wea_RTM_SPY_SYSTEMDS2 : std_logic;       
  signal addra_RTM_SPY_SYSTEMDS2 : std_logic_vector(7 DOWNTO 0);
  signal mem_select_address_RTM_SPY_SYSTEMDS2 : std_logic_vector(addr_port_width(num_RTM_cables)-1 downto 0);
  signal dina_RTM_SPY_SYSTEMDS2 : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal douta_RTM_SPY_SYSTEMDS2 : std_logic_vector(numbits_in_RTM_connector*2 - 1 downto 0);                
  signal port_b_master_inhibit_RTM_SPY_SYSTEMDS2 : std_logic;

  signal ena_rtm_spy_systemds2_individual : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal wea_rtm_spy_systemds2_individual : arr_1(num_RTM_cables-1 downto 0);   
  signal douta_rtm_spy_systemds2_individual : arr_RTM_sdr;
  signal enb_rtm_spy_systemds2_individual   : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_systemds2_individual   : arr_1(num_RTM_cables-1 downto 0);   
  signal addrb_rtm_spy_systemds2_individual : arr_8(num_RTM_cables-1 downto 0);   
  signal dinb_rtm_spy_systemds2_individual  : arr_RTM_sdr;
  signal doutb_rtm_spy_systemds2_individual : arr_RTM_sdr;

  signal addrb_RTM_SPY_SYSTEMDS2_counter : arr_ctr_8bit(num_RTM_cables-1 downto 0);

  signal port_b_master_inhibit_rtm_spy_systemds2_r_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_systemds2_r_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_systemds2_r_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal port_b_master_inhibit_rtm_spy_systemds2_rr_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_systemds2_rr_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_systemds2_rr_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_systemds2 : std_logic;       
  signal enb_rtm_spy_systemds2 : std_logic;

  
  signal port_b_master_inhibit_rtm_spy_systemds2_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal web_rtm_spy_systemds2_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  signal enb_rtm_spy_systemds2_split : std_logic_vector(num_RTM_cables-1 downto 0);   
  
  
  signal spy_write_inhibit_r_system_r_source : std_logic_vector(num_RTM_cables-1 downto 0);
  signal spy_write_inhibit_r_system_rr_source : std_logic_vector(num_RTM_cables-1 downto 0);
  signal spy_write_inhibit_r_system : std_logic_vector(num_RTM_cables-1 downto 0);
  signal spy_write_inhibit_rr_system : std_logic_vector(num_RTM_cables-1 downto 0);
  signal spy_write_inhibit_r_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);
  signal spy_write_inhibit_rr_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);

  
  signal start_playback_r_system : std_logic_vector(num_RTM_cables-1 downto 0);
  signal start_playback_rr_system : std_logic_vector(num_RTM_cables-1 downto 0);
  signal start_playback_r_system_r_source : std_logic_vector(num_RTM_cables-1 downto 0);
  signal start_playback_r_system_rr_source : std_logic_vector(num_RTM_cables-1 downto 0);
  signal start_playback_r_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);
  signal start_playback_rr_systemds2 : std_logic_vector(num_RTM_cables-1 downto 0);

  signal par_err_counter_next : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal par_err_counter : arr_ctr_32bit(num_RTM_cables-1 downto 0);

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  signal data_vme_from_below  : arr_16(4+9*num_RTM_cables+2 downto 0);
  signal bus_drive_from_below : std_logic_vector(4+9*num_RTM_cables+2 downto 0);
  
  
  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;
  
  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;
  
  component vme_outreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk         : in  std_logic;
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0);
      read_detect : out std_logic);
  end component vme_outreg_notri;


  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;



  signal data_to_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS : std_logic_vector(15 downto 0);  
  signal data_from_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS : arr_16(num_RTM_cables-1 downto 0);
  signal data_from_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS : std_logic_vector(15 downto 0);
  signal data_from_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS : std_logic_vector(15 downto 0);  

  signal data_to_vme_reg_ro_rtm_spy_source_mem_check_error_0 : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_reg_ro_rtm_spy_source_mem_check_error_1 : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_reg_ro_rtm_spy_system_mem_check_error_0 : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_reg_ro_rtm_spy_system_mem_check_error_1 : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_reg_ro_rtm_spy_systemds2_mem_check_error_0 : arr_16(num_RTM_cables-1 downto 0);
  signal data_to_vme_reg_ro_rtm_spy_systemds2_mem_check_error_1 : arr_16(num_RTM_cables-1 downto 0);

  signal bit_error_counter_source_next : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_counter_source : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_latch_source : arr_26(num_RTM_cables-1 downto 0); 
  signal bit_error_detect_source : arr_52(num_RTM_cables-1 downto 0); 

  signal bit_error_counter_system_next : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_counter_system : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_latch_system : arr_26(num_RTM_cables-1 downto 0); 
  signal bit_error_detect_system : arr_52(num_RTM_cables-1 downto 0);   

  signal bit_error_counter_systemds2_next : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_counter_systemds2 : arr_ctr_32bit(num_RTM_cables-1 downto 0);
  signal bit_error_latch_systemds2 : arr_26(num_RTM_cables-1 downto 0); 
  signal bit_error_detect_systemds2 : arr_52(num_RTM_cables-1 downto 0);

  component or_all is
    generic (
      numbits : integer);
    port (
      DATA   : in  std_logic_vector(numbits - 1 downto 0);
      or_all : out std_logic);
  end component or_all;

begin

  all_null<=(others=>'0');

  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_from_below,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_from_below);

  vme_inreg_REG_RW_RTM_INPUT_COUNTER_RESET: vme_inreg_notri
    generic map (
      ia_vme  => ADDR_REG_RW_RTM_INPUT_COUNTER_RESET ,
      width   => 16)
    port map (
      clk            => buf_clk40 ,
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      data_from_vme  => data_from_vme_REG_RW_RTM_INPUT_COUNTER_RESET,
      data_to_vme    => data_to_vme_REG_RW_RTM_INPUT_COUNTER_RESET,  
      addr_vme       => addr_vme,
      read_detect    => open,
      write_detect   => counter_reset_unstretched ,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_from_below (0),
      bus_drive      => bus_drive_from_below (0)
      );
  
  data_to_vme_REG_RW_RTM_INPUT_COUNTER_RESET<=data_from_vme_REG_RW_RTM_INPUT_COUNTER_RESET;

  Stretch_10_counter_reset : Stretch_10
    port map (
      unstretched_IN  => counter_reset_unstretched ,
      stretched_OUT   => counter_reset,
      clk             => buf_clk40 );


  
  CMX_generic_spy_mem_control_FSM_inst_SOURCE: entity work.CMX_generic_spy_mem_control_FSM
    generic map (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD     => ADDR_REG_RW_RTM_SPY_SOURCE_MEM_WORD,
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL  => ADDR_REG_RW_RTM_SPY_SOURCE_MEM_CONTROL,
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS   => ADDR_REG_RO_RTM_SPY_SOURCE_MEM_STATUS,
      num_external_RAMS                    => num_RTM_cables)
    port map (
      clk                    => buf_clk40,
      ncs                    => ncs,
      rd_nwr                 => rd_nwr,
      ds                     => ds,
      addr_vme               => addr_vme,
      data_vme_in            => data_vme_in,
      data_vme_out           => data_vme_from_below(1),
      bus_drive              => bus_drive_from_below(1),
      mode_control           => mode_control_RTM_SPY_SOURCE ,
      ena                    => ena_RTM_SPY_SOURCE,
      wea                    => wea_RTM_SPY_SOURCE,
      addra                  => addra_RTM_SPY_SOURCE,
      mem_select_address     => mem_select_address_RTM_SPY_SOURCE ,
      dina                   => dina_RTM_SPY_SOURCE,
      douta                  => douta_RTM_SPY_SOURCE,
      port_b_master_inhibit  => port_b_master_inhibit_RTM_SPY_SOURCE );
  

  CMX_generic_spy_mem_control_FSM_inst_SYSTEM: entity work.CMX_generic_spy_mem_control_FSM
    generic map (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD     => ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_WORD,
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL  => ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_CONTROL,
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS   => ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_STATUS,
      num_external_RAMS                    => num_RTM_cables)
    port map (
      clk                    => buf_clk40,
      ncs                    => ncs,
      rd_nwr                 => rd_nwr,
      ds                     => ds,
      addr_vme               => addr_vme,
      data_vme_in            => data_vme_in,
      data_vme_out           => data_vme_from_below(2),
      bus_drive              => bus_drive_from_below(2),
      mode_control           => mode_control_RTM_SPY_SYSTEM ,
      ena                    => ena_RTM_SPY_SYSTEM,
      wea                    => wea_RTM_SPY_SYSTEM,
      addra                  => addra_RTM_SPY_SYSTEM,
      mem_select_address     => mem_select_address_RTM_SPY_SYSTEM ,
      dina                   => dina_RTM_SPY_SYSTEM,
      douta                  => douta_RTM_SPY_SYSTEM,
      port_b_master_inhibit  => port_b_master_inhibit_RTM_SPY_SYSTEM );

  CMX_generic_spy_mem_control_FSM_inst_SYSTEMDS2: entity work.CMX_generic_spy_mem_control_FSM
    generic map (
      ADDR_REG_RW_GENERIC_SPY_MEM_WORD     => ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_WORD,
      ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL  => ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_CONTROL ,
      ADDR_REG_RO_GENERIC_SPY_MEM_STATUS   => ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_STATUS,
      num_external_RAMS                    => num_RTM_cables)
    port map (
      clk                    => buf_clk40,
      ncs                    => ncs,
      rd_nwr                 => rd_nwr,
      ds                     => ds,
      addr_vme               => addr_vme,
      data_vme_in            => data_vme_in,
      data_vme_out           => data_vme_from_below(3),
      bus_drive              => bus_drive_from_below(3),
      mode_control           => mode_control_RTM_SPY_SYSTEMDS2 ,
      ena                    => ena_RTM_SPY_SYSTEMDS2,
      wea                    => wea_RTM_SPY_SYSTEMDS2,
      addra                  => addra_RTM_SPY_SYSTEMDS2 ,
      mem_select_address     => mem_select_address_RTM_SPY_SYSTEMDS2 ,
      dina                   => dina_RTM_SPY_SYSTEMDS2,
      douta                  => douta_RTM_SPY_SYSTEMDS2 ,
      port_b_master_inhibit  => port_b_master_inhibit_RTM_SPY_SYSTEMDS2);
  
  
  channel_gen: for channel in 0 to num_RTM_cables-1 generate


    
    --process to generate a local registers for the inhibit signal
    process(forwarded_clock(channel),pll_locked)
    begin
      if pll_locked /='1' then
        spy_write_inhibit_r_SYSTEM_r_SOURCE(channel)<='0';
      else
        if rising_edge(forwarded_clock(channel)) then
          spy_write_inhibit_r_SYSTEM_r_SOURCE(channel)<=spy_write_inhibit_r_SYSTEM(channel);
        end if;
      end if;
    end process;                
    process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        spy_write_inhibit_r_SYSTEM_rr_SOURCE(channel)<=spy_write_inhibit_r_SYSTEM_r_SOURCE(channel);
      end if;
    end process;

    
    --process to locally register the inhibit signal in system domain and yet again;
    process(buf_clk40,pll_locked)
    begin
      if pll_locked/='1' then
        spy_write_inhibit_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        spy_write_inhibit_r_SYSTEM(channel)<=spy_write_inhibit;
      end if;
    end process;
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        spy_write_inhibit_rr_SYSTEM(channel)<=spy_write_inhibit_r_SYSTEM(channel);
      end if;
    end process;


    
    --process to locally register the inhibit signal in the DS2 domain using
    --the system domain register as input;
    process(buf_clk40_ds2,pll_locked_ds2)
    begin
      if pll_locked_ds2/='1' then
        spy_write_inhibit_r_SYSTEMDS2(channel)<='0';
      elsif rising_edge(buf_clk40_ds2) then
        spy_write_inhibit_r_SYSTEMDS2(channel)<=spy_write_inhibit;
      end if;
    end process;
    process(buf_clk40_ds2)
    begin
      if rising_edge(buf_clk40_ds2) then
        spy_write_inhibit_rr_SYSTEMDS2(channel)<=spy_write_inhibit_r_SYSTEMDS2(channel);
      end if;
    end process;
    
    

    CMX_cable_clocked_80Mbps_input_module_inst: entity work.CMX_cable_clocked_80Mbps_input_module
      generic map (
        numbits_in_cable_connector  => numbits_in_RTM_connector)
      port map (
        data             => data_sdr_unmasked (channel),
        parity_error     => parity_error_unmasked_sig (channel),
        forwarded_clock  => forwarded_clock(channel),
        ddr_data_in      => ddr_data_in(channel),
        buf_clk40        => buf_clk40,
        buf_clk200       => '0',
        pll_locked       => pll_locked,
        del_array        => (others=>(others =>'0')),
        upload_delays    => '0');

    parity_error_sig(channel)<=parity_error_unmasked_sig(channel) when channel_mask(channel)='0' else '0';
    --PAR_ERROR(channel)<=PAR_ERROR_sig(channel);

    ch_quiet(channel) <= '1' when channel_mask(channel)='1' or (quiet='1' and parity_error_unmasked_sig(channel)='1') else '0'; 
    data_sdr(channel) <= data_sdr_unmasked(channel) when ch_quiet(channel)/='1' else x"8000002000000";

    blk_mem_A8x52_B8x52_2clock_SOURCE: blk_mem_A8x52_B8x52_2clock
      port map (
        clka   => buf_clk40,
        ena    => ena_RTM_SPY_SOURCE_individual(channel),
        wea    => wea_RTM_SPY_SOURCE_individual(channel),
        addra  => addra_RTM_SPY_SOURCE ,
        dina   => dina_RTM_SPY_SOURCE ,
        douta  => douta_RTM_SPY_SOURCE_individual(channel),
        clkb   => clkb_RTM_SPY_SOURCE_individual(channel),
        enb    => enb_RTM_SPY_SOURCE_individual(channel),
        web    => web_RTM_SPY_SOURCE_individual(channel),
        addrb  => addrb_RTM_SPY_SOURCE_individual(channel),
        dinb   => dinb_RTM_SPY_SOURCE_individual(channel),
        doutb  => doutb_RTM_SPY_SOURCE_individual(channel));


    -- select the control signals based on the value of the mem_select_address_RTM_SPY_SOURCE
    ena_RTM_SPY_SOURCE_individual(channel) <= ena_RTM_SPY_SOURCE when mem_select_address_RTM_SPY_SOURCE
                                               =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';
    
    wea_RTM_SPY_SOURCE_individual(channel)(0) <= wea_RTM_SPY_SOURCE when mem_select_address_RTM_SPY_SOURCE
                                                  =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';

    --this should generate a n-1 multiplexer with douta_RTM_SPY_SOURCE as output
    --if there are moren than 1 rtm sources; if there is just one rtm source 
    --I expect the 1-1 'mux' will be optimized out.
    douta_RTM_SPY_SOURCE<=douta_RTM_SPY_SOURCE_individual(channel) when  mem_select_address_RTM_SPY_SOURCE
                       =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else (others=>'Z');

    
    dinb_RTM_SPY_SOURCE_individual(channel)<=data_sdr(channel); 
    clkb_RTM_SPY_SOURCE_individual(channel)<=forwarded_clock(channel);
    addrb_RTM_SPY_SOURCE_individual(channel)<=std_logic_vector(addrb_RTM_SPY_SOURCE_counter(channel));


    
    blk_mem_A8x52_B8x52_1clock_SYSTEM: blk_mem_A8x52_B8x52_1clock
      port map (
        clka   => buf_clk40,
        ena    => ena_RTM_SPY_SYSTEM_individual(channel),
        wea    => wea_RTM_SPY_SYSTEM_individual(channel),
        addra  => addra_RTM_SPY_SYSTEM ,
        dina   => dina_RTM_SPY_SYSTEM ,
        douta  => douta_RTM_SPY_SYSTEM_individual(channel),
        clkb   => buf_clk40,
        enb    => enb_RTM_SPY_SYSTEM_individual(channel),
        web    => web_RTM_SPY_SYSTEM_individual(channel),
        addrb  => addrb_RTM_SPY_SYSTEM_individual(channel),
        dinb   => dinb_RTM_SPY_SYSTEM_individual(channel),
        doutb  => doutb_RTM_SPY_SYSTEM_individual(channel));

    
    -- select the control signals based on the value of the mem_select_address_RTM_SPY_SYSTEM
    ena_RTM_SPY_SYSTEM_individual(channel) <= ena_RTM_SPY_SYSTEM when mem_select_address_RTM_SPY_SYSTEM
                                               =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';
    
    wea_RTM_SPY_SYSTEM_individual(channel)(0) <= wea_RTM_SPY_SYSTEM when mem_select_address_RTM_SPY_SYSTEM
                                                  =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';

    --this should generate a n-1 multiplexer with douta_RTM_SPY_SYSTEM as output
    --if there are moren than 1 rtm sources; if there is just one rtm source 
    --I expect the 1-1 'mux' will be optimized out.
    douta_RTM_SPY_SYSTEM<=douta_RTM_SPY_SYSTEM_individual(channel) when  mem_select_address_RTM_SPY_SYSTEM
                       =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else (others=>'Z');

    
    dinb_RTM_SPY_SYSTEM_individual(channel)<=data_DS2_r_SYSTEM(channel); 
    addrb_RTM_SPY_SYSTEM_individual(channel)<=std_logic_vector(addrb_RTM_SPY_SYSTEM_counter(channel));



    blk_mem_A8x52_B8x52_2clock_SYSTEMDS2: blk_mem_A8x52_B8x52_2clock
      port map (
        clka   => buf_clk40,
        ena    => ena_RTM_SPY_SYSTEMDS2_individual(channel),
        wea    => wea_RTM_SPY_SYSTEMDS2_individual(channel),
        addra  => addra_RTM_SPY_SYSTEMDS2,
        dina   => dina_RTM_SPY_SYSTEMDS2,
        douta  => douta_RTM_SPY_SYSTEMDS2_individual(channel),
        clkb   => buf_clk40_ds2 ,
        enb    => enb_RTM_SPY_SYSTEMDS2_individual(channel),
        web    => web_RTM_SPY_SYSTEMDS2_individual(channel),
        addrb  => addrb_RTM_SPY_SYSTEMDS2_individual(channel),
        dinb   => dinb_RTM_SPY_SYSTEMDS2_individual(channel),
        doutb  => doutb_RTM_SPY_SYSTEMDS2_individual(channel));


    -- select the control signals based on the value of the mem_select_address_RTM_SPY_SYSTEMDS2
    ena_RTM_SPY_SYSTEMDS2_individual(channel) <= ena_RTM_SPY_SYSTEMDS2 when mem_select_address_RTM_SPY_SYSTEMDS2
                                               =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';
    
    wea_RTM_SPY_SYSTEMDS2_individual(channel)(0) <= wea_RTM_SPY_SYSTEMDS2 when mem_select_address_RTM_SPY_SYSTEMDS2
                                                  =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else '0';

    --this should generate a n-1 multiplexer with douta_RTM_SPY_SYSTEMDS2 as output
    --if there are moren than 1 rtm sources; if there is just one rtm source 
    --I expect the 1-1 'mux' will be optimized out.
    douta_RTM_SPY_SYSTEMDS2<=douta_RTM_SPY_SYSTEMDS2_individual(channel) when  mem_select_address_RTM_SPY_SYSTEMDS2
                       =std_logic_vector(to_unsigned(channel,mem_select_addr_width)) else (others=>'Z');

    
    dinb_RTM_SPY_SYSTEMDS2_individual(channel)<=data_sdr_r_SYSTEMDS2(channel);
    addrb_RTM_SPY_SYSTEMDS2_individual(channel)<=std_logic_vector(addrb_RTM_SPY_SYSTEMDS2_counter(channel));

    
    
    vme_inreg_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS: vme_inreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS+2*channel,
        width =>16)
      port map (
        ncs            => ncs,
        rd_nwr         => rd_nwr,
        ds             => ds,
        addr_vme       => addr_vme,
        data_vme_in            => data_vme_in,
        data_vme_out           => data_vme_from_below(4+9*channel),
        bus_drive              => bus_drive_from_below(4+9*channel),
        data_from_vme  => data_from_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS(channel),
        data_to_vme    => data_to_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS(channel));
    data_to_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS(channel)<=data_from_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS(channel);


  


    
    process(buf_clk40,pll_locked)
    begin
      if pll_locked/='1' then
        start_playback_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        start_playback_r_SYSTEM(channel)<=start_playback;
      end if;
    end process;
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        --a local register (one copy for each of the memories)to ease timing
        start_playback_rr_SYSTEM(channel)<=start_playback_r_SYSTEM(channel);
      end if;
    end process;
    
    --synchronisation of the start playback signal to the source domain
    process(forwarded_clock(channel), pll_locked)
    begin
      if pll_locked/='1' then
        start_playback_r_SYSTEM_r_SOURCE(channel)<='0';
      else
        if rising_edge(forwarded_clock(channel)) then
          start_playback_r_SYSTEM_r_SOURCE(channel)<=start_playback_r_SYSTEM(channel);
        end if;
      end if;
    end process;
    process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        start_playback_r_SYSTEM_rr_SOURCE(channel)<=start_playback_r_SYSTEM_r_SOURCE(channel);
      end if;
    end process;
    
    --synchronisation of the start playback signal to the system ds2 domain
    process(buf_clk40_ds2, pll_locked_ds2)
    begin
      if pll_locked_ds2/='1' then
        start_playback_r_SYSTEMDS2(channel)<='0';
      else
        if rising_edge(buf_clk40_ds2) then
          start_playback_r_SYSTEMDS2(channel)<=start_playback;
        end if;
      end if;
    end process;
    process(buf_clk40_ds2)
    begin
      if rising_edge(buf_clk40_ds2) then
        start_playback_rr_SYSTEMDS2(channel)<=start_playback_r_SYSTEMDS2(channel);
      end if;
    end process;


    
    spy_source_addr_proc: process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        if start_playback_r_SYSTEM_rr_SOURCE(channel)='0' then
          addrb_RTM_SPY_SOURCE_counter(channel)<=addrb_RTM_SPY_SOURCE_counter(channel)+1;
        else
          addrb_RTM_SPY_SOURCE_counter(channel)<=unsigned(
            data_from_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS(channel)(7 downto 0));
        end if;
      end if;
    end process;

    spy_system_addr_proc: process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        if start_playback_rr_SYSTEM(channel)='0' then
          addrb_RTM_SPY_SYSTEM_counter(channel)<=addrb_RTM_SPY_SYSTEM_counter(channel)+1;
        else
          addrb_RTM_SPY_SYSTEM_counter(channel)<=unsigned(
            data_from_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS(7 downto 0));
        end if;
      end if;
    end process;

    
    spy_systemds2_addr_proc: process(buf_clk40_ds2)
    begin
      if rising_edge(buf_clk40_ds2) then
        if start_playback_rr_SYSTEMDS2(channel)='0' then
          addrb_RTM_SPY_SYSTEMDS2_counter(channel)<=addrb_RTM_SPY_SYSTEMDS2_counter(channel)+1;
        else
          addrb_RTM_SPY_SYSTEMDS2_counter(channel)<=unsigned(
            data_from_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS(7 downto 0));
        end if;
      end if;
    end process;
    
    
    --create local registers for the master inhibit to aid timing closure
    local_buf_master_inhibit: process(buf_clk40,pll_locked)
    begin
      if pll_locked='0' then
        port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM(channel)<='1';
        web_RTM_SPY_SOURCE_rr_SYSTEM(channel)<='0';
        enb_RTM_SPY_SOURCE_rr_SYSTEM(channel)<='0';
        web_RTM_SPY_SOURCE_r_SYSTEM(channel)<='0';
        enb_RTM_SPY_SOURCE_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM(channel)<=port_b_master_inhibit_RTM_SPY_SOURCE_split(channel);
        web_RTM_SPY_SOURCE_rr_SYSTEM(channel)<=web_RTM_SPY_SOURCE_r_SYSTEM(channel);
        enb_RTM_SPY_SOURCE_rr_SYSTEM(channel)<=enb_RTM_SPY_SOURCE_r_SYSTEM(channel);
        web_RTM_SPY_SOURCE_r_SYSTEM(channel)<=web_RTM_SPY_SOURCE_split(channel);
        enb_RTM_SPY_SOURCE_r_SYSTEM(channel)<=enb_RTM_SPY_SOURCE_split(channel);
      end if;
    end process local_buf_master_inhibit;
    process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM_rr_SOURCE(channel)<=port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM_r_SOURCE(channel);
        port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM_r_SOURCE(channel)<=port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM(channel);
        web_RTM_SPY_SOURCE_rr_SOURCE(channel)<=web_RTM_SPY_SOURCE_r_SOURCE(channel);
        web_RTM_SPY_SOURCE_r_SOURCE(channel)<=web_RTM_SPY_SOURCE_rr_SYSTEM(channel);
        enb_RTM_SPY_SOURCE_rr_SOURCE(channel)<=enb_RTM_SPY_SOURCE_r_SOURCE(channel);
        enb_RTM_SPY_SOURCE_r_SOURCE(channel)<=enb_RTM_SPY_SOURCE_rr_SYSTEM(channel);
      end if;
    end process;


    web_RTM_SPY_SOURCE_individual(channel)(0)<=web_RTM_SPY_SOURCE_rr_SOURCE(channel) and (not port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM_rr_SOURCE(channel)) and (not spy_write_inhibit_r_SYSTEM_rr_SOURCE(channel));
    enb_RTM_SPY_SOURCE_individual(channel)<=enb_RTM_SPY_SOURCE_rr_SOURCE(channel) and (not port_b_master_inhibit_RTM_SPY_SOURCE_r_SYSTEM_rr_SOURCE(channel));

    port_b_master_inhibit_RTM_SPY_SOURCE_split(channel)<=port_b_master_inhibit_RTM_SPY_SOURCE;
    enb_RTM_SPY_SOURCE_split(channel)<=enb_RTM_SPY_SOURCE;
    web_RTM_SPY_SOURCE_split(channel)<=web_RTM_SPY_SOURCE;


    --create local registers for the master inhibit to aid timing closure
    local_buf_master_inhibit_system: process(buf_clk40,pll_locked)
    begin
      if pll_locked='0' then
        port_b_master_inhibit_RTM_SPY_SYSTEM_r_SYSTEM(channel)<='1';
        web_RTM_SPY_SYSTEM_r_SYSTEM(channel)<='0';
        enb_RTM_SPY_SYSTEM_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        port_b_master_inhibit_RTM_SPY_SYSTEM_r_SYSTEM(channel)<=port_b_master_inhibit_RTM_SPY_SYSTEM_split(channel);
        web_RTM_SPY_SYSTEM_r_SYSTEM(channel)<=web_RTM_SPY_SYSTEM_split(channel);
        enb_RTM_SPY_SYSTEM_r_SYSTEM(channel)<=enb_RTM_SPY_SYSTEM_split(channel);
      end if;
    end process local_buf_master_inhibit_system;

    web_RTM_SPY_SYSTEM_individual(channel)(0)<=web_RTM_SPY_SYSTEM_r_SYSTEM(channel) and (not port_b_master_inhibit_RTM_SPY_SYSTEM_r_SYSTEM(channel)) and (not spy_write_inhibit_rr_SYSTEM(channel));
    enb_RTM_SPY_SYSTEM_individual(channel)<=enb_RTM_SPY_SYSTEM_r_SYSTEM(channel) and (not port_b_master_inhibit_RTM_SPY_SYSTEM_r_SYSTEM(channel));
    
    
    port_b_master_inhibit_RTM_SPY_SYSTEM_split(channel)<=port_b_master_inhibit_RTM_SPY_SYSTEM;
    enb_RTM_SPY_SYSTEM_split(channel)<=enb_RTM_SPY_SYSTEM;
    web_RTM_SPY_SYSTEM_split(channel)<=web_RTM_SPY_SYSTEM;


       
    --create local registers for the master inhibit to aid timing closure   
    local_buf_master_inhibit_systemds2_r: process(buf_clk40_ds2,pll_locked_ds2)
    begin
      if pll_locked_ds2='0' then
        port_b_master_inhibit_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel)<='1';
        web_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel)<='0';
        enb_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel)<='0';
      elsif rising_edge(buf_clk40_ds2) then
        port_b_master_inhibit_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel)<=port_b_master_inhibit_RTM_SPY_SYSTEMDS2_split(channel);
        web_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel)<=web_RTM_SPY_SYSTEMDS2_split(channel);
        enb_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel)<=enb_RTM_SPY_SYSTEMDS2_split(channel);
      end if;
    end process local_buf_master_inhibit_systemds2_r;
    local_buf_master_inhibit_systemds2: process(buf_clk40_ds2)
    begin
      if rising_edge(buf_clk40_ds2) then
        port_b_master_inhibit_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel)<=port_b_master_inhibit_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel);
        web_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel)<=web_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel);
        enb_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel)<=enb_RTM_SPY_SYSTEMDS2_r_SYSTEMDS2(channel);
      end if;
    end process local_buf_master_inhibit_systemds2;

    web_RTM_SPY_SYSTEMDS2_individual(channel)(0)<=web_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel) and (not port_b_master_inhibit_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel)) and (not spy_write_inhibit_rr_SYSTEMDS2(channel));
    enb_RTM_SPY_SYSTEMDS2_individual(channel)<=enb_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel) and (not port_b_master_inhibit_RTM_SPY_SYSTEMDS2_rr_SYSTEMDS2(channel));
    
    
    port_b_master_inhibit_RTM_SPY_SYSTEMDS2_split(channel)<=port_b_master_inhibit_RTM_SPY_SYSTEMDS2;
    enb_RTM_SPY_SYSTEMDS2_split(channel)<=enb_RTM_SPY_SYSTEMDS2;
    web_RTM_SPY_SYSTEMDS2_split(channel)<=web_RTM_SPY_SYSTEMDS2;

    
    
    process(buf_clk40_ds2, pll_locked_ds2)
    begin
      if pll_locked_ds2/='1' then

        data_sdr_r_SYSTEMDS2(channel)<=(others=>'0');
        data_sdr_rr_SYSTEMDS2(channel)<=(others=>'0');

        parity_error_r_SYSTEMDS2(channel)<='0';
        data_DS2(channel)<=(others=>'0');
        
      elsif rising_edge(buf_clk40_ds2) then

        data_sdr_rr_SYSTEMDS2(channel)<=data_sdr_r_SYSTEMDS2(channel);
        data_sdr_r_SYSTEMDS2(channel)<=data_sdr(channel);

        --WTF 20150209 push the mux before the register
        if mode_control_RTM_SPY_SYSTEMDS2/=CONST_DPR_CONTROL_PLAYBACK then
          data_DS2(channel)<=data_sdr(channel);
        else
          data_DS2(channel)<=doutb_RTM_SPY_SYSTEMDS2_individual(channel);
        end if;
                            
          
        if mode_control_RTM_SPY_SYSTEMDS2/=CONST_DPR_CONTROL_PLAYBACK then
          parity_error_r_SYSTEMDS2(channel)<=parity_error_sig(channel);
        else
          parity_error_r_SYSTEMDS2(channel)<='0';
        end if;
          
      end if;
    end process;

    --WTF 20150209 push the mux before the register
    --select the data going out from the DS2 domain - 
    --data_DS2(channel)<=data_sdr_r_SYSTEMDS2(channel) when mode_control_RTM_SPY_SYSTEMDS2/=CONST_DPR_CONTROL_PLAYBACK
    --                    else
    --                    doutb_RTM_SPY_SYSTEMDS2_individual(channel);
    
    process(buf_clk40, pll_locked)
    begin
      if pll_locked/='1' then

        data_DS2_r_SYSTEM(channel)<=(others=>'0');
        data_DS2_rr_SYSTEM(channel)<=(others=>'0');

        parity_error_r_SYSTEMDS2_rr_SYSTEM(channel)<='0';
        parity_error_r_SYSTEMDS2_r_SYSTEM(channel)<='0';

      elsif rising_edge(buf_clk40) then
        
        data_DS2_rr_SYSTEM(channel)<=data_DS2_r_SYSTEM(channel);
        data_DS2_r_SYSTEM(channel)<=data_DS2(channel);
        
        parity_error_r_SYSTEMDS2_rr_SYSTEM(channel)<=parity_error_r_SYSTEMDS2_r_SYSTEM(channel);

        if mode_control_RTM_SPY_SYSTEM/=CONST_DPR_CONTROL_PLAYBACK then 
          parity_error_r_SYSTEMDS2_r_SYSTEM(channel)<=parity_error_r_SYSTEMDS2(channel);
        else
          parity_error_r_SYSTEMDS2_r_SYSTEM(channel)<='0';
        end if;
        
      end if;
    end process;

    process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        data_sdr_r_SOURCE(channel)<=data_sdr(channel);
      end if;
    end process;


    --another mux to finally present the data on the output
    --either take data from SYSTEM RAM or from DS2 (register or memory)
    --no additional registers are implemented between the DS2 and rest of the logic
    data(numbits_in_RTM_connector*2*(channel+1)-1 downto numbits_in_RTM_connector*2*channel)
      <=data_DS2(channel) when mode_control_RTM_SPY_SYSTEM/=CONST_DPR_CONTROL_PLAYBACK
      else
      doutb_RTM_SPY_SYSTEM_individual(channel);

    --WTF 20150209 This is incorrect timing:
    --parity_error(channel)<=parity_error_r_SYSTEMDS2_rr_SYSTEM(channel);


    --parity error counter
    
    vme_outreg_REG_RO_RTM_PARITY_ERROR_COUNTER_0: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_PARITY_ERROR_COUNTER+4*channel,
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => std_logic_vector(par_err_counter(channel)(15 downto 0)),
        data_vme               => data_vme_from_below(4+9*channel+1),
        bus_drive              => bus_drive_from_below(4+9*channel+1));
    
    
    vme_outreg_REG_RO_RTM_PARITY_ERROR_COUNTER_1: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_PARITY_ERROR_COUNTER+4*channel+2,
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => std_logic_vector(par_err_counter(channel)(31 downto 16)),
        data_vme               => data_vme_from_below(4+9*channel+2),
        bus_drive              => bus_drive_from_below(4+9*channel+2));

    par_err_counter_next(channel)<=par_err_counter(channel)+1;
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        if counter_reset_rr_SYSTEM(channel) /= '1' then
          if par_err_counter(channel) /= max_ctr32 then
            if parity_error_r_SYSTEMDS2_rr_SYSTEM(channel) = '1' then
              par_err_counter(channel)<=par_err_counter_next(channel);
            end if;
          else
            par_err_counter(channel)<=max_ctr32;
          end if;
        else
          par_err_counter(channel)<=to_unsigned(0,32);
        end if;        
      end if;
    end process;


    --this will make an error detection register that in turn will be used to
    --generate a latch; also an no-error run length counter is made in this process
    error_detect_process_source: process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        if counter_reset_rr_SYSTEM_rr_SOURCE(channel)/='1' then
          if bit_error_latch_source(channel)/=all_null
            or bit_error_counter_source(channel)=max_ctr32 then
            bit_error_counter_source_next(channel)<=bit_error_counter_source(channel);
          else
            bit_error_counter_source_next(channel)<=bit_error_counter_source(channel)+1;
          end if;
        else
          bit_error_counter_source_next(channel)<=to_unsigned(0,32);
        end if;  
        bit_error_counter_source(channel)<=bit_error_counter_source_next(channel);
        bit_error_detect_source(channel)<=doutb_RTM_SPY_SOURCE_individual(channel) xor data_sdr_r_SOURCE(channel);
      end if;
    end process error_detect_process_source;

    gen_err_latch_bit_source: for i_bit in 0 to numbits_in_RTM_connector -1 generate
      --resettable 'latch' (so not really a latch) that is set if there is an error
      --on a given bit 
      process(forwarded_clock(channel))
      begin
        if rising_edge(forwarded_clock(channel)) then
          if counter_reset_rr_SYSTEM_rr_SOURCE(channel)/='1' then
            if bit_error_detect_source(channel)(i_bit)='1' or bit_error_detect_source(channel)(i_bit+numbits_in_RTM_connector)='1' then
              bit_error_latch_source(channel)(i_bit)<='1';
            end if;
          else
            bit_error_latch_source(channel)(i_bit)<='0';
          end if;
        end if;
      end process;
    end generate gen_err_latch_bit_source;


    
    error_detect_process_system: process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        if counter_reset_rr_SYSTEM(channel)/='1' then
          if bit_error_latch_system(channel)/=all_null or bit_error_counter_system(channel)=max_ctr32 then
            bit_error_counter_system_next(channel)<=bit_error_counter_system(channel);
          else
            bit_error_counter_system_next(channel)<=bit_error_counter_system(channel)+1;
          end if;
        else
          bit_error_counter_system_next(channel)<=to_unsigned(0,32);
        end if;  
        bit_error_counter_system(channel)<=bit_error_counter_system_next(channel);
        bit_error_detect_system(channel)<=doutb_RTM_SPY_SYSTEM_individual(channel) xor data_DS2_rr_SYSTEM(channel);
      end if;
    end process error_detect_process_system;

    gen_err_latch_bit_system: for i_bit in 0 to numbits_in_RTM_connector -1 generate
      --resettable 'latch' (so not really a latch) that is set if there is an error
      --on a given bit 
      process(buf_clk40)
      begin
        if rising_edge(buf_clk40) then
          if counter_reset_rr_SYSTEM(channel)/='1' then
            if bit_error_detect_system(channel)(i_bit)='1' or bit_error_detect_system(channel)(i_bit+numbits_in_RTM_connector)='1' then
              bit_error_latch_system(channel)(i_bit)<='1';
            end if;
          else
            bit_error_latch_system(channel)(i_bit)<='0';
          end if;
        end if;
      end process;
    end generate gen_err_latch_bit_system;


    error_detect_process_systemds2: process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        if counter_reset_rr_SYSTEM_rr_SYSTEMDS2(channel)/='1' then
          if bit_error_latch_systemds2(channel)/=all_null
            or bit_error_counter_systemds2(channel)=max_ctr32 then
            bit_error_counter_systemds2_next(channel)<=bit_error_counter_systemds2(channel);
          else
            bit_error_counter_systemds2_next(channel)<=bit_error_counter_systemds2(channel)+1;
          end if;
        else
          bit_error_counter_systemds2_next(channel)<=to_unsigned(0,32);
        end if;  
        bit_error_counter_systemds2(channel)<=bit_error_counter_systemds2_next(channel);
        bit_error_detect_systemds2(channel)<=doutb_RTM_SPY_SYSTEMDS2_individual(channel) xor data_sdr_rr_SYSTEMDS2(channel);
      end if;
    end process error_detect_process_systemds2;

    gen_err_latch_bit_systemds2: for i_bit in 0 to numbits_in_RTM_connector -1 generate
      --resettable 'latch' (so not really a latch) that is set if there is an error
      --on a given bit 
      process(forwarded_clock(channel))
      begin
        if rising_edge(forwarded_clock(channel)) then
          if counter_reset_rr_SYSTEM_rr_SYSTEMDS2(channel)/='1' then
            if bit_error_detect_systemds2(channel)(i_bit)='1' or bit_error_detect_systemds2(channel)(i_bit+numbits_in_RTM_connector)='1' then
              bit_error_latch_systemds2(channel)(i_bit)<='1';
            end if;
          else
            bit_error_latch_systemds2(channel)(i_bit)<='0';
          end if;
        end if;
      end process;
    end generate gen_err_latch_bit_systemds2;


    -- create counter reset registers
    --double register to close timing
    process(buf_clk40)
    begin
      if rising_edge(buf_clk40) then
        counter_reset_rr_SYSTEM(channel)<=counter_reset_r_SYSTEM(channel);
      end if;
    end process;
    process(buf_clk40,pll_locked)
    begin
      if pll_locked/='1' then
        counter_reset_r_SYSTEM(channel)<='0';
      elsif rising_edge(buf_clk40) then
        counter_reset_r_SYSTEM(channel)<=counter_reset;
      end if;
    end process;
    
    --double register in the source domain
    process(forwarded_clock(channel))
    begin
      if rising_edge(forwarded_clock(channel)) then
        counter_reset_rr_SYSTEM_rr_SOURCE(channel)<=counter_reset_rr_SYSTEM_r_SOURCE(channel);
      end if;
    end process;
    process(forwarded_clock(channel),pll_locked)
    begin
      if pll_locked/='1' then
        counter_reset_rr_SYSTEM_r_SOURCE(channel)<='0';
      elsif rising_edge(forwarded_clock(channel)) then
        counter_reset_rr_SYSTEM_r_SOURCE(channel)<=counter_reset_rr_SYSTEM(channel);
      end if;
    end process;

    --double register in the systemds2 domain
    process(buf_clk40_ds2)
    begin
      if rising_edge(buf_clk40_ds2) then
        counter_reset_rr_SYSTEM_rr_SYSTEMDS2(channel)<=counter_reset_rr_SYSTEM_r_SYSTEMDS2(channel);
      end if;
    end process;
    process(buf_clk40_ds2,pll_locked_ds2)
    begin
      if pll_locked_ds2/='1' then
        counter_reset_rr_SYSTEM_r_SYSTEMDS2(channel)<='0';
      elsif rising_edge(buf_clk40_ds2) then
        counter_reset_rr_SYSTEM_r_SYSTEMDS2(channel)<=counter_reset_rr_SYSTEM(channel);
      end if;
    end process;
    

    --assign latches as data to the registers
    data_to_vme_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_0(channel)<=bit_error_latch_source(channel)(15 downto 0);
    data_to_vme_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_1(channel)(numbits_in_RTM_connector-16-1 downto 0)<=bit_error_latch_source(channel)(numbits_in_RTM_connector-1 downto 16);
    data_to_vme_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_1(channel)(15 downto numbits_in_RTM_connector-16)<=(others=>'0');

    data_to_vme_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_0(channel)<=bit_error_latch_system(channel)(15 downto 0);
    data_to_vme_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_1(channel)(numbits_in_RTM_connector-16-1 downto 0)<=bit_error_latch_system(channel)(numbits_in_RTM_connector-1 downto 16);
    data_to_vme_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_1(channel)(15 downto numbits_in_RTM_connector-16)<=(others=>'0');

    data_to_vme_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_0(channel)<=bit_error_latch_systemds2(channel)(15 downto 0);
    data_to_vme_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_1(channel)(numbits_in_RTM_connector-16-1 downto 0)<=bit_error_latch_systemds2(channel)(numbits_in_RTM_connector-1 downto 16);
    data_to_vme_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_1(channel)(15 downto numbits_in_RTM_connector-16)<=(others=>'0');

    vme_outreg_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_0: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR+(4*channel),
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_0(channel),
        data_vme               => data_vme_from_below(4+9*channel+3),
        bus_drive              => bus_drive_from_below(4+9*channel+3));

    vme_outreg_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_1: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR+(4*channel)+2,
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR_1(channel),
        data_vme               => data_vme_from_below(4+9*channel+4),
        bus_drive              => bus_drive_from_below(4+9*channel+4));

    
    vme_outreg_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_0: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR+(4*channel),
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_0(channel),
        data_vme               => data_vme_from_below(4+9*channel+5),
        bus_drive              => bus_drive_from_below(4+9*channel+5));

    vme_outreg_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_1: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR+(4*channel)+2,
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR_1(channel),
        data_vme               => data_vme_from_below(4+9*channel+6),
        bus_drive              => bus_drive_from_below(4+9*channel+6));


    vme_outreg_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_0: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR+(4*channel),
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_0(channel),
        data_vme               => data_vme_from_below(4+9*channel+7),
        bus_drive              => bus_drive_from_below(4+9*channel+7));

    vme_outreg_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_1: vme_outreg_notri_async
      generic map (
        ia_vme  => ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR+(4*channel)+2,
        width   => 16)
      port map (
        addr_vme     => addr_vme,
        ncs          => ncs,
        rd_nwr       => rd_nwr,
        ds           => ds,
        data_to_vme  => data_to_vme_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR_1(channel),
        data_vme               => data_vme_from_below(4+9*channel+8),
        bus_drive              => bus_drive_from_below(4+9*channel+8));

    
    
  end generate channel_gen;
  

  or_all_parity_error_total: entity work.or_all
    generic map (
      numbits  => num_RTM_cables )
    port map (
      DATA    => parity_error_r_SYSTEMDS2 ,
      or_all  => parity_error_total);
  
  --port enables - we enable B port when verifying, spying and playing back. Write
  --is enabled only when spying
  --no playback for the source spy
  enb_RTM_SPY_SOURCE <='1' when mode_control_RTM_SPY_SOURCE=CONST_DPR_CONTROL_SPY
                           or   mode_control_RTM_SPY_SOURCE=CONST_DPR_CONTROL_VERIFY
                           else '0';
  web_RTM_SPY_SOURCE<='1' when mode_control_RTM_SPY_SOURCE=CONST_DPR_CONTROL_SPY else '0';


  enb_RTM_SPY_SYSTEM <='1' when mode_control_RTM_SPY_SYSTEM=CONST_DPR_CONTROL_SPY
                           or   mode_control_RTM_SPY_SYSTEM=CONST_DPR_CONTROL_VERIFY
                           or   mode_control_RTM_SPY_SYSTEM=CONST_DPR_CONTROL_PLAYBACK
                           else '0';
  web_RTM_SPY_SYSTEM<='1' when mode_control_RTM_SPY_SYSTEM=CONST_DPR_CONTROL_SPY else '0';


  enb_RTM_SPY_SYSTEMDS2 <='1' when mode_control_RTM_SPY_SYSTEMDS2=CONST_DPR_CONTROL_SPY
                           or   mode_control_RTM_SPY_SYSTEMDS2=CONST_DPR_CONTROL_VERIFY
                           or   mode_control_RTM_SPY_SYSTEMDS2=CONST_DPR_CONTROL_PLAYBACK
                           else '0';
  web_RTM_SPY_SYSTEMDS2<='1' when mode_control_RTM_SPY_SYSTEMDS2=CONST_DPR_CONTROL_SPY else '0';




    
  vme_inreg_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS: vme_inreg_notri_async
  generic map (
    ia_vme  => ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS,
    width =>16)
  port map (
    ncs            => ncs,
    rd_nwr         => rd_nwr,
    ds             => ds,
    addr_vme       => addr_vme,
    data_vme_in            => data_vme_in,
    data_vme_out           => data_vme_from_below(4+9*num_RTM_cables),
    bus_drive              => bus_drive_from_below(4+9*num_RTM_cables),
    data_from_vme  => data_from_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS,
    data_to_vme    => data_to_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS);
  data_to_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS<=data_from_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS; 
  
  
  
  vme_inreg_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS: vme_inreg_notri_async
  generic map (
    ia_vme  => ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS,
    width =>16)
  port map (
    ncs            => ncs,
    rd_nwr         => rd_nwr,
    ds             => ds,
    addr_vme       => addr_vme,
    data_vme_in            => data_vme_in,
    data_vme_out           => data_vme_from_below(4+9*num_RTM_cables+1),
    bus_drive              => bus_drive_from_below(4+9*num_RTM_cables+1),
    data_from_vme  => data_from_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS,
    data_to_vme    => data_to_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS);
  data_to_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS<=data_from_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS;


  vme_inreg_REG_RW_RTM_INPUT_CHANNEL_MASK: vme_inreg_notri_async
  generic map (
    ia_vme  => ADDR_REG_RW_RTM_INPUT_CHANNEL_MASK,
    width =>16)
  port map (
    ncs            => ncs,
    rd_nwr         => rd_nwr,
    ds             => ds,
    addr_vme       => addr_vme,
    data_vme_in            => data_vme_in,
    data_vme_out           => data_vme_from_below(4+9*num_RTM_cables+2),
    bus_drive              => bus_drive_from_below(4+9*num_RTM_cables+2),
    data_from_vme  => data_from_vme_REG_RW_RTM_INPUT_CHANNEL_MASK,
    data_to_vme    => data_to_vme_REG_RW_RTM_INPUT_CHANNEL_MASK);
  data_to_vme_REG_RW_RTM_INPUT_CHANNEL_MASK<=data_from_vme_REG_RW_RTM_INPUT_CHANNEL_MASK;
  channel_mask<=data_from_vme_REG_RW_RTM_INPUT_CHANNEL_MASK(num_RTM_cables-1 downto 0);


 
    
end Behavioral;