CMX_system_cable_input_module Entity Reference

Inheritance diagram for CMX_system_cable_input_module:

Entities
Behavioral	architecture

Libraries
IEEE
UNISIM
work

Use Clauses
IEEE.STD_LOGIC_1164.all
IEEE.NUMERIC_STD.all
UNISIM.VComponents.all
work.CMX_local_package.all
work.CMXpackage.all
work.CMX_VME_defs.all

Ports
data	out std_logic_vector ( numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0 )
parity_error_total	out std_logic
ddr_data_in	in arr_RTM ( num_RTM_cables - 1 downto 0 )
buf_clk40	in std_logic
buf_clk40_ds2	in std_logic
pll_locked	in std_logic
pll_locked_ds2	in std_logic
quiet	in std_logic
start_playback	in std_logic
spy_write_inhibit	in std_logic
ncs	in std_logic
rd_nwr	in std_logic
ds	in std_logic
addr_vme	in std_logic_vector ( 15 downto 0 )
data_vme_in	in std_logic_vector ( 15 downto 0 )
data_vme_out	out std_logic_vector ( 15 downto 0 )
bus_drive	out std_logic

Detailed Description

Definition at line 28 of file CMX_system_cable_input_module.vhd.

Member Data Documentation

addr_vme in std_logic_vector ( 15 downto 0 )

Port

Definition at line 47 of file CMX_system_cable_input_module.vhd.

buf_clk40 in std_logic

Port

Definition at line 35 of file CMX_system_cable_input_module.vhd.

buf_clk40_ds2 in std_logic

Port

Definition at line 36 of file CMX_system_cable_input_module.vhd.

bus_drive out std_logic

Port

Definition at line 50 of file CMX_system_cable_input_module.vhd.

data out std_logic_vector ( numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0 )

Port

Definition at line 32 of file CMX_system_cable_input_module.vhd.

data_vme_in in std_logic_vector ( 15 downto 0 )

Port

Definition at line 48 of file CMX_system_cable_input_module.vhd.

data_vme_out out std_logic_vector ( 15 downto 0 )

Port

Definition at line 49 of file CMX_system_cable_input_module.vhd.

ddr_data_in in arr_RTM ( num_RTM_cables - 1 downto 0 )

Port

Definition at line 34 of file CMX_system_cable_input_module.vhd.

ds in std_logic

Port

Definition at line 46 of file CMX_system_cable_input_module.vhd.

IEEE

Library

Definition at line 15 of file CMX_system_cable_input_module.vhd.

IEEE.NUMERIC_STD.all

Package

Definition at line 17 of file CMX_system_cable_input_module.vhd.

IEEE.STD_LOGIC_1164.all

Package

Definition at line 16 of file CMX_system_cable_input_module.vhd.

ncs in std_logic

Port

Definition at line 44 of file CMX_system_cable_input_module.vhd.

parity_error_total out std_logic

Port

Definition at line 33 of file CMX_system_cable_input_module.vhd.

pll_locked in std_logic

Port

Definition at line 37 of file CMX_system_cable_input_module.vhd.

pll_locked_ds2 in std_logic

Port

Definition at line 38 of file CMX_system_cable_input_module.vhd.

quiet in std_logic

Port

Definition at line 39 of file CMX_system_cable_input_module.vhd.

rd_nwr in std_logic

Port

Definition at line 45 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit in std_logic

Port

Definition at line 42 of file CMX_system_cable_input_module.vhd.

start_playback in std_logic

Port

Definition at line 40 of file CMX_system_cable_input_module.vhd.

UNISIM

Library

Definition at line 19 of file CMX_system_cable_input_module.vhd.

UNISIM.VComponents.all

Package

Definition at line 20 of file CMX_system_cable_input_module.vhd.

work

Library

Definition at line 22 of file CMX_system_cable_input_module.vhd.

work.CMX_local_package.all

Package

Definition at line 23 of file CMX_system_cable_input_module.vhd.

work.CMX_VME_defs.all

Package

Definition at line 25 of file CMX_system_cable_input_module.vhd.

work.CMXpackage.all

Package

Definition at line 24 of file CMX_system_cable_input_module.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_system_cable_input_module.vhd