Processes
PROCESS_49	( forwarded_clock (channel) , pll_locked )
PROCESS_50	( forwarded_clock (channel) )
PROCESS_51	( buf_clk40 , pll_locked )
PROCESS_52	( buf_clk40 )
PROCESS_53	( buf_clk40_ds2 , pll_locked_ds2 )
PROCESS_54	( buf_clk40_ds2 )
PROCESS_55	( buf_clk40 , pll_locked )
PROCESS_56	( buf_clk40 )
PROCESS_57	( forwarded_clock (channel) , pll_locked )
PROCESS_58	( forwarded_clock (channel) )
PROCESS_59	( buf_clk40_ds2 , pll_locked_ds2 )
PROCESS_60	( buf_clk40_ds2 )
spy_source_addr_proc	( forwarded_clock (channel) )
spy_system_addr_proc	( buf_clk40 )
spy_systemds2_addr_proc	( buf_clk40_ds2 )
local_buf_master_inhibit	( buf_clk40 , pll_locked )
PROCESS_61	( forwarded_clock (channel) )
local_buf_master_inhibit_system	( buf_clk40 , pll_locked )
local_buf_master_inhibit_systemds2_r	( buf_clk40_ds2 , pll_locked_ds2 )
local_buf_master_inhibit_systemds2	( buf_clk40_ds2 )
PROCESS_62	( buf_clk40_ds2 , pll_locked_ds2 )
PROCESS_63	( buf_clk40 , pll_locked )
PROCESS_64	( forwarded_clock (channel) )
PROCESS_65	( buf_clk40 )
error_detect_process_source	( forwarded_clock (channel) )
PROCESS_66	( forwarded_clock (channel) )
error_detect_process_system	( buf_clk40 )
PROCESS_67	( buf_clk40 )
error_detect_process_systemds2	( forwarded_clock (channel) )
PROCESS_68	( forwarded_clock (channel) )
PROCESS_69	( buf_clk40 )
PROCESS_70	( buf_clk40 , pll_locked )
PROCESS_71	( forwarded_clock (channel) )
PROCESS_72	( forwarded_clock (channel) , pll_locked )
PROCESS_73	( buf_clk40_ds2 )
PROCESS_74	( buf_clk40_ds2 , pll_locked_ds2 )

Constants
mem_select_addr_width	integer := addr_port_width ( num_RTM_cables )

Signals
data_sdr_unmasked	arr_RTM_sdr
data_sdr	arr_RTM_sdr
data_sdr_r_SOURCE	arr_RTM_sdr
data_sdr_r_SYSTEMDS2	arr_RTM_sdr
data_sdr_rr_SYSTEMDS2	arr_RTM_sdr
data_DS2	arr_RTM_sdr
data_DS2_r_SYSTEM	arr_RTM_sdr
data_DS2_rr_SYSTEM	arr_RTM_sdr
ch_quiet	std_logic_vector ( num_RTM_cables - 1 downto 0 )
channel_mask	std_logic_vector ( num_RTM_cables - 1 downto 0 )
parity_error_unmasked_sig	std_logic_vector ( num_RTM_cables - 1 downto 0 )
parity_error_sig	std_logic_vector ( num_RTM_cables - 1 downto 0 )
parity_error_r_SYSTEMDS2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
parity_error_r_SYSTEMDS2_r_SYSTEM	std_logic_vector ( num_RTM_cables - 1 downto 0 )
parity_error_r_SYSTEMDS2_rr_SYSTEM	std_logic_vector ( num_RTM_cables - 1 downto 0 )
forwarded_clock	std_logic_vector ( num_RTM_cables - 1 downto 0 )
counter_reset	std_logic
counter_reset_unstretched	std_logic
counter_reset_r_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM_r_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM_rr_SOURCE	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM_r_SYSTEMDS2	std_logic_vector ( numactchan - 1 downto 0 )
counter_reset_rr_SYSTEM_rr_SYSTEMDS2	std_logic_vector ( numactchan - 1 downto 0 )
data_from_vme_REG_RW_RTM_INPUT_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_RTM_INPUT_COUNTER_RESET	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_RTM_INPUT_CHANNEL_MASK	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_RTM_INPUT_CHANNEL_MASK	std_logic_vector ( 15 downto 0 )
all_null	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
mode_control_RTM_SPY_SOURCE	std_logic_vector ( 3 downto 0 )
ena_RTM_SPY_SOURCE	std_logic
wea_RTM_SPY_SOURCE	std_logic
addra_RTM_SPY_SOURCE	std_logic_vector ( 7 downto 0 )
mem_select_address_RTM_SPY_SOURCE	std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )
dina_RTM_SPY_SOURCE	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
douta_RTM_SPY_SOURCE	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
port_b_master_inhibit_RTM_SPY_SOURCE	std_logic
ena_rtm_spy_source_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
wea_rtm_spy_source_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
douta_rtm_spy_source_individual	arr_RTM_sdr
clkb_rtm_spy_source_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_source_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
addrb_rtm_spy_source_individual	arr_8 ( num_RTM_cables - 1 downto 0 )
dinb_rtm_spy_source_individual	arr_RTM_sdr
doutb_rtm_spy_source_individual	arr_RTM_sdr
addrb_RTM_SPY_SOURCE_counter	arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_source_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_source_rr_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source_rr_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_source_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_source_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_source_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_source_r_system_rr_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_source_r_system_r_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_source_rr_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_source_r_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source_rr_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source_r_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_source	std_logic
web_rtm_spy_source	std_logic
mode_control_RTM_SPY_SYSTEM	std_logic_vector ( 3 downto 0 )
ena_RTM_SPY_SYSTEM	std_logic
wea_RTM_SPY_SYSTEM	std_logic
addra_RTM_SPY_SYSTEM	std_logic_vector ( 7 downto 0 )
mem_select_address_RTM_SPY_SYSTEM	std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )
dina_RTM_SPY_SYSTEM	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
douta_RTM_SPY_SYSTEM	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
port_b_master_inhibit_RTM_SPY_SYSTEM	std_logic
ena_rtm_spy_system_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
wea_rtm_spy_system_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
douta_rtm_spy_system_individual	arr_RTM_sdr
enb_rtm_spy_system_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_system_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
addrb_rtm_spy_system_individual	arr_8 ( num_RTM_cables - 1 downto 0 )
dinb_rtm_spy_system_individual	arr_RTM_sdr
doutb_rtm_spy_system_individual	arr_RTM_sdr
addrb_RTM_SPY_SYSTEM_counter	arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_system_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_system_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_system_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_system_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_system_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_system_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_system	std_logic
web_rtm_spy_system	std_logic
mode_control_RTM_SPY_SYSTEMDS2	std_logic_vector ( 3 downto 0 )
ena_RTM_SPY_SYSTEMDS2	std_logic
wea_RTM_SPY_SYSTEMDS2	std_logic
addra_RTM_SPY_SYSTEMDS2	std_logic_vector ( 7 downto 0 )
mem_select_address_RTM_SPY_SYSTEMDS2	std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )
dina_RTM_SPY_SYSTEMDS2	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
douta_RTM_SPY_SYSTEMDS2	*std_logic_vector ( numbits_in_RTM_connector 2 - 1 downto 0 )**
port_b_master_inhibit_RTM_SPY_SYSTEMDS2	std_logic
ena_rtm_spy_systemds2_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
wea_rtm_spy_systemds2_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
douta_rtm_spy_systemds2_individual	arr_RTM_sdr
enb_rtm_spy_systemds2_individual	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_systemds2_individual	arr_1 ( num_RTM_cables - 1 downto 0 )
addrb_rtm_spy_systemds2_individual	arr_8 ( num_RTM_cables - 1 downto 0 )
dinb_rtm_spy_systemds2_individual	arr_RTM_sdr
doutb_rtm_spy_systemds2_individual	arr_RTM_sdr
addrb_RTM_SPY_SYSTEMDS2_counter	arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_systemds2_r_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_systemds2_r_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_systemds2_r_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
port_b_master_inhibit_rtm_spy_systemds2_rr_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_systemds2_rr_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_systemds2_rr_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_systemds2	std_logic
enb_rtm_spy_systemds2	std_logic
port_b_master_inhibit_rtm_spy_systemds2_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
web_rtm_spy_systemds2_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
enb_rtm_spy_systemds2_split	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_r_system_r_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_r_system_rr_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_rr_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_r_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
spy_write_inhibit_rr_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_r_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_rr_system	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_r_system_r_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_r_system_rr_source	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_r_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
start_playback_rr_systemds2	std_logic_vector ( num_RTM_cables - 1 downto 0 )
par_err_counter_next	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
par_err_counter	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
data_vme_from_below	*arr_16 ( 4 + 9 num_RTM_cables + 2 downto 0 )**
bus_drive_from_below	*std_logic_vector ( 4 + 9 num_RTM_cables + 2 downto 0 )**
data_to_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS	arr_16 ( num_RTM_cables - 1 downto 0 )
data_from_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_from_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS	std_logic_vector ( 15 downto 0 )
data_to_vme_reg_ro_rtm_spy_source_mem_check_error_0	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_reg_ro_rtm_spy_source_mem_check_error_1	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_reg_ro_rtm_spy_system_mem_check_error_0	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_reg_ro_rtm_spy_system_mem_check_error_1	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_reg_ro_rtm_spy_systemds2_mem_check_error_0	arr_16 ( num_RTM_cables - 1 downto 0 )
data_to_vme_reg_ro_rtm_spy_systemds2_mem_check_error_1	arr_16 ( num_RTM_cables - 1 downto 0 )
bit_error_counter_source_next	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_counter_source	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_latch_source	arr_26 ( num_RTM_cables - 1 downto 0 )
bit_error_detect_source	arr_52 ( num_RTM_cables - 1 downto 0 )
bit_error_counter_system_next	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_counter_system	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_latch_system	arr_26 ( num_RTM_cables - 1 downto 0 )
bit_error_detect_system	arr_52 ( num_RTM_cables - 1 downto 0 )
bit_error_counter_systemds2_next	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_counter_systemds2	arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )
bit_error_latch_systemds2	arr_26 ( num_RTM_cables - 1 downto 0 )
bit_error_detect_systemds2	arr_52 ( num_RTM_cables - 1 downto 0 )

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_inreg_reg_rw_rtm_input_counter_reset	vme_inreg_notri <Entity vme_inreg_notri>
stretch_10_counter_reset	Stretch_10 <Entity Stretch_10>
cmx_generic_spy_mem_control_fsm_inst_source	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
cmx_generic_spy_mem_control_fsm_inst_system	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
cmx_generic_spy_mem_control_fsm_inst_systemds2	CMX_generic_spy_mem_control_FSM <Entity CMX_generic_spy_mem_control_FSM>
cmx_cable_clocked_80mbps_input_module_inst	CMX_cable_clocked_80Mbps_input_module <Entity CMX_cable_clocked_80Mbps_input_module>
blk_mem_a8x52_b8x52_2clock_source	blk_mem_a8x52_b8x52_2clock
blk_mem_a8x52_b8x52_1clock_system	blk_mem_a8x52_b8x52_1clock
blk_mem_a8x52_b8x52_2clock_systemds2	blk_mem_a8x52_b8x52_2clock
vme_inreg_reg_rw_rtm_spy_source_mem_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_outreg_reg_ro_rtm_parity_error_counter_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_parity_error_counter_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_spy_source_mem_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_spy_source_mem_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_spy_system_mem_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_spy_system_mem_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_spy_systemds2_mem_check_error_0	vme_outreg_notri_async <Entity vme_outreg_notri_async>
vme_outreg_reg_ro_rtm_spy_systemds2_mem_check_error_1	vme_outreg_notri_async <Entity vme_outreg_notri_async>
or_all_parity_error_total	or_all <Entity or_all>
vme_inreg_reg_rw_rtm_spy_system_mem_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_inreg_reg_rw_rtm_spy_systemds2_mem_start_address	vme_inreg_notri_async <Entity vme_inreg_notri_async>
vme_inreg_reg_rw_rtm_input_channel_mask	vme_inreg_notri_async <Entity vme_inreg_notri_async>

Detailed Description

Definition at line 56 of file CMX_system_cable_input_module.vhd.

Member Function Documentation

error_detect_process_source	(		forwarded_clock (channel)
	)

Process

Definition at line 1072 of file CMX_system_cable_input_module.vhd.

error_detect_process_system	(		buf_clk40
	)

Process

Definition at line 1109 of file CMX_system_cable_input_module.vhd.

error_detect_process_systemds2	(		forwarded_clock (channel)
	)

Process

Definition at line 1144 of file CMX_system_cable_input_module.vhd.

local_buf_master_inhibit	(	buf_clk40 ,
		pll_locked
	)

Process

Definition at line 845 of file CMX_system_cable_input_module.vhd.

local_buf_master_inhibit_system	(	buf_clk40 ,
		pll_locked
	)

Process

Definition at line 883 of file CMX_system_cable_input_module.vhd.

local_buf_master_inhibit_systemds2	(		buf_clk40_ds2
	)

Process

Definition at line 919 of file CMX_system_cable_input_module.vhd.

local_buf_master_inhibit_systemds2_r	(	buf_clk40_ds2 ,
		pll_locked_ds2
	)

Process

Definition at line 907 of file CMX_system_cable_input_module.vhd.

PROCESS_49	(	forwarded_clock (channel) ,
		pll_locked
	)

Definition at line 550 of file CMX_system_cable_input_module.vhd.

PROCESS_50	(		forwarded_clock (channel)
	)

Process

Definition at line 560 of file CMX_system_cable_input_module.vhd.

PROCESS_51	(	buf_clk40 ,
		pll_locked
	)

Process

Definition at line 569 of file CMX_system_cable_input_module.vhd.

PROCESS_52	(		buf_clk40
	)

Process

Definition at line 577 of file CMX_system_cable_input_module.vhd.

PROCESS_53	(	buf_clk40_ds2 ,
		pll_locked_ds2
	)

Process

Definition at line 588 of file CMX_system_cable_input_module.vhd.

PROCESS_54	(		buf_clk40_ds2
	)

Process

Definition at line 596 of file CMX_system_cable_input_module.vhd.

PROCESS_55	(	buf_clk40 ,
		pll_locked
	)

Definition at line 752 of file CMX_system_cable_input_module.vhd.

PROCESS_56	(		buf_clk40
	)

Process

Definition at line 760 of file CMX_system_cable_input_module.vhd.

PROCESS_57	(	forwarded_clock (channel) ,
		pll_locked
	)

Process

Definition at line 769 of file CMX_system_cable_input_module.vhd.

PROCESS_58	(		forwarded_clock (channel)
	)

Process

Definition at line 779 of file CMX_system_cable_input_module.vhd.

PROCESS_59	(	buf_clk40_ds2 ,
		pll_locked_ds2
	)

Process

Definition at line 787 of file CMX_system_cable_input_module.vhd.

PROCESS_60	(		buf_clk40_ds2
	)

Process

Definition at line 797 of file CMX_system_cable_input_module.vhd.

PROCESS_61	(		forwarded_clock (channel)
	)

Process

Definition at line 861 of file CMX_system_cable_input_module.vhd.

PROCESS_62	(	buf_clk40_ds2 ,
		pll_locked_ds2
	)

Process

Definition at line 938 of file CMX_system_cable_input_module.vhd.

PROCESS_63	(	buf_clk40 ,
		pll_locked
	)

Process

Definition at line 976 of file CMX_system_cable_input_module.vhd.

PROCESS_64	(		forwarded_clock (channel)
	)

Process

Definition at line 1002 of file CMX_system_cable_input_module.vhd.

PROCESS_65 ( buf_clk40 )

Definition at line 1052 of file CMX_system_cable_input_module.vhd.

PROCESS_66	(		forwarded_clock (channel)
	)

Process

Definition at line 1093 of file CMX_system_cable_input_module.vhd.

PROCESS_67	(		buf_clk40
	)

Process

Definition at line 1129 of file CMX_system_cable_input_module.vhd.

PROCESS_68	(		forwarded_clock (channel)
	)

Process

Definition at line 1165 of file CMX_system_cable_input_module.vhd.

PROCESS_69	(		buf_clk40
	)

Process

Definition at line 1182 of file CMX_system_cable_input_module.vhd.

PROCESS_70	(	buf_clk40 ,
		pll_locked
	)

Process

Definition at line 1188 of file CMX_system_cable_input_module.vhd.

PROCESS_71	(		forwarded_clock (channel)
	)

Process

Definition at line 1198 of file CMX_system_cable_input_module.vhd.

PROCESS_72	(	forwarded_clock (channel) ,
		pll_locked
	)

Process

Definition at line 1204 of file CMX_system_cable_input_module.vhd.

PROCESS_73	(		buf_clk40_ds2
	)

Process

Definition at line 1214 of file CMX_system_cable_input_module.vhd.

PROCESS_74	(	buf_clk40_ds2 ,
		pll_locked_ds2
	)

Process

Definition at line 1220 of file CMX_system_cable_input_module.vhd.

spy_source_addr_proc	(		forwarded_clock (channel)
	)

Process

Definition at line 806 of file CMX_system_cable_input_module.vhd.

spy_system_addr_proc	(		buf_clk40
	)

Process

Definition at line 818 of file CMX_system_cable_input_module.vhd.

spy_systemds2_addr_proc	(		buf_clk40_ds2
	)

Process

Definition at line 831 of file CMX_system_cable_input_module.vhd.

Member Data Documentation

addra_RTM_SPY_SOURCE std_logic_vector ( 7 downto 0 )

Signal

Definition at line 192 of file CMX_system_cable_input_module.vhd.

addra_RTM_SPY_SYSTEM std_logic_vector ( 7 downto 0 )

Signal

Definition at line 234 of file CMX_system_cable_input_module.vhd.

addra_RTM_SPY_SYSTEMDS2 std_logic_vector ( 7 downto 0 )

Signal

Definition at line 264 of file CMX_system_cable_input_module.vhd.

addrb_RTM_SPY_SOURCE_counter arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 208 of file CMX_system_cable_input_module.vhd.

addrb_rtm_spy_source_individual arr_8 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 204 of file CMX_system_cable_input_module.vhd.

addrb_RTM_SPY_SYSTEM_counter arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 249 of file CMX_system_cable_input_module.vhd.

addrb_rtm_spy_system_individual arr_8 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 245 of file CMX_system_cable_input_module.vhd.

addrb_RTM_SPY_SYSTEMDS2_counter arr_ctr_8bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 279 of file CMX_system_cable_input_module.vhd.

addrb_rtm_spy_systemds2_individual arr_8 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 275 of file CMX_system_cable_input_module.vhd.

all_null std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 162 of file CMX_system_cable_input_module.vhd.

bit_error_counter_source arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 409 of file CMX_system_cable_input_module.vhd.

bit_error_counter_source_next arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 408 of file CMX_system_cable_input_module.vhd.

bit_error_counter_system arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 414 of file CMX_system_cable_input_module.vhd.

bit_error_counter_system_next arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 413 of file CMX_system_cable_input_module.vhd.

bit_error_counter_systemds2 arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 419 of file CMX_system_cable_input_module.vhd.

bit_error_counter_systemds2_next arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 418 of file CMX_system_cable_input_module.vhd.

bit_error_detect_source arr_52 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 411 of file CMX_system_cable_input_module.vhd.

bit_error_detect_system arr_52 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 416 of file CMX_system_cable_input_module.vhd.

bit_error_detect_systemds2 arr_52 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 421 of file CMX_system_cable_input_module.vhd.

bit_error_latch_source arr_26 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 410 of file CMX_system_cable_input_module.vhd.

bit_error_latch_system arr_26 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 415 of file CMX_system_cable_input_module.vhd.

bit_error_latch_systemds2 arr_26 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 420 of file CMX_system_cable_input_module.vhd.

blk_mem_A8x52_B8x52_1clock

Component

Definition at line 126 of file CMX_system_cable_input_module.vhd.

blk_mem_a8x52_b8x52_1clock_system blk_mem_a8x52_b8x52_1clock

Instantiation

Definition at line 661 of file CMX_system_cable_input_module.vhd.

blk_mem_A8x52_B8x52_2clock

Component

Definition at line 110 of file CMX_system_cable_input_module.vhd.

blk_mem_a8x52_b8x52_2clock_source blk_mem_a8x52_b8x52_2clock

Instantiation

Definition at line 625 of file CMX_system_cable_input_module.vhd.

blk_mem_a8x52_b8x52_2clock_systemds2 blk_mem_a8x52_b8x52_2clock

Instantiation

Definition at line 696 of file CMX_system_cable_input_module.vhd.

bus_drive_from_below std_logic_vector ( 4 + 9 * num_RTM_cables + 2 downto 0 )

Signal

Definition at line 323 of file CMX_system_cable_input_module.vhd.

ch_quiet std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 90 of file CMX_system_cable_input_module.vhd.

channel_mask std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 92 of file CMX_system_cable_input_module.vhd.

clkb_rtm_spy_source_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 201 of file CMX_system_cable_input_module.vhd.

CMX_cable_clocked_80Mbps_input_module

Component

Definition at line 60 of file CMX_system_cable_input_module.vhd.

cmx_cable_clocked_80mbps_input_module_inst CMX_cable_clocked_80Mbps_input_module

Instantiation

Definition at line 605 of file CMX_system_cable_input_module.vhd.

CMX_generic_spy_mem_control_FSM

Component

Definition at line 164 of file CMX_system_cable_input_module.vhd.

cmx_generic_spy_mem_control_fsm_inst_source CMX_generic_spy_mem_control_FSM

Instantiation

Definition at line 471 of file CMX_system_cable_input_module.vhd.

cmx_generic_spy_mem_control_fsm_inst_system CMX_generic_spy_mem_control_FSM

Instantiation

Definition at line 496 of file CMX_system_cable_input_module.vhd.

cmx_generic_spy_mem_control_fsm_inst_systemds2 CMX_generic_spy_mem_control_FSM

Instantiation

Definition at line 520 of file CMX_system_cable_input_module.vhd.

counter_reset std_logic

Signal

Definition at line 143 of file CMX_system_cable_input_module.vhd.

counter_reset_r_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 151 of file CMX_system_cable_input_module.vhd.

counter_reset_rr_SYSTEM std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 151 of file CMX_system_cable_input_module.vhd.

counter_reset_rr_SYSTEM_r_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 151 of file CMX_system_cable_input_module.vhd.

counter_reset_rr_SYSTEM_r_SYSTEMDS2 std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 151 of file CMX_system_cable_input_module.vhd.

counter_reset_rr_SYSTEM_rr_SOURCE std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 151 of file CMX_system_cable_input_module.vhd.

counter_reset_rr_SYSTEM_rr_SYSTEMDS2 std_logic_vector ( numactchan - 1 downto 0 )

Signal

Definition at line 151 of file CMX_system_cable_input_module.vhd.

counter_reset_unstretched std_logic

Signal

Definition at line 143 of file CMX_system_cable_input_module.vhd.

data_DS2 arr_RTM_sdr

Signal

Definition at line 84 of file CMX_system_cable_input_module.vhd.

data_DS2_r_SYSTEM arr_RTM_sdr

Signal

Definition at line 86 of file CMX_system_cable_input_module.vhd.

data_DS2_rr_SYSTEM arr_RTM_sdr

Signal

Definition at line 87 of file CMX_system_cable_input_module.vhd.

data_from_vme_REG_RW_RTM_INPUT_CHANNEL_MASK std_logic_vector ( 15 downto 0 )

Signal

Definition at line 159 of file CMX_system_cable_input_module.vhd.

data_from_vme_REG_RW_RTM_INPUT_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 153 of file CMX_system_cable_input_module.vhd.

data_from_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 397 of file CMX_system_cable_input_module.vhd.

data_from_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 398 of file CMX_system_cable_input_module.vhd.

data_from_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 399 of file CMX_system_cable_input_module.vhd.

data_sdr arr_RTM_sdr

Signal

Definition at line 77 of file CMX_system_cable_input_module.vhd.

data_sdr_r_SOURCE arr_RTM_sdr

Signal

Definition at line 78 of file CMX_system_cable_input_module.vhd.

data_sdr_r_SYSTEMDS2 arr_RTM_sdr

Signal

Definition at line 79 of file CMX_system_cable_input_module.vhd.

data_sdr_rr_SYSTEMDS2 arr_RTM_sdr

Signal

Definition at line 80 of file CMX_system_cable_input_module.vhd.

data_sdr_unmasked arr_RTM_sdr

Signal

Definition at line 76 of file CMX_system_cable_input_module.vhd.

data_to_vme_reg_ro_rtm_spy_source_mem_check_error_0 arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 401 of file CMX_system_cable_input_module.vhd.

data_to_vme_reg_ro_rtm_spy_source_mem_check_error_1 arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 402 of file CMX_system_cable_input_module.vhd.

data_to_vme_reg_ro_rtm_spy_system_mem_check_error_0 arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 403 of file CMX_system_cable_input_module.vhd.

data_to_vme_reg_ro_rtm_spy_system_mem_check_error_1 arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 404 of file CMX_system_cable_input_module.vhd.

data_to_vme_reg_ro_rtm_spy_systemds2_mem_check_error_0 arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 405 of file CMX_system_cable_input_module.vhd.

data_to_vme_reg_ro_rtm_spy_systemds2_mem_check_error_1 arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 406 of file CMX_system_cable_input_module.vhd.

data_to_vme_REG_RW_RTM_INPUT_CHANNEL_MASK std_logic_vector ( 15 downto 0 )

Signal

Definition at line 160 of file CMX_system_cable_input_module.vhd.

data_to_vme_REG_RW_RTM_INPUT_COUNTER_RESET std_logic_vector ( 15 downto 0 )

Signal

Definition at line 156 of file CMX_system_cable_input_module.vhd.

data_to_vme_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS arr_16 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 394 of file CMX_system_cable_input_module.vhd.

data_to_vme_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 395 of file CMX_system_cable_input_module.vhd.

data_to_vme_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS std_logic_vector ( 15 downto 0 )

Signal

Definition at line 396 of file CMX_system_cable_input_module.vhd.

data_vme_from_below arr_16 ( 4 + 9 * num_RTM_cables + 2 downto 0 )

Signal

Definition at line 322 of file CMX_system_cable_input_module.vhd.

dina_RTM_SPY_SOURCE std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 194 of file CMX_system_cable_input_module.vhd.

dina_RTM_SPY_SYSTEM std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 236 of file CMX_system_cable_input_module.vhd.

dina_RTM_SPY_SYSTEMDS2 std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 266 of file CMX_system_cable_input_module.vhd.

dinb_rtm_spy_source_individual arr_RTM_sdr

Signal

Definition at line 205 of file CMX_system_cable_input_module.vhd.

dinb_rtm_spy_system_individual arr_RTM_sdr

Signal

Definition at line 246 of file CMX_system_cable_input_module.vhd.

dinb_rtm_spy_systemds2_individual arr_RTM_sdr

Signal

Definition at line 276 of file CMX_system_cable_input_module.vhd.

douta_RTM_SPY_SOURCE std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 195 of file CMX_system_cable_input_module.vhd.

douta_rtm_spy_source_individual arr_RTM_sdr

Signal

Definition at line 200 of file CMX_system_cable_input_module.vhd.

douta_RTM_SPY_SYSTEM std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 237 of file CMX_system_cable_input_module.vhd.

douta_rtm_spy_system_individual arr_RTM_sdr

Signal

Definition at line 242 of file CMX_system_cable_input_module.vhd.

douta_RTM_SPY_SYSTEMDS2 std_logic_vector ( numbits_in_RTM_connector * 2 - 1 downto 0 )

Signal

Definition at line 267 of file CMX_system_cable_input_module.vhd.

douta_rtm_spy_systemds2_individual arr_RTM_sdr

Signal

Definition at line 272 of file CMX_system_cable_input_module.vhd.

doutb_rtm_spy_source_individual arr_RTM_sdr

Signal

Definition at line 206 of file CMX_system_cable_input_module.vhd.

doutb_rtm_spy_system_individual arr_RTM_sdr

Signal

Definition at line 247 of file CMX_system_cable_input_module.vhd.

doutb_rtm_spy_systemds2_individual arr_RTM_sdr

Signal

Definition at line 277 of file CMX_system_cable_input_module.vhd.

ena_RTM_SPY_SOURCE std_logic

Signal

Definition at line 190 of file CMX_system_cable_input_module.vhd.

ena_rtm_spy_source_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 198 of file CMX_system_cable_input_module.vhd.

ena_RTM_SPY_SYSTEM std_logic

Signal

Definition at line 232 of file CMX_system_cable_input_module.vhd.

ena_rtm_spy_system_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 240 of file CMX_system_cable_input_module.vhd.

ena_RTM_SPY_SYSTEMDS2 std_logic

Signal

Definition at line 262 of file CMX_system_cable_input_module.vhd.

ena_rtm_spy_systemds2_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 270 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source std_logic

Signal

Definition at line 225 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 202 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source_r_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 224 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 215 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source_rr_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 223 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source_rr_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 213 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_source_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 218 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_system std_logic

Signal

Definition at line 257 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_system_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 243 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_system_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 253 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_system_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 255 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_systemds2 std_logic

Signal

Definition at line 288 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_systemds2_individual std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 273 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_systemds2_r_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 283 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_systemds2_rr_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 286 of file CMX_system_cable_input_module.vhd.

enb_rtm_spy_systemds2_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 293 of file CMX_system_cable_input_module.vhd.

forwarded_clock std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 107 of file CMX_system_cable_input_module.vhd.

mem_select_addr_width integer := addr_port_width ( num_RTM_cables )

Constant

Definition at line 58 of file CMX_system_cable_input_module.vhd.

mem_select_address_RTM_SPY_SOURCE std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )

Signal

Definition at line 193 of file CMX_system_cable_input_module.vhd.

mem_select_address_RTM_SPY_SYSTEM std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )

Signal

Definition at line 235 of file CMX_system_cable_input_module.vhd.

mem_select_address_RTM_SPY_SYSTEMDS2 std_logic_vector ( addr_port_width ( num_RTM_cables ) - 1 downto 0 )

Signal

Definition at line 265 of file CMX_system_cable_input_module.vhd.

mode_control_RTM_SPY_SOURCE std_logic_vector ( 3 downto 0 )

Signal

Definition at line 189 of file CMX_system_cable_input_module.vhd.

mode_control_RTM_SPY_SYSTEM std_logic_vector ( 3 downto 0 )

Signal

Definition at line 231 of file CMX_system_cable_input_module.vhd.

mode_control_RTM_SPY_SYSTEMDS2 std_logic_vector ( 3 downto 0 )

Signal

Definition at line 261 of file CMX_system_cable_input_module.vhd.

or_all

Component

Definition at line 423 of file CMX_system_cable_input_module.vhd.

or_all_parity_error_total or_all

Instantiation

Definition at line 1328 of file CMX_system_cable_input_module.vhd.

par_err_counter arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 312 of file CMX_system_cable_input_module.vhd.

par_err_counter_next arr_ctr_32bit ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 311 of file CMX_system_cable_input_module.vhd.

parity_error_r_SYSTEMDS2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 98 of file CMX_system_cable_input_module.vhd.

parity_error_r_SYSTEMDS2_r_SYSTEM std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 99 of file CMX_system_cable_input_module.vhd.

parity_error_r_SYSTEMDS2_rr_SYSTEM std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 100 of file CMX_system_cable_input_module.vhd.

parity_error_sig std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 96 of file CMX_system_cable_input_module.vhd.

parity_error_unmasked_sig std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 95 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_RTM_SPY_SOURCE std_logic

Signal

Definition at line 196 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_source_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 211 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_source_r_system_r_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 220 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_source_r_system_rr_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 219 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_source_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 216 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_RTM_SPY_SYSTEM std_logic

Signal

Definition at line 238 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_system_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 251 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_system_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 254 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_RTM_SPY_SYSTEMDS2 std_logic

Signal

Definition at line 268 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_systemds2_r_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 281 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_systemds2_rr_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 284 of file CMX_system_cable_input_module.vhd.

port_b_master_inhibit_rtm_spy_systemds2_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 291 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 298 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit_r_system_r_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 296 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit_r_system_rr_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 297 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit_r_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 300 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit_rr_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 299 of file CMX_system_cable_input_module.vhd.

spy_write_inhibit_rr_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 301 of file CMX_system_cable_input_module.vhd.

start_playback_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 304 of file CMX_system_cable_input_module.vhd.

start_playback_r_system_r_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 306 of file CMX_system_cable_input_module.vhd.

start_playback_r_system_rr_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 307 of file CMX_system_cable_input_module.vhd.

start_playback_r_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 308 of file CMX_system_cable_input_module.vhd.

start_playback_rr_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 305 of file CMX_system_cable_input_module.vhd.

start_playback_rr_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 309 of file CMX_system_cable_input_module.vhd.

Stretch_10

Component

Definition at line 144 of file CMX_system_cable_input_module.vhd.

stretch_10_counter_reset Stretch_10

Instantiation

Definition at line 463 of file CMX_system_cable_input_module.vhd.

vme_inreg_notri

Component

Definition at line 326 of file CMX_system_cable_input_module.vhd.

vme_inreg_notri_async

Component

Definition at line 345 of file CMX_system_cable_input_module.vhd.

vme_inreg_reg_rw_rtm_input_channel_mask vme_inreg_notri_async

Instantiation

Definition at line 1396 of file CMX_system_cable_input_module.vhd.

vme_inreg_reg_rw_rtm_input_counter_reset vme_inreg_notri

Instantiation

Definition at line 442 of file CMX_system_cable_input_module.vhd.

vme_inreg_reg_rw_rtm_spy_source_mem_start_address vme_inreg_notri_async

Instantiation

Definition at line 731 of file CMX_system_cable_input_module.vhd.

vme_inreg_reg_rw_rtm_spy_system_mem_start_address vme_inreg_notri_async

Instantiation

Definition at line 1361 of file CMX_system_cable_input_module.vhd.

vme_inreg_reg_rw_rtm_spy_systemds2_mem_start_address vme_inreg_notri_async

Instantiation

Definition at line 1379 of file CMX_system_cable_input_module.vhd.

vme_local_switch

Component

Definition at line 314 of file CMX_system_cable_input_module.vhd.

vme_local_switch_inst vme_local_switch

Instantiation

Definition at line 435 of file CMX_system_cable_input_module.vhd.

vme_outreg_notri

Component

Definition at line 361 of file CMX_system_cable_input_module.vhd.

vme_outreg_notri_async

Component

Definition at line 378 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_parity_error_counter_0 vme_outreg_notri_async

Instantiation

Definition at line 1024 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_parity_error_counter_1 vme_outreg_notri_async

Instantiation

Definition at line 1038 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_spy_source_mem_check_error_0 vme_outreg_notri_async

Instantiation

Definition at line 1243 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_spy_source_mem_check_error_1 vme_outreg_notri_async

Instantiation

Definition at line 1256 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_spy_system_mem_check_error_0 vme_outreg_notri_async

Instantiation

Definition at line 1270 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_spy_system_mem_check_error_1 vme_outreg_notri_async

Instantiation

Definition at line 1283 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_spy_systemds2_mem_check_error_0 vme_outreg_notri_async

Instantiation

Definition at line 1297 of file CMX_system_cable_input_module.vhd.

vme_outreg_reg_ro_rtm_spy_systemds2_mem_check_error_1 vme_outreg_notri_async

Instantiation

Definition at line 1310 of file CMX_system_cable_input_module.vhd.

wea_RTM_SPY_SOURCE std_logic

Signal

Definition at line 191 of file CMX_system_cable_input_module.vhd.

wea_rtm_spy_source_individual arr_1 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 199 of file CMX_system_cable_input_module.vhd.

wea_RTM_SPY_SYSTEM std_logic

Signal

Definition at line 233 of file CMX_system_cable_input_module.vhd.

wea_rtm_spy_system_individual arr_1 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 241 of file CMX_system_cable_input_module.vhd.

wea_RTM_SPY_SYSTEMDS2 std_logic

Signal

Definition at line 263 of file CMX_system_cable_input_module.vhd.

wea_rtm_spy_systemds2_individual arr_1 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 271 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source std_logic

Signal

Definition at line 226 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source_individual arr_1 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 203 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source_r_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 222 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 214 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source_rr_source std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 221 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source_rr_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 212 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_source_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 217 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_system std_logic

Signal

Definition at line 258 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_system_individual arr_1 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 244 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_system_r_system std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 252 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_system_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 256 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_systemds2 std_logic

Signal

Definition at line 287 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_systemds2_individual arr_1 ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 274 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_systemds2_r_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 282 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_systemds2_rr_systemds2 std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 285 of file CMX_system_cable_input_module.vhd.

web_rtm_spy_systemds2_split std_logic_vector ( num_RTM_cables - 1 downto 0 )

Signal

Definition at line 292 of file CMX_system_cable_input_module.vhd.

The documentation for this class was generated from the following file:

Common/trunk/sources/CMX_system_cable_input_module.vhd

Components
CMX_cable_clocked_80Mbps_input_module	<Entity CMX_cable_clocked_80Mbps_input_module>
blk_mem_A8x52_B8x52_2clock
blk_mem_A8x52_B8x52_1clock
Stretch_10	<Entity Stretch_10>
CMX_generic_spy_mem_control_FSM	<Entity CMX_generic_spy_mem_control_FSM>
vme_local_switch	<Entity vme_local_switch>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>
vme_outreg_notri	<Entity vme_outreg_notri>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>
or_all	<Entity or_all>

Processes

Components

Constants

Signals

Instantiations

Detailed Description

Member Function Documentation

Member Data Documentation