CMX_delay_generator.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.MATH_REAL.ALL;

use work.CMXpackage.all;

entity CMX_delay_generator is
  generic (
      start_address : integer);         --400(d) will be used starting at the
                                        --specified address 
  port (
    clk40         : in    std_logic;    --system clock
    ncs           : in    std_logic;    --ports forwarded to the vme register instances
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic;
    del_register  : out del_register_type;  -- result read from the registers;
    upload_delays : out std_logic
  );
end CMX_delay_generator;

architecture Behavioral of CMX_delay_generator is


  
  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;

  component vme_inreg_notri is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      clk           : in  std_logic;
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0);
      read_detect   : out std_logic;
      write_detect  : out std_logic);
  end component vme_inreg_notri;
 
  --note no -1 on because clock line adds one signal
  --signal write_detect : std_logic_vector(numactchan*(numbitsinchan+1) - 1  downto 0);
  signal data_from_vme : arr_16( numactchan*(numbitsinchan+1) - 1  downto 0); 
  signal data_to_vme : arr_16( numactchan*(numbitsinchan+1) - 1  downto 0);

  signal data_vme_out_local : arr_16( numactchan*(numbitsinchan+1) - 1  downto 0);
  signal bus_drive_local : std_logic_vector(numactchan*(numbitsinchan+1) - 1  downto 0);
  
begin


  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local);
  
  gen_inreg_assign_chan: for ichannel in  numactchan-1 downto 0 generate
    --no -1 because the clock adds one:
    gen_inreg_assign_sig: for ibit in  numbitsinchan downto 0 generate

      --all register except for the last one are acynchroneous
      gen_async: if ichannel /= numactchan-1 or ibit /= numbitsinchan generate
        --ireg=ichannel*(numbitsinchan+1)+ibit --(+1 is for clock)

        vme_inreg_notri_async_inst : entity work.vme_inreg_notri_async
          generic map (
            ia_vme  => start_address+2* (ichannel*(numbitsinchan+1)+ibit),
            width   => 16)
          port map (
            ncs            => ncs,
            rd_nwr         => rd_nwr,
            ds             => ds,
            addr_vme       => addr_vme,
            data_vme_in    => data_vme_in,
            data_vme_out   => data_vme_out_local(ichannel*(numbitsinchan+1)+ibit),
            bus_drive      => bus_drive_local(ichannel*(numbitsinchan+1)+ibit),
            data_from_vme  => data_from_vme(ichannel*(numbitsinchan+1)+ibit),
            data_to_vme    => data_to_vme(ichannel*(numbitsinchan+1)+ibit));
        
        --vme_inreg_async_inst: vme_inreg_async
        --  generic map (
        --    ia_vme => start_address+2*(ichannel*(numbitsinchan+1)+ibit),
        --    width  => 16)
        --  port map (
        --    ncs           => ncs,
        --    rd_nwr        => rd_nwr,
        --    ds            => ds,
        --    addr_vme      => addr_vme,
        --    data_vme      => data_vme,
        --    data_from_vme => data_from_vme(ichannel*(numbitsinchan+1)+ibit),
        --    data_to_vme   => data_to_vme(ichannel*(numbitsinchan+1)+ibit));
        
      end generate gen_async;

      gen_sync: if ichannel = numactchan-1 and ibit = numbitsinchan generate
        --ireg=ichannel*(numbitsinchan+1)+ibit --(+1 is for clock)
        vme_inreg_notri_1: entity work.vme_inreg_notri
          generic map (
            ia_vme  => start_address+2* (ichannel*(numbitsinchan+1)+ibit),
            width   => 16)
          port map (
            clk            => clk40,
            ncs            => ncs,
            rd_nwr         => rd_nwr,
            ds             => ds,
            addr_vme       => addr_vme,
            data_vme_in    => data_vme_in,
            data_vme_out   => data_vme_out_local(ichannel*(numbitsinchan+1)+ibit),
            bus_drive      => bus_drive_local(ichannel*(numbitsinchan+1)+ibit),
            data_from_vme  => data_from_vme(ichannel*(numbitsinchan+1)+ibit),
            data_to_vme    => data_to_vme(ichannel*(numbitsinchan+1)+ibit),
            read_detect    => open,
            write_detect   => upload_delays);
        
        --vme_inreg_sync_inst: vme_inreg
        --  generic map (
        --    ia_vme => start_address+2*(ichannel*(numbitsinchan+1)+ibit),
        --    width  => 16)
        --  port map (
        --    clk           => clk40,
        --    ncs           => ncs,
        --    rd_nwr        => rd_nwr,
        --    ds            => ds,
        --    addr_vme      => addr_vme,
        --    data_vme      => data_vme,
        --    data_from_vme => data_from_vme(ichannel*(numbitsinchan+1)+ibit),
        --    data_to_vme   => data_to_vme(ichannel*(numbitsinchan+1)+ibit),
        --    read_detect   => open,
        --    write_detect  => upload_delays);
      end generate gen_sync;

      
      
      del_register( ichannel, ibit ) <= data_from_vme(ichannel*(numbitsinchan+1)+ibit)(4 downto 0);
      data_to_vme(ichannel*(numbitsinchan+1)+ibit)<=data_from_vme(ichannel*(numbitsinchan+1)+ibit);
      
    end generate gen_inreg_assign_sig;
  end generate gen_inreg_assign_chan;

  --upload_delays<=write_detect(write_detect'high);
    
end Behavioral;