7 ----------------------------------------------------------------------------------
9 use IEEE.STD_LOGIC_1164.
ALL;
16 -- Uncomment the following library declaration if using
17 -- arithmetic functions with Signed or Unsigned values
20 -- Uncomment the following library declaration if instantiating
21 -- any Xilinx primitives in this code.
23 --use UNISIM.VComponents.all;
28 local_data :
in (4*26-1
downto 0);
30 -- this instructs the modules downstream to plug in the alignment word.
33 Data_out : out (TX_indata_length - 1 downto 0);
38 end CMX_SumET_Topo_Encoder;
51 signal sumX : (14 downto 0);
53 signal sumY : (14 downto 0);
62 --adjust the bcid for the latency of calculating the local data
65 if rising_edge(clk) then
104 gen_all_Topo_data: for i_fiber in (num_GTX_groups * num_GTX_per_group)-1 downto 0 generate
106 non_empty: if i_fiber=5 or i_fiber=7 or i_fiber=9 or i_fiber=11 generate
108 end generate non_empty;
110 empty: if i_fiber/=5 and i_fiber/=7 and i_fiber/=9 and i_fiber/=11 generate
111 Data_out(128*(fiber_to_gtx(i_fiber)+1)-1 downto 128*fiber_to_gtx(i_fiber))<=(others=>'0');
114 end generate gen_all_Topo_data;
std_logic_vector (14 downto 0) sumX
out bcid_adjstd_logic_vector (11 downto 0)
std_logic_vector (127 downto 0) non_empty_row
out send_align_outstd_logic_vector (num_GTX_groups * num_GTX_per_group - 1 downto 0)
std_logic_vector (14 downto 0) sumET_res
in local_datastd_logic_vector (4 * 26 - 1 downto 0)
std_logic_vector (14 downto 0) sumY_res
std_logic_vector (14 downto 0) sumET
std_logic_vector (14 downto 0) sumX_res
std_logic_vector (14 downto 0) sumY
in bcid_instd_logic_vector (11 downto 0)
std_logic_vector (95 downto 0) descrambled_local_data
out Data_outstd_logic_vector (TX_indata_length - 1 downto 0)