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CMX_SumET_Topo_Encoder.vhd
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1 
6 
7 ----------------------------------------------------------------------------------
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.ALL;
10 
11 library work;
12 use work.CMXpackage.all;
14 
15 
16 -- Uncomment the following library declaration if using
17 -- arithmetic functions with Signed or Unsigned values
18 use IEEE.NUMERIC_STD.ALL;
19 
20 -- Uncomment the following library declaration if instantiating
21 -- any Xilinx primitives in this code.
22 --library UNISIM;
23 --use UNISIM.VComponents.all;
24 
26  port (
27 
28  local_data : in std_logic_vector(4*26-1 downto 0);
29 
30  -- this instructs the modules downstream to plug in the alignment word.
31  send_align_out : out std_logic_vector(num_GTX_groups*num_GTX_per_group - 1 downto 0);
32 
33  Data_out : out std_logic_vector(TX_indata_length - 1 downto 0);
34  bcid_in : in std_logic_vector(11 downto 0);
35  bcid_adj : out std_logic_vector(11 downto 0);
36 
37  clk :in std_logic);
38 end CMX_SumET_Topo_Encoder;
39 
40 architecture Behavioral of CMX_SumET_Topo_Encoder is
41 
42  signal sumET_res : std_logic_vector(14 downto 0);
43  signal sumET_res_ov : std_logic;
44  signal sumX_res : std_logic_vector(14 downto 0);
45  signal sumX_res_ov : std_logic;
46  signal sumY_res : std_logic_vector(14 downto 0);
47  signal sumY_res_ov : std_logic;
48 
49  signal sumET : std_logic_vector(14 downto 0);
50  signal sumET_ov : std_logic;
51  signal sumX : std_logic_vector(14 downto 0);
52  signal sumX_ov : std_logic;
53  signal sumY : std_logic_vector(14 downto 0);
54  signal sumY_ov : std_logic;
55 
56  signal non_empty_row : std_logic_vector(127 downto 0);
57 
58  signal descrambled_local_data : std_logic_vector(95 downto 0);
59 
60 begin
61 
62  --adjust the bcid for the latency of calculating the local data
63  process(clk)
64  begin
65  if rising_edge(clk) then
67  end if;
68  end process;
69 
70  descrambled_local_data<=crate_cable_in(local_data);
71 
72  sumX<=descrambled_local_data(14 downto 0);
74  sumY<=descrambled_local_data(29 downto 15);
76  sumET<=descrambled_local_data(44 downto 30);
78 
79  sumX_res<=descrambled_local_data(59 downto 45);
81  sumY_res<=descrambled_local_data(74 downto 60);
83  sumET_res<=descrambled_local_data(89 downto 75);
85 
86 
88  non_empty_row(126 downto 112)<=sumET_res;
89  non_empty_row(111)<=sumET_ov;
90  non_empty_row(110 downto 96)<=sumET;
91 
93  non_empty_row(94 downto 80)<=sumY_res;
95  non_empty_row(78 downto 72)<=sumY(14 downto 8);
96  non_empty_row(71 downto 52)<=(others=>'0');
97  non_empty_row(51 downto 44)<=sumY(7 downto 0);
99  non_empty_row(42 downto 28)<=sumX_res;
100  non_empty_row(27)<=sumX_ov;
101  non_empty_row(26 downto 12)<=sumX;
102  non_empty_row(11 downto 0)<=(others=>'0');
103 
104  gen_all_Topo_data: for i_fiber in (num_GTX_groups * num_GTX_per_group)-1 downto 0 generate
105 
106  non_empty: if i_fiber=5 or i_fiber=7 or i_fiber=9 or i_fiber=11 generate
107  Data_out(128*(fiber_to_gtx(i_fiber)+1)-1 downto 128*fiber_to_gtx(i_fiber))<=non_empty_row;
108  end generate non_empty;
109 
110  empty: if i_fiber/=5 and i_fiber/=7 and i_fiber/=9 and i_fiber/=11 generate
111  Data_out(128*(fiber_to_gtx(i_fiber)+1)-1 downto 128*fiber_to_gtx(i_fiber))<=(others=>'0');
112  end generate empty;
113 
114  end generate gen_all_Topo_data;
115 
116  send_align_out<=(others=>'1');
117 
118 end Behavioral;
119 
std_logic_vector (14 downto 0) sumX
out bcid_adjstd_logic_vector (11 downto 0)
_library_ IEEEIEEE
Definition: CMX_SumEt.vhd:7
std_logic_vector (127 downto 0) non_empty_row
_library_ workwork
Definition: CMX_SumEt.vhd:11
out send_align_outstd_logic_vector (num_GTX_groups * num_GTX_per_group - 1 downto 0)
std_logic_vector (14 downto 0) sumET_res
in local_datastd_logic_vector (4 * 26 - 1 downto 0)
std_logic_vector (14 downto 0) sumY_res
std_logic_vector (14 downto 0) sumET
std_logic_vector (14 downto 0) sumX_res
std_logic_vector (14 downto 0) sumY
in bcid_instd_logic_vector (11 downto 0)
std_logic_vector (95 downto 0) descrambled_local_data
out Data_outstd_logic_vector (TX_indata_length - 1 downto 0)