CMX_SumEt.vhd

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library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
use work.CMX_VME_defs.all;
use work.CMXpackage.all;
use work.CMX_flavor_package.all;



entity CMX_Sum_Et is

  port (
    CLK           : in  std_logic;
    --SYSTEM
    ENERGY_REMOTE : in  std_logic_vector(26*4-1 downto 0);
    CTP_CABLE_0   : out std_logic_vector(23 downto 0);
    CTP_CABLE_1   : out std_logic_vector(23 downto 0);
    -- thresholds
    MISS_E_THR         : in arr_ctr_31bit(num_thresholds-1 downto 0);
    MISS_E_RES_THR     : in arr_ctr_31bit(num_thresholds-1 downto 0);
    SUM_ET_THR         : in arr_ctr_15bit(num_thresholds-1 downto 0);
    SUM_ET_RES_THR     : in arr_ctr_15bit(num_thresholds-1 downto 0);
    XS_T2_A2           : in arr_ctr_31bit(num_thresholds-1 downto 0);
    -- parameters
    T_MISS_E_MIN    : in arr_ctr_31bit(num_thresholds-1 downto 0); 
    T_MISS_E_MAX    : in arr_ctr_31bit(num_thresholds-1 downto 0);
    T_SUM_E_MIN     : in arr_ctr_15bit(num_thresholds-1 downto 0);
    T_SUM_E_MAX     : in arr_ctr_15bit(num_thresholds-1 downto 0);
    XS_B2           : in arr_ctr_15bit(num_thresholds-1 downto 0);
    ov_all_out        : out std_logic_vector(5 downto 0);
    sums_all_out      : out arr_ctr_15bit(5 downto 0);
    --CRATE
    BACKPLANE_DATA_IN : in  energy_array;
    LOCAL_CABLE_OUT   : out std_logic_vector(4*26-1 downto 0);
    BCID_in          : in std_logic_vector(11 downto 0);
    BCID_delayed     : out std_logic_vector(11 downto 0);
    -- counter signals
    counter_reset        : in  T_SL;
    counter_inhibit      : in  T_SL;
     
    par_err          : in std_logic_vector(1 downto 0); -- parity error (input module - 0, RTM - 1)
     force            : in T_SL; -- force
    --VME
    ncs           : in    std_logic;    --ports forwarded to the vme register instances
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
         
    );
end CMX_Sum_Et;

architecture CMX_Sum_Et of CMX_Sum_Et is
  signal local_cable_to_system : std_logic_vector(4*26-1 downto 0);

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  signal bus_drive_local : std_logic_vector(1+(16*5) downto 0);
  signal data_vme_out_local : arr_16(1+(16*5)  downto 0);
  signal ctp_cable_0_internal : std_logic_vector(23 downto 0);
  signal ctp_cable_1_internal : std_logic_vector(23 downto 0);
  
  signal cnt_sum_et                : cnt_mult_arr(7 downto 0);
  signal cnt_missing_et            : cnt_mult_arr(7 downto 0);
  signal cnt_missing_et_sign       : cnt_mult_arr(7 downto 0);
  signal cnt_sum_et_weighted       : cnt_mult_arr(7 downto 0);
  signal cnt_missing_et_res        : cnt_mult_arr(7 downto 0);
  
  signal cnt_sum_et_2x16           : cnt_mult_arr_2x16(15 downto 0);
  signal cnt_missing_et_2x16       : cnt_mult_arr_2x16(15 downto 0);
  signal cnt_missing_et_sign_2x16  : cnt_mult_arr_2x16(15 downto 0);
  signal cnt_sum_et_weighted_2x16  : cnt_mult_arr_2x16(15 downto 0);
  signal cnt_missing_et_res_2x16   : cnt_mult_arr_2x16(15 downto 0);

 
  component parity_gen 
    GENERIC( 
      width : integer := 60
      );
    PORT( 
      din    : IN     std_logic_vector (width-1 downto 0) ;
      parity : OUT    std_logic 
      );
  end component;
 
  component adder_counter is
   generic(
     flavor         : T_SLV2  := "10";                                 -- JET/CPM/SUMET
      thresholds_num : integer := 25;
      width          : integer := 60
    ); 
  port(   
    clk            : in  T_SL;                                     -- clock
    reset          : in  T_SL;                                     -- reset  
    inhibit        : in  T_SL;                                     -- inhibit
     data           : in  std_logic_vector(width-1 downto 0);       -- data
    cnt_arr        : out cnt_mult_arr(thresholds_num-1 downto 0)); -- counters 
  end component adder_counter;

 component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;

  
  signal counter_inhibit_r_local : std_logic;
  signal counter_reset_r_local : std_logic;

 
begin



  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local);
  

  process(CLK)
  begin
    if rising_edge(CLK) then
      counter_inhibit_r_local<=counter_inhibit;
      counter_reset_r_local<=counter_reset;
    end if;
  end process;

  
  CRATE_SUMMING_MODULE_INST : entity work.crate_summing_module
    port map (
      CLK                => CLK,
      BACKPLANE_DATA_IN  => BACKPLANE_DATA_IN ,
      LOCAL_CABLE_OUT    => local_cable_to_system,
      BCID_in            => BCID_in,
      BCID_delayed       => BCID_delayed,
        par_err_lcl        => par_err(0),
       force              => force,
      ncs                => ncs,         
      rd_nwr             => rd_nwr,      
      ds                 => ds,          
      addr_vme           => addr_vme,    
      data_vme_in        => data_vme_in, 
      data_vme_out       => data_vme_out_local(0),
      bus_drive          => bus_drive_local(0)   
      );

  system_summing_module_inst: entity work.system_summing_module
    port map (
      CLK             => CLK,
      ENERGY_CRATE    => local_cable_to_system ,
      ENERGY_REMOTE   => ENERGY_REMOTE,
      CTP_CABLE_0     => ctp_cable_0_internal ,
      CTP_CABLE_1     => ctp_cable_1_internal ,
      MISS_E_THR      => MISS_E_THR,
      MISS_E_RES_THR  => MISS_E_RES_THR,
      SUM_ET_THR      => SUM_ET_THR,
      SUM_ET_RES_THR  => SUM_ET_RES_THR,
      XS_T2_A2        => XS_T2_A2,
      T_MISS_E_MIN    => T_MISS_E_MIN,
      T_MISS_E_MAX    => T_MISS_E_MAX,
      T_SUM_E_MIN     => T_SUM_E_MIN,
      T_SUM_E_MAX     => T_SUM_E_MAX,
      XS_B2           => XS_B2,
      sums_all_out    => sums_all_out,
      ov_all_out      => ov_all_out,

       par_err_cbl     => par_err(1),   
       force           => force, 

      ncs             => ncs,
      rd_nwr          => rd_nwr,
      ds              => ds,
      addr_vme        => addr_vme,
      data_vme_in     => data_vme_in,
      data_vme_out    => data_vme_out_local (1),
      bus_drive       => bus_drive_local (1));
  
  --SYSTEM_SUMMING_MODULE_INST : entity work.system_summing_module
  --  port map (
  --    CLK           => CLK,
  --    ENERGY_CRATE  => local_cable_to_system,
  --    ENERGY_REMOTE => ENERGY_REMOTE,
  --    CTP_CABLE_0   => ctp_cable_0_internal, -- CTP_CABLE_0,
  --    CTP_CABLE_1   => ctp_cable_1_internal, -- CTP_CABLE_1,
  --    MISS_THR      => MISS_THR,
  --    SUMET_THR     => SUMET_THR,
  --    XS_THR        => XS_THR,
  --    XS_PARAM      => XS_PARAM,
  --    ov_all_out    => ov_all_out,
  --    sums_all_out  => sums_all_out,
  --    ncs               => ncs,         
  --    rd_nwr            => rd_nwr, 
  --    ds                => ds,          
  --    addr_vme          => addr_vme,    
  --    data_vme_in       => data_vme_in, 
  --    data_vme_out      => data_vme_out_local(1),
  --    bus_drive         => bus_drive_local(1)
  --    );

-- parity

  I14 : parity_gen
    generic map (
      width  => 25
      )
    port map (
      din  => local_cable_to_system(24 downto 0),
      parity  =>  LOCAL_CABLE_OUT (25)    --  cbla, mux0
      );
  
  I15 : parity_gen
    generic map (
      width  => 25
      )
    port map (
      din  => local_cable_to_system(50 downto 26),
      parity  => LOCAL_CABLE_OUT(51)     --  cbla, mux1
      );

  I16 : parity_gen
    generic map (
      width  => 25
      )
    port map (
      din  => local_cable_to_system(76 downto 52),
      parity  => LOCAL_CABLE_OUT(77)     --  cblb, mux0
      );

  I17 : parity_gen
    generic map (
      width  => 25
      )
    port map (
     din  => local_cable_to_system(102 downto 78),
      parity  => LOCAL_CABLE_OUT(103)     --  cblb, mux1
      );



  LOCAL_CABLE_OUT(24 downto 0)   <= local_cable_to_system(24 downto 0);
  LOCAL_CABLE_OUT(50 downto 26)  <= local_cable_to_system(50 downto 26);
  LOCAL_CABLE_OUT(76 downto 52)  <= local_cable_to_system(76 downto 52);
  LOCAL_CABLE_OUT(102 downto 78) <= local_cable_to_system(102 downto 78);


  CTP_CABLE_0 <= ctp_cable_0_internal; 
  CTP_CABLE_1 <= ctp_cable_1_internal;

-- ------------------------------------------------------------------------------------
--                                   COUNTERS
-- ------------------------------------------------------------------------------------

mult_2x16: for i in 0 to 7 generate

cnt_sum_et_2x16(2*i) <= cnt_sum_et(i)(15 downto 0);
cnt_sum_et_2x16(2*i+1) <= cnt_sum_et(i)(31 downto 16);

cnt_missing_et_2x16(2*i) <= cnt_missing_et(i)(15 downto 0);
cnt_missing_et_2x16(2*i+1) <= cnt_missing_et(i)(31 downto 16);

cnt_missing_et_sign_2x16(2*i) <= cnt_missing_et_sign(i)(15 downto 0);
cnt_missing_et_sign_2x16(2*i+1) <= cnt_missing_et_sign(i)(31 downto 16);

cnt_sum_et_weighted_2x16(2*i) <= cnt_sum_et_weighted(i)(15 downto 0);
cnt_sum_et_weighted_2x16(2*i+1) <= cnt_sum_et_weighted(i)(31 downto 16);

cnt_missing_et_res_2x16(2*i) <= cnt_missing_et_res(i)(15 downto 0);
cnt_missing_et_res_2x16(2*i+1) <= cnt_missing_et_res(i)(31 downto 16);


end generate mult_2x16;

-- ------------------------------------------------------------------------------------
--                                          sum ET
-- ------------------------------------------------------------------------------------

--
--
--
cnt_sumEt: adder_counter 
   generic map(
     flavor           => "10",                                             
      thresholds_num   => 8,
      width            => 8
    )
  port map( 
    clk               => clk,
    reset             => counter_reset_r_local ,  
    inhibit           => counter_inhibit_r_local,
     data              => ctp_cable_0_internal (7 downto 0),   -- sumET
    cnt_arr           => cnt_sum_et (7 downto 0) 
  ); 

-- 
-- VME   
--  
VME_CNT_SUM_ET_COUNTER_i: for i in 0 to 15 generate
  
VME_CNT_SUM_ET_COUNTER: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_SUM_ET_COUNTER+ (2*i),
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => cnt_sum_et_2x16 (i),
      data_vme     => data_vme_out_local (i+1+1),
      bus_drive    => bus_drive_local (i+1+1)
      );  
      
end generate VME_CNT_SUM_ET_COUNTER_i;

-- ------------------------------------------------------------------------------------
--                                      MISSING ET
-- ------------------------------------------------------------------------------------
--
--
-- 
cnt_missingEt: adder_counter 
   generic map(
     flavor           => "10",                                         
      thresholds_num   => 8,
      width            => 8
    )
  port map( 
    clk               => clk,
    reset             => counter_reset_r_local ,  
    inhibit           => counter_inhibit_r_local ,
     data              => ctp_cable_0_internal (15 downto 8),   -- missing Et
    cnt_arr           => cnt_missing_et (7 downto 0) 
  ); 


-- 
-- VME   
--  
VME_CNT_MISSING_ET_COUNTER_i: for i in 0 to 15 generate
  
VME_CNT_MISSING_ET_COUNTER: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_MISSING_ET_COUNTER+ (2*i),
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => cnt_missing_et_2x16 (i),
      data_vme     => data_vme_out_local (i+1+1+16),
      bus_drive    => bus_drive_local (i+1+1+16)
      );  
    
end generate VME_CNT_MISSING_ET_COUNTER_i;


-- ------------------------------------------------------------------------------------
--                                      MISSING ET SIGNIFICANCE
-- ------------------------------------------------------------------------------------
--
  
cnt_missingEt_sign: adder_counter 
   generic map(
     flavor           => "10",                                         
      thresholds_num   => 8,
      width            => 8
    )
  port map( 
    clk               => clk,
    reset             => counter_reset_r_local ,  
    inhibit           => counter_inhibit_r_local ,
     data              => ctp_cable_0_internal (23 downto 16),   -- missing ET significance
    cnt_arr           => cnt_missing_et_sign(7 downto 0) 
  ); 
 
-- 
-- VME   
--  
VME_CNT_MISSING_ET_SIGN_COUNTER_i: for i in 0 to 15 generate
  
VME_CNT_MISSING_ET_SIGN_COUNTER: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_MISSING_ET_SIGN_COUNTER+ (2*i),
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => cnt_missing_et_sign_2x16 (i),
      data_vme     => data_vme_out_local (i+1+1+16+16),
      bus_drive    => bus_drive_local (i+1+1+16+16)
      );  
    
end generate VME_CNT_MISSING_ET_SIGN_COUNTER_i;


-- ------------------------------------------------------------------------------------
--                                      SUM ET WEIGHTED
-- ------------------------------------------------------------------------------------
--

cnt_missingEt_weighted: adder_counter 
   generic map(
     flavor           => "10",                                         
      thresholds_num   => 8,
      width            => 8
    )
  port map( 
    clk               => clk,
    reset             => counter_reset_r_local ,  
    inhibit           => counter_inhibit_r_local ,
     data              => ctp_cable_1_internal (7 downto 0),   -- missing ET significance
    cnt_arr           => cnt_sum_et_weighted(7 downto 0) 
  ); 

-- 
-- VME   
--  
VME_CNT_SUM_ET_WEIGHTED_COUNTER_i: for i in 0 to 15 generate
  
VME_CNT_SUM_ET_WEIGHTED_COUNTER: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_SUM_ET_WEIGHTED_COUNTER+ (2*i),
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => cnt_sum_et_weighted_2x16 (i),
      data_vme     => data_vme_out_local (i+1+1+16+16+16),
      bus_drive    => bus_drive_local (i+1+1+16+16+16)
      );  
 
 
end generate VME_CNT_SUM_ET_WEIGHTED_COUNTER_i;

-- ------------------------------------------------------------------------------------
--                                      MISSING ET RESTRCITED
-- ------------------------------------------------------------------------------------
--

cnt_missingEt_restricted: adder_counter 
   generic map(
     flavor           => "10",                                         
      thresholds_num   => 8,
      width            => 8
    )
  port map( 
    clk               => clk,
    reset             => counter_reset_r_local ,  
    inhibit           => counter_inhibit_r_local ,
     data              => ctp_cable_1_internal (15 downto 8),   -- missing ET restricted
    cnt_arr           => cnt_missing_et_res (7 downto 0) 
  ); 

-- 
-- VME   
--  
VME_CNT_MISS_ET_RESCTRICTED_COUNTER_i: for i in 0 to 15 generate
  
VME_CNT_MISS_ET_RESCTRICTED_COUNTER: vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_MISSING_ET_RES_COUNTER+ (2*i),
      width   => 16)
    port map (
      addr_vme     => addr_vme,
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      data_to_vme  => cnt_missing_et_res_2x16(i),
      data_vme     => data_vme_out_local (i+1+1+16+16+16+16),
      bus_drive    => bus_drive_local (i+1+1+16+16+16+16)
      );  
 
 
end generate VME_CNT_MISS_ET_RESCTRICTED_COUNTER_i;


end CMX_Sum_Et;