system_summing_module.vhd

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library IEEE;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.CMX_flavor_package.all;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;

entity system_summing_module is
  port (
    CLK   : in std_logic;

    ENERGY_CRATE   : in  std_logic_vector(26*4-1 downto 0);
    ENERGY_REMOTE  : in  std_logic_vector(26*4-1 downto 0);
    CTP_CABLE_0    : out std_logic_vector(23 downto 0);
    CTP_CABLE_1    : out std_logic_vector(23 downto 0);

    -- thresholds
    MISS_E_THR         : in arr_ctr_31bit(num_thresholds-1 downto 0);
    MISS_E_RES_THR     : in arr_ctr_31bit(num_thresholds-1 downto 0);
    SUM_ET_THR         : in arr_ctr_15bit(num_thresholds-1 downto 0);
    SUM_ET_RES_THR     : in arr_ctr_15bit(num_thresholds-1 downto 0);
    XS_T2_A2           : in arr_ctr_31bit(num_thresholds-1 downto 0);
    -- parameters
    T_MISS_E_MIN    : in arr_ctr_31bit(num_thresholds-1 downto 0); 
    T_MISS_E_MAX    : in arr_ctr_31bit(num_thresholds-1 downto 0);
    T_SUM_E_MIN     : in arr_ctr_15bit(num_thresholds-1 downto 0);
    T_SUM_E_MAX     : in arr_ctr_15bit(num_thresholds-1 downto 0);
    XS_B2           : in arr_ctr_15bit(num_thresholds-1 downto 0);
    
    sums_all_out   : out arr_ctr_15bit(5 downto 0);
    ov_all_out     : out std_logic_vector(5 downto 0);
    
    par_err_cbl      : in T_SL; -- parity error local
    force            : in T_SL; -- force
     
    --VME
    ncs           : in    std_logic;
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
end system_summing_module;

architecture system_summing_module of system_summing_module is
  signal energy_crate_delayed : std_logic_vector(ENERGY_CRATE'range);
  signal energy_crate_delayed_l, energy_remote_l : std_logic_vector(15*6+6-1 downto 0);
  signal sums_all : sum_array;
  signal ov_all : std_logic_vector(5 downto 0) := (others => '0');

  signal miss_map, res_miss_map, sumet_map, res_sumet_map : std_logic_vector(7 downto 0);
  signal xs_map: std_logic_vector(7 downto 0);



  signal EX_local : signed(max_bits_ExEy-1 downto 0);       
  signal EY_local : signed(max_bits_ExEy-1 downto 0);             
  signal TE_local : unsigned(max_bits_TE-1 downto 0);      
  signal EX_res_local : signed(max_bits_ExEy-1 downto 0);   
  signal EY_res_local : signed(max_bits_ExEy-1 downto 0);   
  signal TE_res_local : unsigned(max_bits_TE-1-1 downto 0); --the partial sums
                                                             --are 14 bits    
  signal ov_EX_local : std_logic;   
  signal ov_EY_local : std_logic;   
  signal ov_TE_local : std_logic;   
  signal ov_EX_res_local : std_logic;
  signal ov_EY_res_local : std_logic;
  signal ov_TE_res_local : std_logic;

  signal ov_EX_local_r : std_logic;   
  signal ov_EY_local_r : std_logic;   
  signal ov_TE_local_r : std_logic;   
  signal ov_EX_res_local_r : std_logic;
  signal ov_EY_res_local_r : std_logic;
  signal ov_TE_res_local_r : std_logic;

  
  signal EX_remote : signed(max_bits_ExEy-1 downto 0);       
  signal EY_remote : signed(max_bits_ExEy-1 downto 0);             
  signal TE_remote : unsigned(max_bits_TE-1 downto 0);      
  signal EX_res_remote : signed(max_bits_ExEy-1 downto 0);   
  signal EY_res_remote : signed(max_bits_ExEy-1 downto 0);   
  signal TE_res_remote : unsigned(max_bits_TE-1-1 downto 0);
  
  signal ov_EX_remote : std_logic;   
  signal ov_EY_remote : std_logic;   
  signal ov_TE_remote : std_logic;   
  signal ov_EX_res_remote : std_logic;
  signal ov_EY_res_remote : std_logic;
  signal ov_TE_res_remote : std_logic;

  signal ov_EX_remote_r : std_logic;   
  signal ov_EY_remote_r : std_logic;   
  signal ov_TE_remote_r : std_logic;   
  signal ov_EX_res_remote_r : std_logic;
  signal ov_EY_res_remote_r : std_logic;
  signal ov_TE_res_remote_r : std_logic;

  
  signal EX_total : signed(max_bits_ExEy downto 0); --one bit over, will be trimmed...
  signal EY_total : signed(max_bits_ExEy downto 0);
  
  signal TE_total : unsigned(max_bits_TE-1 downto 0);


  signal EX_res_total : signed(max_bits_ExEy downto 0); --one bit over, will be trimmed...
  signal EY_res_total : signed(max_bits_ExEy downto 0);
  
  signal TE_res_total : unsigned(max_bits_TE-1 downto 0);


  signal EX_total_trunc : signed(max_bits_ExEy-1 downto 0);
  signal EY_total_trunc : signed(max_bits_ExEy-1 downto 0);

  signal EX_res_total_trunc : signed(max_bits_ExEy-1 downto 0);
  signal EY_res_total_trunc : signed(max_bits_ExEy-1 downto 0);

  
  signal ov_EX_sum : std_logic;
  signal ov_EY_sum : std_logic;

  signal ov_EX_res_sum : std_logic;
  signal ov_EY_res_sum : std_logic;


  signal ov_EX : std_logic;
  signal ov_EY : std_logic;
  signal ov_TE : std_logic;

  signal ov_EX_res : std_logic;
  signal ov_EY_res : std_logic;
  signal ov_TE_res : std_logic;

  signal EX_total_abs : unsigned(max_bits_ExEy-1 downto 0);
  signal EY_total_abs : unsigned(max_bits_ExEy-1 downto 0);
  
  signal EX_res_total_abs : unsigned(max_bits_ExEy-1 downto 0);
  signal EY_res_total_abs : unsigned(max_bits_ExEy-1 downto 0);

  signal EX2 : unsigned(max_bits_ExEy*2 -1 downto 0);
  signal EY2 : unsigned(max_bits_ExEy*2 -1 downto 0);
  
  signal EX2_res : unsigned(max_bits_ExEy*2 -1 downto 0);
  signal EY2_res : unsigned(max_bits_ExEy*2 -1 downto 0);

  signal ov_EX_r : std_logic;
  signal ov_EY_r : std_logic;
  signal ov_EX_rr : std_logic;
  signal ov_EY_rr : std_logic;

  signal ov_EX_res_r : std_logic;
  signal ov_EY_res_r : std_logic;
  signal ov_EX_res_rr : std_logic;
  signal ov_EY_res_rr : std_logic;
  
  --the missing energy squared
  signal XE2 : unsigned(max_bits_XE2-1 downto 0);
  signal XE2_res : unsigned(max_bits_XE2-1 downto 0);

  signal s_XE2 : signed(max_bits_XE2 downto 0);
  
  signal T2_A2_B2 : arr_ctr_46bit(num_thresholds-1 downto 0);
  signal T4_A4    : arr_ctr_62bit(num_thresholds-1 downto 0);
  signal T4_A4_B2 : arr_ctr_77bit(num_thresholds-1 downto 0);

  signal us_T4_A4_B2_TE : arr_ctr_92bit(num_thresholds-1 downto 0);
  signal X4_T4_A4_B2_TE : arr_sig_95bit(num_thresholds-1 downto 0);
  signal X4_T4_A4_B2_TE_r : arr_sig_95bit(num_thresholds-1 downto 0);
  signal X4_T4_A4_B2_TE_rr : arr_sig_95bit(num_thresholds-1 downto 0);
  signal X4_T4_A4_B2_TE_rrr : arr_sig_95bit(num_thresholds-1 downto 0);
    
  signal T2_A2_TE : arr_ctr_47bit(num_thresholds-1 downto 0);

  signal us_T2_A2_TE_PLUS_T2_A2_B2 : arr_ctr_47bit(num_thresholds-1 downto 0);
  signal T2_A2_TE_PLUS_T2_A2_B2 : arr_sig_49bit(num_thresholds-1 downto 0);

  signal T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2 : arr_sig_49bit(num_thresholds-1 downto 0);

  signal T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2_ALL2 : arr_sig_98bit(num_thresholds-1 downto 0);
  
  
  
  --criterion signal missing ET
  signal c_XE : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XE_res : std_logic_vector(num_thresholds-1 downto 0);

  --register to align with TE and XS
  signal c_XE_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XE_res_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XE_rr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XE_res_rr : std_logic_vector(num_thresholds-1 downto 0);

  --delayed parity error flag to sync with the logic
  signal par_err_cbl_l : std_logic;
  signal par_err_cbl_l_0 : std_logic;
  signal par_err_cbl_l_r : std_logic;
  signal par_err_cbl_l_rr : std_logic;
  signal par_err_cbl_l_rrr : std_logic;
  signal par_err_cbl_l_rrrr : std_logic;
  signal par_err_cbl_l_rrrrr : std_logic;
  
  
  --criterion for sum ET
  signal c_TE : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_res : std_logic_vector(num_thresholds-1 downto 0);

  --register to align with missing ET and XS
  signal c_TE_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_res_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_rr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_res_rr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_rrr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_res_rrr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_rrrr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_TE_res_rrrr : std_logic_vector(num_thresholds-1 downto 0);


  
  --criterion signals for missing energy significance 
  signal c_XS_0 : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_1 : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_2 : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_3 : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_4A   : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_4A_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_4B   : std_logic_vector(num_thresholds-1 downto 0);

  signal c_XS_0_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_1_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_0_rr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_1_rr : std_logic_vector(num_thresholds-1 downto 0);
  
  signal c_XS_2_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_3_r : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_2_rr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_3_rr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_2_rrr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_3_rrr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_2_rrrr : std_logic_vector(num_thresholds-1 downto 0);
  signal c_XS_3_rrrr : std_logic_vector(num_thresholds-1 downto 0);
  

  
  signal bus_drive_local : std_logic_vector(0 downto 0);
  signal data_vme_out_local : arr_16(0 downto 0);

  constant gnd32: std_logic_vector(31 downto 0):=x"00000000";
  constant ones32: std_logic_vector(31 downto 0):=x"FFFFFFFF";
    
begin
  
  CMX_PIPELINE_MODULE_INST : entity work.CMX_pipeline_module
    generic map (
      ADDR_REG_RW_PIPELINE_DELAY_LENGTH  => ADDR_REG_RW_DELAY_INPUT_DATA_ADDER)
    port map (
      clk       => CLK,
      din       => ENERGY_CRATE ,
      dout      => energy_crate_delayed ,
      ncs                => ncs,         
      rd_nwr             => rd_nwr,      
      ds                 => ds,          
      addr_vme           => addr_vme,    
      data_vme_in        => data_vme_in, 
      data_vme_out       => data_vme_out,
      bus_drive          => bus_drive
      );
  --energy_crate_delayed <= ENERGY_CRATE;
  energy_crate_delayed_l <= crate_cable_in(energy_crate_delayed);
  --register the remote data in the system domain
  process(CLK)
  begin
    if rising_edge(CLK) then
      energy_remote_l <= crate_cable_in(ENERGY_REMOTE);
      par_err_cbl_l<=par_err_cbl;
    end if;
  end process;

  --decipher the remote and local quantities and overflows
  EX_local<=signed(energy_crate_delayed_l(14 downto 0));
  EY_local<=signed(energy_crate_delayed_l(29 downto 15));
  TE_local<=unsigned('0'&energy_crate_delayed_l(43 downto 30)); --14 bits!
  EX_res_local<=signed(energy_crate_delayed_l(59 downto 45));
  EY_res_local<=signed(energy_crate_delayed_l(74 downto 60));
  TE_res_local<=unsigned(energy_crate_delayed_l(88 downto 75)); --14 bits! 
  ov_EX_local<=energy_crate_delayed_l(90);
  ov_EY_local<=energy_crate_delayed_l(91);
  ov_TE_local<=energy_crate_delayed_l(92);
  ov_EX_res_local<=energy_crate_delayed_l(93);
  ov_EY_res_local<=energy_crate_delayed_l(94);
  ov_TE_res_local<=energy_crate_delayed_l(95);

  EX_remote<=signed(energy_remote_l(14 downto 0));
  EY_remote<=signed(energy_remote_l(29 downto 15));
  TE_remote<=unsigned('0'&energy_remote_l(43 downto 30)); --14 bits!
  EX_res_remote<=signed(energy_remote_l(59 downto 45));
  EY_res_remote<=signed(energy_remote_l(74 downto 60));
  TE_res_remote<=unsigned(energy_remote_l(88 downto 75)); --14 bits! 
  ov_EX_remote<=energy_remote_l(90);
  ov_EY_remote<=energy_remote_l(91);
  ov_TE_remote<=energy_remote_l(92);
  ov_EX_res_remote<=energy_remote_l(93);
  ov_EY_res_remote<=energy_remote_l(94);
  ov_TE_res_remote<=energy_remote_l(95);

  process(CLK)
  begin
    if rising_edge(CLK) then

      --tick 0
      EX_total<=resize(EX_remote,16)-resize(EX_local,16); --local coordinate x is
                                                          --negative on the
                                                          --'system' CMX
      EY_total<=resize(EY_remote,16)+resize(EY_local,16); --y points up on 'crate'
                                                          --and 'system'
      TE_total<=resize(TE_remote,15)+resize(TE_local,15); --14 bits from local and
                                                          --remote make 15 bits after addition
      
      
      EX_res_total<=resize(EX_res_remote,16)-resize(EX_res_local,16);
      EY_res_total<=resize(EY_res_remote,16)+resize(EY_res_local,16); 
      TE_res_total<=resize(TE_res_remote,15)+resize(TE_res_local,15);

      par_err_cbl_l_0<=par_err_cbl_l;

      ov_EX_local_r<=ov_EX_local;
      ov_EY_local_r<=ov_EY_local;
      ov_TE_local_r<=ov_TE_local;

      ov_EX_remote_r<=ov_EX_remote;
      ov_EY_remote_r<=ov_EY_remote;
      ov_TE_remote_r<=ov_TE_remote;

      ov_EX_res_local_r<=ov_EX_res_local;
      ov_EY_res_local_r<=ov_EY_res_local;
      ov_TE_res_local_r<=ov_TE_res_local;
            
      ov_EX_res_remote_r<=ov_EX_res_remote;
      ov_EY_res_remote_r<=ov_EY_res_remote;
      ov_TE_res_remote_r<=ov_TE_res_remote;
      
    end if;
  end process;

  --truncate to maximum number of bits 
  EX_total_trunc<=resize(EX_total,max_bits_ExEy);
  --if top bits (from msb downto max_bits-2 are all '0' or all '1' then there
  --is no overflow; not that to signal an overflow
  ov_EX_sum<='0' when ( std_logic_vector(EX_total(EX_total'length-1 downto max_bits_ExEy-2)) = ones32( EX_total'length-1 downto max_bits_ExEy-2)
                        or
                        std_logic_vector(EX_total(EX_total'length-1 downto max_bits_ExEy-2)) = gnd32( EX_total'length-1 downto max_bits_ExEy-2 ) ) else '1';

  --repeat for EY
  EY_total_trunc<=resize(EY_total,max_bits_ExEy);
  ov_EY_sum<='0' when  (std_logic_vector(EY_total(EY_total'length-1 downto max_bits_ExEy-2)) = ones32( EY_total'length-1 downto max_bits_ExEy-2 )
                        or
                        std_logic_vector(EY_total(EY_total'length-1 downto max_bits_ExEy-2)) = gnd32( EY_total'length-1 downto max_bits_ExEy-2 ) ) else '1';

  --restricted range EX EY truncation and overflow
  EX_res_total_trunc<=resize(EX_res_total,max_bits_ExEy);
  ov_EX_res_sum<='0' when (std_logic_vector(EX_res_total(EX_res_total'length-1 downto max_bits_ExEy-2)) = ones32( EX_res_total'length-1 downto max_bits_ExEy-2 )
                           or
                           std_logic_vector(EX_res_total(EX_res_total'length-1 downto max_bits_ExEy-2)) = gnd32( EX_res_total'length-1 downto max_bits_ExEy-2 ) ) else '1';
  EY_res_total_trunc<=resize(EY_res_total,max_bits_ExEy);
  ov_EY_res_sum<='0' when (std_logic_vector(EY_res_total(EY_res_total'length-1 downto max_bits_ExEy-2)) = ones32( EY_res_total'length-1 downto max_bits_ExEy-2 )
                           or
                           std_logic_vector(EY_res_total(EY_res_total'length-1 downto max_bits_ExEy-2)) = gnd32( EY_res_total'length-1 downto max_bits_ExEy-2 ) ) else '1';

  --combine overflows; note that we need to use the registered local and remote
  --overflows to keep the total overflow consistent in time
  ov_EX<=ov_EX_local_r or ov_EX_remote_r or ov_EX_sum;
  ov_EY<=ov_EY_local_r or ov_EY_remote_r or ov_EY_sum;
  ov_TE<=ov_TE_local_r or ov_TE_remote_r;

  ov_EX_res<=ov_EX_res_local_r or ov_EX_res_remote_r or ov_EX_res_sum;
  ov_EY_res<=ov_EY_res_local_r or ov_EY_res_remote_r or ov_EY_res_sum;
  ov_TE_res<=ov_TE_res_local_r or ov_TE_res_remote_r;

  EX_total_abs<=unsigned(std_logic_vector(abs(EX_total_trunc)));
  EY_total_abs<=unsigned(std_logic_vector(abs(EY_total_trunc)));

  EX_res_total_abs<=unsigned(std_logic_vector(abs(EX_res_total_trunc)));
  EY_res_total_abs<=unsigned(std_logic_vector(abs(EY_res_total_trunc)));

  
  --to preserve the interfaces we 're-cipher' the quantities
  sums_all(0)<=unsigned(std_logic_vector(EX_total_trunc));
  sums_all(1)<=unsigned(std_logic_vector(EY_total_trunc));
  sums_all(2)<=TE_total;
  
  sums_all(3)<=unsigned(std_logic_vector(EX_res_total_trunc));
  sums_all(4)<=unsigned(std_logic_vector(EY_res_total_trunc));
  sums_all(5)<=TE_res_total;

  ov_all(0)<=ov_EX;
  ov_all(1)<=ov_EY;
  ov_all(2)<=ov_TE;

  ov_all(3)<=ov_EX_res;
  ov_all(4)<=ov_EY_res;
  ov_all(5)<=ov_TE_res;

  

  gen_XS_criteria: for i_thr in 0 to num_thresholds-1 generate

    --multiplication of the two register values
    --no real timing requirements here
    T2_A2_B2(i_thr)<=XS_T2_A2(i_thr)*XS_B2(i_thr);
    T4_A4(i_thr)<=XS_T2_A2(i_thr)*XS_T2_A2(i_thr);
    T4_A4_B2(i_thr)<=T4_A4(i_thr)*XS_B2(i_thr);

    --leading '0' is for a '+' sign, trailing "00" is a multiplication by 4
    --(syntax error when I try & "00" don't know why)
    X4_T4_A4_B2_TE(i_thr)<=signed( '0' & (std_logic_vector(us_T4_A4_B2_TE(i_thr))) & '0' & '0' );

    --first leading 0 is to convert to '+'ve signed, next '0' is to
    --accommodate XE2 subtraction
    --doesn't like "00"&
    T2_A2_TE_PLUS_T2_A2_B2(i_thr)<=signed('0'&  ('0'& (std_logic_vector( us_T2_A2_TE_PLUS_T2_A2_B2(i_thr) ))  ) );

    process(CLK)
    begin

      if rising_edge(CLK) then

        --tick 1
        
        --this is the LHS of the comparison for criterion c4
        us_T4_A4_B2_TE(i_thr)<= T4_A4_B2(i_thr) * TE_total;
        
        --resize the result of the multiplication by 1 bit to accomodate
        --subsequent addition
        T2_A2_TE(i_thr)<=resize( XS_T2_A2(i_thr) * TE_total, max_bits_ExEy*2+1+max_bits_TE+1);

        if TE_total < T_SUM_E_MIN(i_thr) then
          c_XS_2(i_thr)<='1';
        else
          c_XS_2(i_thr)<='0';
        end if;

        if TE_total >= T_SUM_E_MAX(i_thr) or ov_TE='1' then
          c_XS_3(i_thr)<='1';
        else
          c_XS_3(i_thr)<='0';
        end if;

        --tick 2
        
        us_T2_A2_TE_PLUS_T2_A2_B2(i_thr)<=T2_A2_TE(i_thr) + T2_A2_B2(i_thr);

        --register LHS so it is matched with RHS latency
        X4_T4_A4_B2_TE_r(i_thr)<=X4_T4_A4_B2_TE(i_thr);

        c_XS_2_r(i_thr)<=c_XS_2(i_thr);
        c_XS_3_r(i_thr)<=c_XS_3(i_thr);
        
        --tick 3
        T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2(i_thr)<=T2_A2_TE_PLUS_T2_A2_B2(i_thr)-s_XE2;

        if XE2<T_MISS_E_MIN(i_thr) then
          c_XS_0(i_thr)<='1';
        else 
          c_XS_0(i_thr)<='0';
        end if;

        if XE2>T_MISS_E_MAX(i_thr) or ov_EX_rr='1' or ov_EY_rr ='1' then
          c_XS_1(i_thr)<='1';
        else 
          c_XS_1(i_thr)<='0';
        end if;

        
        --register LHS so it is matched with RHS latency
        X4_T4_A4_B2_TE_rr(i_thr)<=X4_T4_A4_B2_TE_r(i_thr);

        c_XS_2_rr(i_thr)<=c_XS_2_r(i_thr);
        c_XS_3_rr(i_thr)<=c_XS_3_r(i_thr);
        
        
        --tick 4
        T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2_ALL2(i_thr)<=T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2(i_thr)*T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2(i_thr);

        if T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2(i_thr) < to_signed(0,48) then
          c_XS_4A(i_thr)<='1';
        else
          c_XS_4A(i_thr)<='0';
        end if;
        
        --register LHS so it is matched with RHS latency
        X4_T4_A4_B2_TE_rrr(i_thr)<=X4_T4_A4_B2_TE_rr(i_thr);

        c_XS_0_r(i_thr)<=c_XS_0(i_thr);
        c_XS_1_r(i_thr)<=c_XS_1(i_thr);
        c_XS_2_rrr(i_thr)<=c_XS_2_rr(i_thr);
        c_XS_3_rrr(i_thr)<=c_XS_3_rr(i_thr);
        
        
        --tick 5

        if X4_T4_A4_B2_TE_rrr(i_thr) > T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2_ALL2(i_thr) then
          c_XS_4B(i_thr)<='1';
        else
          c_XS_4B(i_thr)<='0';
        end if;

        c_XS_0_rr(i_thr)<=c_XS_0_r(i_thr);
        c_XS_1_rr(i_thr)<=c_XS_1_r(i_thr);
        c_XS_2_rrrr(i_thr)<=c_XS_2_rrr(i_thr);
        c_XS_3_rrrr(i_thr)<=c_XS_3_rrr(i_thr);

        c_XS_4A_r(i_thr)<=c_XS_4A(i_thr);
        
        --tick 6
        if c_XS_0_rr(i_thr)='1' then
          xs_map(i_thr)<='0' or ( par_err_cbl_l_rrrrr and force);
        else
          if c_XS_1_rr(i_thr)='1' then
            xs_map(i_thr)<='1';
          else
            if c_XS_2_rrrr(i_thr)='1' or c_XS_3_rrrr(i_thr)='1' then
              xs_map(i_thr)<='0' or ( par_err_cbl_l_rrrrr and force);
            else
              if c_XS_4A_r(i_thr)='1' then
                xs_map(i_thr)<='1';
              else
                xs_map(i_thr)<=c_XS_4B(i_thr) or ( par_err_cbl_l_rrrrr and force);
              end if;
            end if;
          end if;
        end if;
        
        
        
      end if;
    end process;

  end generate gen_XS_criteria;

  
  gen_TE_criteria: for i_thr in 0 to num_thresholds-1 generate
    process(CLK)
    begin
      if rising_edge(CLK) then

        --tick 1
        if TE_total > SUM_ET_THR(i_thr) or ov_TE='1' then
          c_TE(i_thr)<='1';
        else
          c_TE(i_thr)<='0';
        end if;

        
        if TE_res_total > SUM_ET_RES_THR(i_thr) or ov_TE_res='1' then
          c_TE_res(i_thr)<='1';
        else
          c_TE_res(i_thr)<='0';
        end if;
        
        --tick 2,3,4,5
        c_TE_r(i_thr)<=c_TE(i_thr);
        c_TE_res_r(i_thr)<=c_TE_res(i_thr);

        c_TE_rr(i_thr)<=c_TE_r(i_thr);
        c_TE_res_rr(i_thr)<=c_TE_res_r(i_thr);

        c_TE_rrr(i_thr)<=c_TE_rr(i_thr);
        c_TE_res_rrr(i_thr)<=c_TE_res_rr(i_thr);

        c_TE_rrrr(i_thr)<=c_TE_rrr(i_thr);
        c_TE_res_rrrr(i_thr)<=c_TE_res_rrr(i_thr);
        
        --tick 6
        sumet_map(i_thr)<=c_TE_rrrr(i_thr) or ( par_err_cbl_l_rrrrr and force);
        res_sumet_map(i_thr)<=c_TE_res_rrrr(i_thr) or ( par_err_cbl_l_rrrrr and force);
        
      end if;
    end process;
  end generate gen_TE_criteria;

  gen_XE_criteria: for i_thr in 0 to num_thresholds-1 generate
    process(CLK)
    begin
      if rising_edge(CLK) then

        --tick 3
        if  XE2> MISS_E_THR(i_thr) or ov_EX_rr='1' or ov_EY_rr='1' then
          c_XE(i_thr)<='1';
        else
          c_XE(i_thr)<='0';
        end if;

        
        if XE2_res > MISS_E_RES_THR(i_thr) or ov_EX_res_rr='1' or ov_EY_res_rr='1'then
          c_XE_res(i_thr)<='1';
        else
          c_XE_res(i_thr)<='0';
        end if;
        
        --tick 4,5
        c_XE_r(i_thr)<=c_XE(i_thr);
        c_XE_res_r(i_thr)<=c_XE_res(i_thr);

        c_XE_rr(i_thr)<=c_XE_r(i_thr);
        c_XE_res_rr(i_thr)<=c_XE_res_r(i_thr);

        --tick 6
        miss_map(i_thr)<=c_XE_rr(i_thr) or ( par_err_cbl_l_rrrrr and force);
        res_miss_map(i_thr)<=c_XE_res_rr(i_thr) or ( par_err_cbl_l_rrrrr and force);
        
      end if;
    end process;
  end generate gen_XE_criteria;
  
  
  s_XE2<=signed('0'&(std_logic_vector(XE2)));
  
  --process that performs the sequence of common calculations
  process(CLK)
  begin
    if rising_edge(CLK) then

      --tick 1
      EX2<=EX_total_abs*EX_total_abs;
      EY2<=EY_total_abs*EY_total_abs;
      
      EX2_res<=EX_res_total_abs*EX_res_total_abs;
      EY2_res<=EY_res_total_abs*EY_res_total_abs;

      
      ov_EX_r<=ov_EX;
      ov_EY_r<=ov_EY;

      ov_EX_res_r<=ov_EX_res;
      ov_EY_res_r<=ov_EY_res;

      par_err_cbl_l_r<=par_err_cbl_l_0;

      --tick 2
      XE2<=resize(EX2,max_bits_ExEy*2+1)+EY2;
      
      XE2_res<=resize(EX2_res,max_bits_ExEy*2+1)+EY2_res;

      
      ov_EX_rr<=ov_EX_r;
      ov_EY_rr<=ov_EY_r;       

      ov_EX_res_rr<=ov_EX_res_r;
      ov_EY_res_rr<=ov_EY_res_r;

      par_err_cbl_l_rr<=par_err_cbl_l_r;

      --tick 3
      par_err_cbl_l_rrr<=par_err_cbl_l_rr;

      --tick 4
      par_err_cbl_l_rrrr<=par_err_cbl_l_rrr;

      --tick 5
      par_err_cbl_l_rrrrr<=par_err_cbl_l_rrrr;

    end if;
  end process;
  

  ov_all_out<=ov_all;
  
  sums_all_out<=sums_all(5 downto 0);

  CTP_CABLE_0 <= xs_map & miss_map & sumet_map;
  CTP_CABLE_1 <= x"00" & res_miss_map & res_sumet_map;

  
end system_summing_module;