crate_summing_module.vhd

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library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.CMX_flavor_package.all;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;

entity crate_summing_module is
  port (
    CLK                        : in  std_logic;
    BACKPLANE_DATA_IN          : in  energy_array; 
    LOCAL_CABLE_OUT            : out std_logic_vector(26*4 -1 downto 0);
    BCID_in          : in std_logic_vector(11 downto 0);
    BCID_delayed     : out std_logic_vector(11 downto 0);
    par_err_lcl      : in T_SL; -- parity error local
    force            : in T_SL; -- force
    --VME 
    ncs           : in    std_logic;    
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
   --data org 3 - OV res tyx, 3 - OV tyx, 3*15 E res tyx, 3*15 E tyx, 
    );
end crate_summing_module;

architecture crate_summing_module of crate_summing_module is
  type sum_array is array (0 to 15) of unsigned(19 downto 0);
  type sum_array_array is array (0 to 15) of sum_array;
  signal data_in_l : sum_array_array := (others => (others => (others => '0')));
  signal sum_e : sum_array_array;
  type total_sum_array is array (0 to 15) of unsigned(19 downto 0);
  signal total_sums : total_sum_array;
  signal e_ov : std_logic_vector(5 downto 0) := (others => '0');
  signal energy_out : std_logic_vector(95 downto 0);

  signal bus_drive_local : std_logic_vector(1 downto 0);
  signal data_vme_out_local : arr_16(1  downto 0);

  signal data_from_vme_REG_RW_SUMET_MASK : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RW_SUMET_MASK : std_logic_vector(15 downto 0);
  signal data_from_vme_REG_RW_MISSET_MASK : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RW_MISSET_MASK : std_logic_vector(15 downto 0);
  
  signal par_err_lcl_d0  : T_SL; -- parity error local
  
begin
-- data_in_l --should be organized on the input of the component (tyyxxtyyxx)
-- 0 - sum ex u; 1 - sum ex l, 2 -  sum ey u, 3 - sum ey l, 4 - sum et,
-- 5 - res sum ex u; 6 - res sum ex l, 7 - res sum ey u, 8 - res sum ey l, 9- res sum et,
-- quad_rest - selects if the given input is restricter or upper/lower quadrant
-- (see cmx_sumet_pkg.vhd)

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local );

  vme_inreg_notri_async_REG_RW_SUMET_MASK : entity work.vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_SUMET_MASK,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(0),
      bus_drive      => bus_drive_local (0),
      data_from_vme  => data_from_vme_REG_RW_SUMET_MASK,
      data_to_vme    => data_to_vme_REG_RW_SUMET_MASK);

  data_to_vme_REG_RW_SUMET_MASK<=data_from_vme_REG_RW_SUMET_MASK;

  vme_inreg_notri_async_REG_RW_MISSET_MASK : entity work.vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_MISSET_MASK ,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(1),
      bus_drive      => bus_drive_local (1),
      data_from_vme  => data_from_vme_REG_RW_MISSET_MASK,
      data_to_vme    => data_to_vme_REG_RW_MISSET_MASK);

  data_to_vme_REG_RW_MISSET_MASK<=data_from_vme_REG_RW_MISSET_MASK;

  RESHUFLLE_DATA: for i in 0 to 15 generate  --i iterates over module
    data_in_l(i)(0)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(13 downto 0));  --x
    data_in_l(i)(1)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(13 downto 0));  --x
    data_in_l(i)(2)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(27 downto 14)); --y
    data_in_l(i)(3)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(27 downto 14)); --y
    data_in_l(i)(4)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(41 downto 28)); --t
    data_in_l(i)(5)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(13 downto 0));  --x
    data_in_l(i)(6)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(13 downto 0));  --x
    data_in_l(i)(7)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(27 downto 14)); --y
    data_in_l(i)(8)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(27 downto 14)); --y
    data_in_l(i)(9)(13 downto 0) <= unsigned(BACKPLANE_DATA_IN(i)(41 downto 28)); --t
  end generate RESHUFLLE_DATA;

  GENERATE_ALL_SUMS : for j in 0 to 9 generate --j iterates over energy type as
                                               --above
    GENERATE_E_ADDERS : for i in 0 to 7 generate  --i iterates over modules
      CALC_SUM_E_0 : process (data_in_l, sum_e)
      begin
        
        sum_e(j)(i) <= quad_rest(data_in_l(i*2+1)(j), BACKPLANE_MAP(i*2+1),
                                 data_from_vme_REG_RW_SUMET_MASK(i*2+1),
                                 data_from_vme_REG_RW_MISSET_MASK(i*2+1),
                                 j)
                       + quad_rest(data_in_l(i*2)(j)  , BACKPLANE_MAP(i*2),
                                   data_from_vme_REG_RW_SUMET_MASK(i*2),
                                   data_from_vme_REG_RW_MISSET_MASK(i*2),
                                   j);
      end process CALC_SUM_E_0;
      
      ADDER_STAGE_1: if i < 4 generate
        CALC_SUM_E_1 : process (sum_e)
        begin
          sum_e(j)(i+8) <= sum_e(j)(i*2+1)+sum_e(j)(i*2);
        end process CALC_SUM_E_1;
      end generate ADDER_STAGE_1;

      ADDER_STAGE_2: if i < 2 generate
        CALC_SUM_E_2 : process (sum_e)
        begin
          sum_e(j)(i+12) <= sum_e(j)(i*2+1+8)+sum_e(j)(i*2+8);
        end process CALC_SUM_E_2;
      end generate ADDER_STAGE_2;

      ADDER_STAGE_3: if i < 1 generate
        CALC_SUM_E_3 : process (sum_e)
        begin
          sum_e(j)(14) <= sum_e(j)(12) + sum_e(j)(13);
        end process CALC_SUM_E_3;
      end generate ADDER_STAGE_3;

    end generate GENERATE_E_ADDERS;
  end generate GENERATE_ALL_SUMS;

  -- 0 -> Ex; 1 -> Ey; 2 -> ET; 3,4,5 as above but restricted 
  CALC_CRATE_EX_EY_ET : process (CLK)
  begin
    if rising_edge(CLK) then
      total_sums(0) <= sum_e(0)(14) + not(sum_e(1)(14)) + 1;  
      total_sums(1) <= sum_e(2)(14) + not(sum_e(3)(14)) + 1;
      total_sums(2) <= sum_e(4)(14);
      total_sums(3) <= sum_e(5)(14) + not(sum_e(6)(14)) + 1;
      total_sums(4) <= sum_e(7)(14) + not(sum_e(8)(14)) + 1;
      total_sums(5) <= sum_e(9)(14);
      BCID_delayed<=BCID_in;
      
      -- parity error delay
      par_err_lcl_d0 <= par_err_lcl;
      
    end if;
  end process CALC_CRATE_EX_EY_ET;

  GENERATE_OV : for i in 0 to 5 generate
    generate_ov_signed: if i /=2 and i/=5 generate
      CHECK_E_OV_EXEY : process (total_sums)
      begin
        --    if rising_edge(CLK) then
        if (total_sums(i)(18 downto 14) /= 0 and total_sums(i)(19) = '0') or (par_err_lcl_d0 = '1' and force = '1') then
          e_ov(i) <= '1';
          
        elsif (total_sums(i)(18 downto 14) /= "11111" and total_sums(i)(19) = '1') or (par_err_lcl_d0 = '1' and force = '1') then
          e_ov(i) <= '1';
          
        else
          e_ov(i) <= '0';
          
        end if;
        energy_out(15*(i+1)-1 downto i*15) <= std_logic_vector(total_sums(i)(14 downto 0));
        
--end if;
      end process CHECK_E_OV_EXEY;
    end generate generate_ov_signed;
    generate_ov_sumET: if i=2 or i=5 generate
      CHECK_E_OV_TE : process (total_sums)
      begin
        --    if rising_edge(CLK) then
        if total_sums(i)(18 downto 14) /= 0 or (par_err_lcl_d0 = '1' and force = '1') then
          e_ov(i) <= '1';
          
        else 
          e_ov(i) <= '0';
          
        end if;
        --fifteen bits are assigned but the msb will be truncated anyway by the
        --crate_cable_out function below
        energy_out(15*(i+1)-1 downto i*15) <= std_logic_vector(total_sums(i)(14 downto 0));
        
--end if;
      end process CHECK_E_OV_TE;
    end generate generate_ov_sumET;
    
  end generate GENERATE_OV;

  
  energy_out(energy_out'high downto energy_out'high-5) <= e_ov;

  LOCAL_CABLE_OUT <= crate_cable_out(energy_out);
  
  
end crate_summing_module;