CMX
CMX firmware code in-line documentation
 All Classes Namespaces Files Functions Variables
Signals | Constants | Processes | Instantiations
system_summing_module Architecture Reference

Processes

PROCESS_181  ( CLK )
PROCESS_182  ( CLK )
PROCESS_183  ( CLK )
PROCESS_184  ( CLK )
PROCESS_185  ( CLK )
PROCESS_186  ( CLK )

Constants

gnd32  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
ones32  std_logic_vector ( 31 downto 0 ) := x " FFFFFFFF "

Signals

energy_crate_delayed  std_logic_vector ( ENERGY_CRATE ' range )
energy_crate_delayed_l  std_logic_vector ( 15 * 6 + 6 - 1 downto 0 )
energy_remote_l  std_logic_vector ( 15 * 6 + 6 - 1 downto 0 )
sums_all  sum_array
ov_all  std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
miss_map  std_logic_vector ( 7 downto 0 )
res_miss_map  std_logic_vector ( 7 downto 0 )
sumet_map  std_logic_vector ( 7 downto 0 )
res_sumet_map  std_logic_vector ( 7 downto 0 )
xs_map  std_logic_vector ( 7 downto 0 )
EX_local  signed ( max_bits_ExEy - 1 downto 0 )
EY_local  signed ( max_bits_ExEy - 1 downto 0 )
TE_local  unsigned ( max_bits_TE - 1 downto 0 )
EX_res_local  signed ( max_bits_ExEy - 1 downto 0 )
EY_res_local  signed ( max_bits_ExEy - 1 downto 0 )
TE_res_local  unsigned ( max_bits_TE - 1 - 1 downto 0 )
ov_EX_local  std_logic
ov_EY_local  std_logic
ov_TE_local  std_logic
ov_EX_res_local  std_logic
ov_EY_res_local  std_logic
ov_TE_res_local  std_logic
ov_EX_local_r  std_logic
ov_EY_local_r  std_logic
ov_TE_local_r  std_logic
ov_EX_res_local_r  std_logic
ov_EY_res_local_r  std_logic
ov_TE_res_local_r  std_logic
EX_remote  signed ( max_bits_ExEy - 1 downto 0 )
EY_remote  signed ( max_bits_ExEy - 1 downto 0 )
TE_remote  unsigned ( max_bits_TE - 1 downto 0 )
EX_res_remote  signed ( max_bits_ExEy - 1 downto 0 )
EY_res_remote  signed ( max_bits_ExEy - 1 downto 0 )
TE_res_remote  unsigned ( max_bits_TE - 1 - 1 downto 0 )
ov_EX_remote  std_logic
ov_EY_remote  std_logic
ov_TE_remote  std_logic
ov_EX_res_remote  std_logic
ov_EY_res_remote  std_logic
ov_TE_res_remote  std_logic
ov_EX_remote_r  std_logic
ov_EY_remote_r  std_logic
ov_TE_remote_r  std_logic
ov_EX_res_remote_r  std_logic
ov_EY_res_remote_r  std_logic
ov_TE_res_remote_r  std_logic
EX_total  signed ( max_bits_ExEy downto 0 )
EY_total  signed ( max_bits_ExEy downto 0 )
TE_total  unsigned ( max_bits_TE - 1 downto 0 )
EX_res_total  signed ( max_bits_ExEy downto 0 )
EY_res_total  signed ( max_bits_ExEy downto 0 )
TE_res_total  unsigned ( max_bits_TE - 1 downto 0 )
EX_total_trunc  signed ( max_bits_ExEy - 1 downto 0 )
EY_total_trunc  signed ( max_bits_ExEy - 1 downto 0 )
EX_res_total_trunc  signed ( max_bits_ExEy - 1 downto 0 )
EY_res_total_trunc  signed ( max_bits_ExEy - 1 downto 0 )
ov_EX_sum  std_logic
ov_EY_sum  std_logic
ov_EX_res_sum  std_logic
ov_EY_res_sum  std_logic
ov_EX  std_logic
ov_EY  std_logic
ov_TE  std_logic
ov_EX_res  std_logic
ov_EY_res  std_logic
ov_TE_res  std_logic
EX_total_abs  unsigned ( max_bits_ExEy - 1 downto 0 )
EY_total_abs  unsigned ( max_bits_ExEy - 1 downto 0 )
EX_res_total_abs  unsigned ( max_bits_ExEy - 1 downto 0 )
EY_res_total_abs  unsigned ( max_bits_ExEy - 1 downto 0 )
EX2  unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
EY2  unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
EX2_res  unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
EY2_res  unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
ov_EX_r  std_logic
ov_EY_r  std_logic
ov_EX_rr  std_logic
ov_EY_rr  std_logic
ov_EX_res_r  std_logic
ov_EY_res_r  std_logic
ov_EX_res_rr  std_logic
ov_EY_res_rr  std_logic
XE2  unsigned ( max_bits_XE2 - 1 downto 0 )
XE2_res  unsigned ( max_bits_XE2 - 1 downto 0 )
s_XE2  signed ( max_bits_XE2 downto 0 )
T2_A2_B2  arr_ctr_46bit ( num_thresholds - 1 downto 0 )
T4_A4  arr_ctr_62bit ( num_thresholds - 1 downto 0 )
T4_A4_B2  arr_ctr_77bit ( num_thresholds - 1 downto 0 )
us_T4_A4_B2_TE  arr_ctr_92bit ( num_thresholds - 1 downto 0 )
X4_T4_A4_B2_TE  arr_sig_95bit ( num_thresholds - 1 downto 0 )
X4_T4_A4_B2_TE_r  arr_sig_95bit ( num_thresholds - 1 downto 0 )
X4_T4_A4_B2_TE_rr  arr_sig_95bit ( num_thresholds - 1 downto 0 )
X4_T4_A4_B2_TE_rrr  arr_sig_95bit ( num_thresholds - 1 downto 0 )
T2_A2_TE  arr_ctr_47bit ( num_thresholds - 1 downto 0 )
us_T2_A2_TE_PLUS_T2_A2_B2  arr_ctr_47bit ( num_thresholds - 1 downto 0 )
T2_A2_TE_PLUS_T2_A2_B2  arr_sig_49bit ( num_thresholds - 1 downto 0 )
T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2  arr_sig_49bit ( num_thresholds - 1 downto 0 )
T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2_ALL2  arr_sig_98bit ( num_thresholds - 1 downto 0 )
c_XE  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XE_res  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XE_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XE_res_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XE_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XE_res_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
par_err_cbl_l  std_logic
par_err_cbl_l_0  std_logic
par_err_cbl_l_r  std_logic
par_err_cbl_l_rr  std_logic
par_err_cbl_l_rrr  std_logic
par_err_cbl_l_rrrr  std_logic
par_err_cbl_l_rrrrr  std_logic
c_TE  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_res  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_res_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_res_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_rrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_res_rrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_rrrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_TE_res_rrrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_0  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_1  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_2  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_3  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_4A  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_4A_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_4B  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_0_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_1_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_0_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_1_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_2_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_3_r  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_2_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_3_rr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_2_rrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_3_rrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_2_rrrr  std_logic_vector ( num_thresholds - 1 downto 0 )
c_XS_3_rrrr  std_logic_vector ( num_thresholds - 1 downto 0 )
bus_drive_local  std_logic_vector ( 0 downto 0 )
data_vme_out_local  arr_16 ( 0 downto 0 )

Instantiations

cmx_pipeline_module_inst  CMX_pipeline_module <Entity CMX_pipeline_module>

Detailed Description

Definition at line 53 of file system_summing_module.vhd.

Member Function Documentation

PROCESS_181 (   CLK )

Definition at line 278 of file system_summing_module.vhd.

PROCESS_182 (   CLK  
)
Process

Definition at line 313 of file system_summing_module.vhd.

PROCESS_183 (   CLK  
)
Process

Definition at line 429 of file system_summing_module.vhd.

PROCESS_184 (   CLK  
)
Process

Definition at line 549 of file system_summing_module.vhd.

PROCESS_185 (   CLK  
)
Process

Definition at line 589 of file system_summing_module.vhd.

PROCESS_186 (   CLK  
)
Process

Definition at line 626 of file system_summing_module.vhd.

Member Data Documentation

bus_drive_local std_logic_vector ( 0 downto 0 )
Signal

Definition at line 252 of file system_summing_module.vhd.

c_TE std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 212 of file system_summing_module.vhd.

c_TE_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 216 of file system_summing_module.vhd.

c_TE_res std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 213 of file system_summing_module.vhd.

c_TE_res_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 217 of file system_summing_module.vhd.

c_TE_res_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 219 of file system_summing_module.vhd.

c_TE_res_rrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 221 of file system_summing_module.vhd.

c_TE_res_rrrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 223 of file system_summing_module.vhd.

c_TE_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 218 of file system_summing_module.vhd.

c_TE_rrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 220 of file system_summing_module.vhd.

c_TE_rrrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 222 of file system_summing_module.vhd.

c_XE std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 192 of file system_summing_module.vhd.

c_XE_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 196 of file system_summing_module.vhd.

c_XE_res std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 193 of file system_summing_module.vhd.

c_XE_res_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 197 of file system_summing_module.vhd.

c_XE_res_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 199 of file system_summing_module.vhd.

c_XE_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 198 of file system_summing_module.vhd.

c_XS_0 std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 228 of file system_summing_module.vhd.

c_XS_0_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 236 of file system_summing_module.vhd.

c_XS_0_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 238 of file system_summing_module.vhd.

c_XS_1 std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 229 of file system_summing_module.vhd.

c_XS_1_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 237 of file system_summing_module.vhd.

c_XS_1_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 239 of file system_summing_module.vhd.

c_XS_2 std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 230 of file system_summing_module.vhd.

c_XS_2_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 241 of file system_summing_module.vhd.

c_XS_2_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 243 of file system_summing_module.vhd.

c_XS_2_rrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 245 of file system_summing_module.vhd.

c_XS_2_rrrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 247 of file system_summing_module.vhd.

c_XS_3 std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 231 of file system_summing_module.vhd.

c_XS_3_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 242 of file system_summing_module.vhd.

c_XS_3_rr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 244 of file system_summing_module.vhd.

c_XS_3_rrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 246 of file system_summing_module.vhd.

c_XS_3_rrrr std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 248 of file system_summing_module.vhd.

c_XS_4A std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 232 of file system_summing_module.vhd.

c_XS_4A_r std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 233 of file system_summing_module.vhd.

c_XS_4B std_logic_vector ( num_thresholds - 1 downto 0 )
Signal

Definition at line 234 of file system_summing_module.vhd.

cmx_pipeline_module_inst CMX_pipeline_module
Instantiation

Definition at line 260 of file system_summing_module.vhd.

data_vme_out_local arr_16 ( 0 downto 0 )
Signal

Definition at line 253 of file system_summing_module.vhd.

energy_crate_delayed std_logic_vector ( ENERGY_CRATE ' range )
Signal

Definition at line 54 of file system_summing_module.vhd.

energy_crate_delayed_l std_logic_vector ( 15 * 6 + 6 - 1 downto 0 )
Signal

Definition at line 55 of file system_summing_module.vhd.

energy_remote_l std_logic_vector ( 15 * 6 + 6 - 1 downto 0 )
Signal

Definition at line 55 of file system_summing_module.vhd.

EX2 unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
Signal

Definition at line 148 of file system_summing_module.vhd.

EX2_res unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
Signal

Definition at line 151 of file system_summing_module.vhd.

EX_local signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 64 of file system_summing_module.vhd.

EX_remote signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 86 of file system_summing_module.vhd.

EX_res_local signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 67 of file system_summing_module.vhd.

EX_res_remote signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 89 of file system_summing_module.vhd.

EX_res_total signed ( max_bits_ExEy downto 0 )
Signal

Definition at line 114 of file system_summing_module.vhd.

EX_res_total_abs unsigned ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 145 of file system_summing_module.vhd.

EX_res_total_trunc signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 123 of file system_summing_module.vhd.

EX_total signed ( max_bits_ExEy downto 0 )
Signal

Definition at line 108 of file system_summing_module.vhd.

EX_total_abs unsigned ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 142 of file system_summing_module.vhd.

EX_total_trunc signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 120 of file system_summing_module.vhd.

EY2 unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
Signal

Definition at line 149 of file system_summing_module.vhd.

EY2_res unsigned ( max_bits_ExEy * 2 - 1 downto 0 )
Signal

Definition at line 152 of file system_summing_module.vhd.

EY_local signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 65 of file system_summing_module.vhd.

EY_remote signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 87 of file system_summing_module.vhd.

EY_res_local signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 68 of file system_summing_module.vhd.

EY_res_remote signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 90 of file system_summing_module.vhd.

EY_res_total signed ( max_bits_ExEy downto 0 )
Signal

Definition at line 115 of file system_summing_module.vhd.

EY_res_total_abs unsigned ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 146 of file system_summing_module.vhd.

EY_res_total_trunc signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 124 of file system_summing_module.vhd.

EY_total signed ( max_bits_ExEy downto 0 )
Signal

Definition at line 109 of file system_summing_module.vhd.

EY_total_abs unsigned ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 143 of file system_summing_module.vhd.

EY_total_trunc signed ( max_bits_ExEy - 1 downto 0 )
Signal

Definition at line 121 of file system_summing_module.vhd.

gnd32 std_logic_vector ( 31 downto 0 ) := x " 00000000 "
Constant

Definition at line 255 of file system_summing_module.vhd.

miss_map std_logic_vector ( 7 downto 0 )
Signal

Definition at line 59 of file system_summing_module.vhd.

ones32 std_logic_vector ( 31 downto 0 ) := x " FFFFFFFF "
Constant

Definition at line 256 of file system_summing_module.vhd.

ov_all std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 57 of file system_summing_module.vhd.

ov_EX std_logic
Signal

Definition at line 134 of file system_summing_module.vhd.

ov_EX_local std_logic
Signal

Definition at line 71 of file system_summing_module.vhd.

ov_EX_local_r std_logic
Signal

Definition at line 78 of file system_summing_module.vhd.

ov_EX_r std_logic
Signal

Definition at line 154 of file system_summing_module.vhd.

ov_EX_remote std_logic
Signal

Definition at line 93 of file system_summing_module.vhd.

ov_EX_remote_r std_logic
Signal

Definition at line 100 of file system_summing_module.vhd.

ov_EX_res std_logic
Signal

Definition at line 138 of file system_summing_module.vhd.

ov_EX_res_local std_logic
Signal

Definition at line 74 of file system_summing_module.vhd.

ov_EX_res_local_r std_logic
Signal

Definition at line 81 of file system_summing_module.vhd.

ov_EX_res_r std_logic
Signal

Definition at line 159 of file system_summing_module.vhd.

ov_EX_res_remote std_logic
Signal

Definition at line 96 of file system_summing_module.vhd.

ov_EX_res_remote_r std_logic
Signal

Definition at line 103 of file system_summing_module.vhd.

ov_EX_res_rr std_logic
Signal

Definition at line 161 of file system_summing_module.vhd.

ov_EX_res_sum std_logic
Signal

Definition at line 130 of file system_summing_module.vhd.

ov_EX_rr std_logic
Signal

Definition at line 156 of file system_summing_module.vhd.

ov_EX_sum std_logic
Signal

Definition at line 127 of file system_summing_module.vhd.

ov_EY std_logic
Signal

Definition at line 135 of file system_summing_module.vhd.

ov_EY_local std_logic
Signal

Definition at line 72 of file system_summing_module.vhd.

ov_EY_local_r std_logic
Signal

Definition at line 79 of file system_summing_module.vhd.

ov_EY_r std_logic
Signal

Definition at line 155 of file system_summing_module.vhd.

ov_EY_remote std_logic
Signal

Definition at line 94 of file system_summing_module.vhd.

ov_EY_remote_r std_logic
Signal

Definition at line 101 of file system_summing_module.vhd.

ov_EY_res std_logic
Signal

Definition at line 139 of file system_summing_module.vhd.

ov_EY_res_local std_logic
Signal

Definition at line 75 of file system_summing_module.vhd.

ov_EY_res_local_r std_logic
Signal

Definition at line 82 of file system_summing_module.vhd.

ov_EY_res_r std_logic
Signal

Definition at line 160 of file system_summing_module.vhd.

ov_EY_res_remote std_logic
Signal

Definition at line 97 of file system_summing_module.vhd.

ov_EY_res_remote_r std_logic
Signal

Definition at line 104 of file system_summing_module.vhd.

ov_EY_res_rr std_logic
Signal

Definition at line 162 of file system_summing_module.vhd.

ov_EY_res_sum std_logic
Signal

Definition at line 131 of file system_summing_module.vhd.

ov_EY_rr std_logic
Signal

Definition at line 157 of file system_summing_module.vhd.

ov_EY_sum std_logic
Signal

Definition at line 128 of file system_summing_module.vhd.

ov_TE std_logic
Signal

Definition at line 136 of file system_summing_module.vhd.

ov_TE_local std_logic
Signal

Definition at line 73 of file system_summing_module.vhd.

ov_TE_local_r std_logic
Signal

Definition at line 80 of file system_summing_module.vhd.

ov_TE_remote std_logic
Signal

Definition at line 95 of file system_summing_module.vhd.

ov_TE_remote_r std_logic
Signal

Definition at line 102 of file system_summing_module.vhd.

ov_TE_res std_logic
Signal

Definition at line 140 of file system_summing_module.vhd.

ov_TE_res_local std_logic
Signal

Definition at line 76 of file system_summing_module.vhd.

ov_TE_res_local_r std_logic
Signal

Definition at line 83 of file system_summing_module.vhd.

ov_TE_res_remote std_logic
Signal

Definition at line 98 of file system_summing_module.vhd.

ov_TE_res_remote_r std_logic
Signal

Definition at line 105 of file system_summing_module.vhd.

par_err_cbl_l std_logic
Signal

Definition at line 202 of file system_summing_module.vhd.

par_err_cbl_l_0 std_logic
Signal

Definition at line 203 of file system_summing_module.vhd.

par_err_cbl_l_r std_logic
Signal

Definition at line 204 of file system_summing_module.vhd.

par_err_cbl_l_rr std_logic
Signal

Definition at line 205 of file system_summing_module.vhd.

par_err_cbl_l_rrr std_logic
Signal

Definition at line 206 of file system_summing_module.vhd.

par_err_cbl_l_rrrr std_logic
Signal

Definition at line 207 of file system_summing_module.vhd.

par_err_cbl_l_rrrrr std_logic
Signal

Definition at line 208 of file system_summing_module.vhd.

res_miss_map std_logic_vector ( 7 downto 0 )
Signal

Definition at line 59 of file system_summing_module.vhd.

res_sumet_map std_logic_vector ( 7 downto 0 )
Signal

Definition at line 59 of file system_summing_module.vhd.

s_XE2 signed ( max_bits_XE2 downto 0 )
Signal

Definition at line 168 of file system_summing_module.vhd.

sumet_map std_logic_vector ( 7 downto 0 )
Signal

Definition at line 59 of file system_summing_module.vhd.

sums_all sum_array
Signal

Definition at line 56 of file system_summing_module.vhd.

T2_A2_B2 arr_ctr_46bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 170 of file system_summing_module.vhd.

T2_A2_TE arr_ctr_47bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 180 of file system_summing_module.vhd.

T2_A2_TE_PLUS_T2_A2_B2 arr_sig_49bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 183 of file system_summing_module.vhd.

T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2 arr_sig_49bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 185 of file system_summing_module.vhd.

T2_A2_TE_PLUS_T2_A2_B2_MINUS_XE2_ALL2 arr_sig_98bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 187 of file system_summing_module.vhd.

T4_A4 arr_ctr_62bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 171 of file system_summing_module.vhd.

T4_A4_B2 arr_ctr_77bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 172 of file system_summing_module.vhd.

TE_local unsigned ( max_bits_TE - 1 downto 0 )
Signal

Definition at line 66 of file system_summing_module.vhd.

TE_remote unsigned ( max_bits_TE - 1 downto 0 )
Signal

Definition at line 88 of file system_summing_module.vhd.

TE_res_local unsigned ( max_bits_TE - 1 - 1 downto 0 )
Signal

Definition at line 69 of file system_summing_module.vhd.

TE_res_remote unsigned ( max_bits_TE - 1 - 1 downto 0 )
Signal

Definition at line 91 of file system_summing_module.vhd.

TE_res_total unsigned ( max_bits_TE - 1 downto 0 )
Signal

Definition at line 117 of file system_summing_module.vhd.

TE_total unsigned ( max_bits_TE - 1 downto 0 )
Signal

Definition at line 111 of file system_summing_module.vhd.

us_T2_A2_TE_PLUS_T2_A2_B2 arr_ctr_47bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 182 of file system_summing_module.vhd.

us_T4_A4_B2_TE arr_ctr_92bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 174 of file system_summing_module.vhd.

X4_T4_A4_B2_TE arr_sig_95bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 175 of file system_summing_module.vhd.

X4_T4_A4_B2_TE_r arr_sig_95bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 176 of file system_summing_module.vhd.

X4_T4_A4_B2_TE_rr arr_sig_95bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 177 of file system_summing_module.vhd.

X4_T4_A4_B2_TE_rrr arr_sig_95bit ( num_thresholds - 1 downto 0 )
Signal

Definition at line 178 of file system_summing_module.vhd.

XE2 unsigned ( max_bits_XE2 - 1 downto 0 )
Signal

Definition at line 165 of file system_summing_module.vhd.

XE2_res unsigned ( max_bits_XE2 - 1 downto 0 )
Signal

Definition at line 166 of file system_summing_module.vhd.

xs_map std_logic_vector ( 7 downto 0 )
Signal

Definition at line 60 of file system_summing_module.vhd.

The documentation for this class was generated from the following file: