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main_sys_cp.vhd
Go to the documentation of this file.
1
15
16
LIBRARY
ieee
;
17
USE
ieee
.std_logic_1164.
all
;
18
USE
ieee
.numeric_std.
all
;
19
use
ieee
.std_logic_arith.
all
;
20
use
ieee
.std_logic_unsigned.
all
;
21
LIBRARY
work
;
22
use
work
.
CMXpackage
.
all
;
23
use
work
.
CMX_flavor_package
.
all
;
24
25
26
27
entity
main_sys
is
28
generic
(
29
ADDR_REG_RW_PIPELINE_DELAY_LENGTH
:
integer
:=
0
;
30
gen_system
:
std_logic
:=
'
1
'
31
)
;
32
port
(
33
clk
:
in
T_SL
;
-- clock
34
din_cbl
:
in
T_SLV150
;
-- remote input (multiplicity)
35
din_cbla_ro
:
in
T_SL
;
-- remote overflow cbla
36
din_cblb_ro
:
in
T_SL
;
-- remote overflow cblb
37
din_cblc_ro
:
in
T_SL
;
-- remote overflow cblc
38
din_lcl
:
in
T_SLV48
;
-- local input (multiplicity), excluding parity
39
din_lcl_ro
:
in
T_SL
;
-- local overflow
40
dout
:
out
T_SLV62
;
-- global output (multiplicity), including parity
41
dout_ro
:
out
T_SL
;
-- gobal overflow
42
par_err_cbl
:
in
T_SL
;
-- parity error
43
force
:
in
T_SL
;
-- force
44
--VME control:
45
ncs
:
in
std_logic
;
46
rd_nwr
:
in
std_logic
;
47
ds
:
in
std_logic
;
48
addr_vme
:
in
std_logic_vector
(
15
downto
0
)
;
49
data_vme_in
:
in
std_logic_vector
(
15
downto
0
)
;
50
data_vme_out
:
out
std_logic_vector
(
15
downto
0
)
;
51
bus_drive
:
out
std_logic
52
)
;
53
54
-- Declarations
55
56
end
main_sys
;
57
58
59
architecture
struct
of
main_sys
is
60
61
62
-- Component Declarations
63
component
add3x4
64
port
(
65
a
:
in
T_SLV3;
66
b
:
in
T_SLV3;
67
c
:
in
T_SLV3;
68
d
:
in
T_SLV3;
69
sum
:
out
T_SLV3;
70
clk
:
in
T_SL
71
);
72
end
component
;
73
74
75
component
parity_gen
76
generic
(
77
width
:
integer
:=
60
78
);
79
port
(
80
din
:
in
std_logic_vector
(
width
-
1
downto
0
);
81
parity
:
out
std_logic
82
);
83
end
component
;
84
85
component
CMX_pipeline_module
IS
86
GENERIC
(
87
ADDR_REG_RW_PIPELINE_DELAY_LENGTH
:
integer
);
88
PORT
(
89
clk
:
IN
std_logic
;
90
din
:
IN
std_logic_vector
;
91
dout
:
OUT
std_logic_vector
;
92
--VME control:
93
ncs
:
in
std_logic
;
94
rd_nwr
:
in
std_logic
;
95
ds
:
in
std_logic
;
96
addr_vme
:
in
std_logic_vector
(
15
downto
0
);
97
data_vme_in
:
in
std_logic_vector
(
15
downto
0
);
98
data_vme_out
:
out
std_logic_vector
(
15
downto
0
);
99
bus_drive
:
out
std_logic
100
);
101
end
component
CMX_pipeline_module
;
102
103
-- End of component Declarations
104
105
-- Internal signal declarations
106
107
signal
din_cbl_a
:
T_SLV48
;
-- excluding parity
108
signal
din_cbl_b
:
T_SLV48
;
-- excluding parity
109
signal
din_cbl_c
:
T_SLV48
;
-- excluding parity
110
signal
idout
:
T_SLV48
;
-- excluding parity
111
signal
hits_dly_d
:
T_SLV48
;
-- including parity
112
signal
parity0
:
std_logic
;
113
signal
parity1
:
std_logic
;
114
115
signal
din_lcl_spec
:
T_SLV49
;
116
signal
hits_dly_d_spec
:
T_SLV49
;
-- excluding parity
117
signal
din_lcl_ro_d
:
T_SL
;
-- local input (overflow delayed)
118
signal
par_err_cbl_d0
:
T_SL
;
-- parity error delayed
119
signal
dout_tmp
:
T_SLV62
;
-- temporary data out
120
121
122
begin
123
124
din_cbl_a
(
47
downto
0
)
<=
din_cbl
(
47
downto
0
)
;
125
din_cbl_b
(
47
downto
0
)
<=
din_cbl
(
95
downto
48
)
;
126
din_cbl_c
(
47
downto
0
)
<=
din_cbl
(
143
downto
96
)
;
127
128
129
-- Architecture concurrent statements
130
131
gen_system_data
:
if
gen_system
=
'
1
'
generate
132
133
din_lcl_spec
(
47
downto
0
)
<=
din_lcl
;
134
din_lcl_spec
(
48
)
<=
din_lcl_ro
;
135
hits_dly_d
(
47
downto
0
)
<=
hits_dly_d_spec
(
47
downto
0
)
;
136
din_lcl_ro_d
<=
hits_dly_d_spec
(
48
)
;
137
138
139
pipeline_inst
:
CMX_pipeline_module
140
GENERIC
MAP
(
141
ADDR_REG_RW_PIPELINE_DELAY_LENGTH
=>
ADDR_REG_RW_PIPELINE_DELAY_LENGTH
142
)
143
PORT
MAP
(
144
clk
=>
clk
,
145
din
=>
din_lcl_spec
,
146
dout
=>
hits_dly_d_spec
,
147
--VME control:
148
ncs
=> ncs,
149
rd_nwr
=> rd_nwr,
150
ds
=> ds,
151
addr_vme
=> addr_vme,
152
data_vme_in
=> data_vme_in,
153
data_vme_out
=> data_vme_out,
154
bus_drive
=> bus_drive
155
)
;
156
157
g0
:
FOR
i
IN
0
TO
thresholds_num
-
1
GENERATE
158
I0
:
add3x4
159
port
map
(
160
clk
=>
clk
,
161
a
=>
din_cbl_a
(
(
i*3
)
+
2
downto
i*3
)
,
-- 3-bit mutliplicty
162
b
=>
din_cbl_b
(
(
i*3
)
+
2
downto
i*3
)
,
163
c
=>
din_cbl_c
(
(
i*3
)
+
2
downto
i*3
)
,
164
d
=>
hits_dly_d
(
(
i*3
)
+
2
downto
i*3
)
,
165
sum
=>
idout
(
(
i*3
)
+
2
downto
i*3
)
166
)
;
167
end
generate
g0
;
168
169
process
(
clk
)
-- global overflow
170
begin
171
if
clk
'
event
and
clk
=
'
1
'
then
172
-- overflow delay
173
dout_ro
<=
din_cbla_ro
or
din_cblb_ro
or
din_cblc_ro
or
din_lcl_ro_d
;
174
-- parity delay
175
par_err_cbl_d0
<=
par_err_cbl
;
176
177
end
if
;
178
end
process
;
179
180
181
end
generate
gen_system_data
;
182
183
184
gen_crate_data_only
:
if
gen_system
=
'
0
'
generate
185
186
idout
(
47
downto
0
)
<=
din_lcl
(
47
downto
0
)
;
187
188
end
generate
gen_crate_data_only
;
189
190
191
I1_parity0
:
parity_gen
192
generic
map
(
193
width
=>
24
194
)
195
port
map
(
196
din
=>
idout
(
23
downto
0
)
,
197
parity
=>
parity0
198
)
;
199
200
I1_parity1
:
parity_gen
201
generic
map
(
202
width
=>
24
203
)
204
port
map
(
205
din
=>
idout
(
47
downto
24
)
,
206
parity
=>
parity1
207
)
;
208
209
--
210
-- The CTP output
211
--
212
dout_tmp
(
29
downto
0
)
<=
frame_6
&
idout
(
23
downto
0
)
;
-- 3-bit mutliplicty
213
dout_tmp
(
30
)
<=
parity0
;
214
dout_tmp
(
60
downto
31
)
<=
frame_6
&
idout
(
47
downto
24
)
;
-- 3-bit mutliplicty
215
dout_tmp
(
61
)
<=
parity1
;
216
217
218
dout
<=
(
others
=
>
'
1
'
)
when
(
par_err_cbl_d0
=
'
1
'
and
force
=
'
1
'
)
else
dout_tmp
;
219
220
end
struct
;
add3x4.clk
in clkstd_logic
Definition:
add3x4.vhd:28
parity_gen
Definition:
parity_gen.vhd:18
CMX_pipeline_module.bus_drive
out bus_drivestd_logic
Definition:
CMX_pipeline_module.vhd:38
main_sys.struct.parity0
std_logic parity0
Definition:
main_sys.vhd:115
main_sys.struct.par_err_cbl_d0
T_SL par_err_cbl_d0
Definition:
main_sys.vhd:121
add3x4.a
in astd_logic_vector (2 downto 0)
Definition:
add3x4.vhd:23
CMX_pipeline_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition:
CMX_pipeline_module.vhd:35
add3x4
Definition:
add3x4.vhd:21
main_sys.struct.din_lcl_spec
T_SLV49 din_lcl_spec
Definition:
main_sys_cp.vhd:115
main_sys.din_lcl_ro
in din_lcl_roT_SL
Definition:
main_sys.vhd:39
main_sys.struct.hits_dly_d_spec
T_SLV49 hits_dly_d_spec
Definition:
main_sys_cp.vhd:116
main_sys.struct.din_cbl_b
T_SLV48 din_cbl_b
Definition:
main_sys_cp.vhd:108
main_sys.par_err_cbl
in par_err_cblT_SL
Definition:
main_sys.vhd:42
i0
add3x2 i0i0
Definition:
main_sys_cp.vhd:155
add3x4.sum
out sumstd_logic_vector (2 downto 0)
Definition:
add3x4.vhd:27
pipeline_inst
CMX_pipeline_module pipeline_instpipeline_inst
Definition:
main_sys_cp.vhd:136
CMX_pipeline_module.din
in dinstd_logic_vector
Definition:
CMX_pipeline_module.vhd:29
main_crt.work
_library_ workwork
Definition:
main_crt_vs.vhd:30
main_sys.struct.din_cbl_c
T_SLV48 din_cbl_c
Definition:
main_sys_cp.vhd:109
CMX_pipeline_module.clk
in clkstd_logic
Definition:
CMX_pipeline_module.vhd:28
main_sys.dout_ro
out dout_roT_SL
Definition:
main_sys.vhd:41
CMX_pipeline_module.dout
out doutstd_logic_vector
Definition:
CMX_pipeline_module.vhd:30
main_sys.struct.parity1
std_logic parity1
Definition:
main_sys.vhd:116
i1_parity1
parity_gen i1_parity1i1_parity1
Definition:
main_sys_cp.vhd:200
main_sys.dout
out doutT_SLV62
Definition:
main_sys.vhd:40
main_sys.din_cblb_ro
in din_cblb_roT_SL
Definition:
main_sys_cp.vhd:36
main_sys.gen_system
gen_systemstd_logic :='1'
Definition:
main_sys.vhd:32
CMX_pipeline_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition:
CMX_pipeline_module.vhd:37
parity_gen.parity
out paritystd_logic
Definition:
parity_gen.vhd:24
CMX_pipeline_module.ADDR_REG_RW_PIPELINE_DELAY_LENGTH
ADDR_REG_RW_PIPELINE_DELAY_LENGTHinteger :=0
Definition:
CMX_pipeline_module.vhd:25
i1_parity0
parity_gen i1_parity0i1_parity0
Definition:
main_sys_cp.vhd:191
main_sys.din_cblc_ro
in din_cblc_roT_SL
Definition:
main_sys_cp.vhd:37
CMXpackage
Definition:
CMXpackage.vhd:12
main_sys.din_lcl
in din_lclT_SLV60
Definition:
main_sys.vhd:38
main_sys.din_cbl
in din_cblT_SLV65
Definition:
main_sys.vhd:36
main_sys.din_cbla_ro
in din_cbla_roT_SL
Definition:
main_sys_cp.vhd:35
CMX_pipeline_module.rd_nwr
in rd_nwrstd_logic
Definition:
CMX_pipeline_module.vhd:33
main_crt.IEEE
_library_ IEEEIEEE
Definition:
main_crt_vs.vhd:24
add3x4.c
in cstd_logic_vector (2 downto 0)
Definition:
add3x4.vhd:25
main_sys.ADDR_REG_RW_PIPELINE_DELAY_LENGTH
ADDR_REG_RW_PIPELINE_DELAY_LENGTHinteger :=0
Definition:
main_sys.vhd:31
main_sys.struct.din_cbl_a
T_SLV48 din_cbl_a
Definition:
main_sys_cp.vhd:107
CMX_pipeline_module
Definition:
CMX_pipeline_module.vhd:23
parity_gen.width
widthinteger :=60
Definition:
parity_gen.vhd:20
CMX_flavor_package
Definition:
CMX_flavor_package.vhd:19
add3x4.d
in dstd_logic_vector (2 downto 0)
Definition:
add3x4.vhd:26
add3x4.b
in bstd_logic_vector (2 downto 0)
Definition:
add3x4.vhd:24
main_sys.struct.CMX_pipeline_module
CMX_pipeline_module
Definition:
main_sys.vhd:91
CMX_pipeline_module.ncs
in ncsstd_logic
Definition:
CMX_pipeline_module.vhd:32
main_sys.clk
in clkT_SL
Definition:
main_sys.vhd:35
main_sys
Definition:
main_sys.vhd:28
main_sys.struct.hits_dly_d
T_SLV48 hits_dly_d
Definition:
main_sys_cp.vhd:111
CMX_pipeline_module.ds
in dsstd_logic
Definition:
CMX_pipeline_module.vhd:34
main_sys.struct.idout
T_SLV48 idout
Definition:
main_sys_cp.vhd:110
main_sys.struct.din_lcl_ro_d
T_SL din_lcl_ro_d
Definition:
main_sys.vhd:120
main_sys.struct.dout_tmp
T_SLV62 dout_tmp
Definition:
main_sys.vhd:122
parity_gen.din
in dinstd_logic_vector (width - 1 downto 0)
Definition:
parity_gen.vhd:23
CMX_pipeline_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition:
CMX_pipeline_module.vhd:36
CP
CP_common
trunk
sources
main_sys_cp.vhd
Generated on Thu Mar 3 2016 09:59:17 for CMX by
1.8.6