main_sys.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
use work.CMXpackage.all;
use work.CMX_flavor_package.all;



entity main_sys is
  generic(
    numactchan : integer := 16;
    ADDR_REG_RW_PIPELINE_DELAY_LENGTH   : integer := 0;
    gen_system : std_logic := '1'
    );
  port( 
    clk            : in     T_SL;                            -- clock
    din_cbl        : in     T_SLV65;                         -- remote input (multiplicity)
    din_cbl_ro     : in     T_SL;                            -- remote input (overflow)
    din_lcl        : in     T_SLV60;                                    -- local  input (multiplicity), excluding parity 
    din_lcl_ro     : in     T_SL;                                   -- local  input (overflow)
    dout           : out    T_SLV62;                                -- global output (multiplicity), including parity  
    dout_ro        : out    T_SL;                            -- local overflow
    par_err_cbl    : in     T_SL;                            -- parity error
    force          : in     T_SL;                            -- force       
    --VME control:
    ncs             : in    std_logic;
    rd_nwr          : in    std_logic;
    ds              : in    std_logic;
    addr_vme        : in    std_logic_vector (15 downto 0);
    data_vme_in     : in    std_logic_vector (15 downto 0);
    data_vme_out    : out   std_logic_vector (15 downto 0);
    bus_drive       : out   std_logic
    );

-- Declarations

end main_sys ;


architecture struct of main_sys is


  -- Component Declarations
  component add3x2
    port (
      a      : in     T_SLV3;
      b      : in     T_SLV3;
      sum    : out    T_SLV3;
      clk    : in     T_SL 
      );
  end component;

  component add2x2
    port (
      a      : in     T_SLV2;
      b      : in     T_SLV2;
      sum    : out    T_SLV2;
      clk    : in     T_SL 
      );
  end component;

  component parity_gen
    generic (
      width : integer := 60
      );
    port (
      din    : in     std_logic_vector (width-1 downto 0);
      parity : out    std_logic 
      );
  end component;

  component CMX_pipeline_module IS
    GENERIC(
      ADDR_REG_RW_PIPELINE_DELAY_LENGTH  : integer);
    PORT( 
      clk    : IN     std_logic  ;
      din    : IN     std_logic_vector ;
      dout   : OUT    std_logic_vector ;
      --VME control:
      ncs           : in    std_logic;
      rd_nwr        : in    std_logic;
      ds            : in    std_logic;
      addr_vme      : in    std_logic_vector (15 downto 0);
      data_vme_in   : in    std_logic_vector (15 downto 0);
      data_vme_out  : out   std_logic_vector (15 downto 0);
      bus_drive     : out   std_logic       
      );
  end component CMX_pipeline_module;    

  -- End of component Declarations      

  -- Internal signal declarations

  signal idout           : T_SLV60;  -- excluding parity
  signal hits_dly_d      : T_SLV60;  -- excluding parity
  signal parity0         : std_logic;
  signal parity1         : std_logic;
  
  signal din_lcl_spec    : T_SLV61;
  signal hits_dly_d_spec : T_SLV61;  -- excluding parity
  signal din_lcl_ro_d    : T_SL;      -- local input (overflow delayed)
  signal par_err_cbl_d0  : T_SL;     -- parity error delayed
  signal dout_tmp        : T_SLV62;  -- temporary data out 


begin
  -- Architecture concurrent statements
  
  gen_system_data: if gen_system = '1' generate
    
    din_lcl_spec(59 downto 0) <= din_lcl;
    din_lcl_spec(60) <= din_lcl_ro; 
    hits_dly_d(59 downto 0) <= hits_dly_d_spec(59 downto 0);
    din_lcl_ro_d <= hits_dly_d_spec(60);

    
    pipeline_inst: CMX_pipeline_module
      GENERIC MAP(
        ADDR_REG_RW_PIPELINE_DELAY_LENGTH   => ADDR_REG_RW_PIPELINE_DELAY_LENGTH 
        )
      PORT MAP( 
        clk        => clk, 
        din        => din_lcl_spec ,
        dout       => hits_dly_d_spec ,
        --VME control:
        ncs                => ncs,         
        rd_nwr             => rd_nwr,     
        ds                 => ds,         
        addr_vme           => addr_vme,   
        data_vme_in        => data_vme_in,
        data_vme_out       => data_vme_out,
        bus_drive          => bus_drive
        ); 
    
    g0: FOR i IN 0 TO 9 GENERATE   
      I0 : add3x2
        port map (
          clk =>  clk,
          a  =>   din_cbl    ((i*3) + 2 downto i*3),       -- 3-bit mutliplicty
          b  =>   hits_dly_d ((i*3) + 2 downto i*3),
          sum  => idout       ((i*3) + 2 downto i*3)
          );
    end generate g0;        
    
    g1: FOR i IN 0 TO 14 GENERATE   
      I0 : add2x2
        port map (
          clk =>  clk,
          a  =>   din_cbl    ((i*2) + 31 downto (i*2) + 30), -- 2-bit multiplicity
          b  =>   hits_dly_d ((i*2) + 31 downto (i*2) + 30),
          sum  => idout       ((i*2) + 31 downto (i*2) + 30)
          );
      
    end generate g1;


    process(clk)
    begin
      if clk'event and clk = '1' then 
        -- global overflow delay      
        dout_ro <= din_cbl_ro or din_lcl_ro_d;
        -- parity delay
        par_err_cbl_d0 <= par_err_cbl; 
      end if;
    end process;  
    

  end generate gen_system_data; 


  gen_crate_data_only: if gen_system = '0' generate

--
-- din_cbl(61) &  -- parity, mux 1
-- din_cbl(60) &  -- parity, mux 0
-- din_cbl(29 downto 0);  -- 3-bit mutliplicty      
--
--
-- din_cbl(63) & -- parity, mux 1
-- din_cbl(62) & -- parity, mux 0
-- din_cbl(59 downto 30); -- 2-bit multiplicity         
--

    idout(29 downto  0) <= din_lcl(29 downto  0);
    idout(59 downto 30) <= din_lcl(59 downto 30);

  end generate gen_crate_data_only;

  I1_parity0 : parity_gen
    generic map (
      width  => 30
      )
    port map (
      din  => idout(29 downto 0),
      parity  => parity0
      );

  I1_parity1 : parity_gen
    generic map (
      width  =>  30
      )
    port map (
      din  => idout(59 downto 30),
      parity  => parity1
      ); 

--
-- The CTP output
--
  dout_tmp(29 downto 0) <= idout(29 downto 0); -- 3-bit mutliplicty
  dout_tmp(30) <= parity0;
  dout_tmp(60 downto 31) <= idout(59 downto 30); -- 2-bit mutliplicty
  dout_tmp(61) <= parity1;


  dout <= (others=>'1') when (par_err_cbl_d0 = '1' and force = '1') else dout_tmp;
  
end struct;