add3x2.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
Library cmm;

ENTITY add3x2 IS
   PORT( 
      a      : IN     std_logic_vector (2 DOWNTO 0);
      b      : IN     std_logic_vector (2 DOWNTO 0);
      sum    : OUT    std_logic_vector (2 DOWNTO 0);
      clk    : IN     std_logic
   );

-- Declarations

END add3x2 ;

-- hds interface_end
--------------------------------------------------------------------------------
ARCHITECTURE rtl_abx OF add3x2 IS
--------------------------------------------------------------------------------
-- 3-bit by 2-value adder, saturates at 7
--
  ----------
  function add2 (
      a: std_logic_vector (2 downto 0);   
      b: std_logic_vector (2 downto 0)
  ) 
  return std_logic_vector is
  ----------
  -- add two 3-bit numbers, return 3-bit result that saturates at 7.
  -- 
    variable isum: integer range 0 to 28;
    variable vsum: std_logic_vector(3 downto 0);
  ----------
  begin
    isum :=   to_integer(unsigned(a))
            + to_integer(unsigned(b));
    vsum := std_logic_vector(to_unsigned(isum, 4));
    if (vsum(3) = '1') then
      return "111";
    else
      return vsum(2 downto 0);
    end if;
  end add2;


--------------------------------------------------------------------------------
BEGIN

  clokprok: process (clk, a, b)
  --
    variable isum: integer range 0 to 14;
    variable vsum: std_logic_vector(3 downto 0);
  --
  begin
    if (clk'event and clk = '1') then
      --
      sum <= add2(a, b);
    end if;
  end process;

END rtl_abx;