add2x2.vhd

Go to the documentation of this file.

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY add2x2 IS
   PORT(
      a   : IN     std_logic_vector (1 DOWNTO 0);
      b   : IN     std_logic_vector (1 DOWNTO 0);
      clk : IN     std_logic;
      sum : OUT    std_logic_vector (1 DOWNTO 0)
   );

-- Declarations

END add2x2 ;

-- hds interface_end
------------------------------------------------------------------------------
ARCHITECTURE rtl OF add2x2 IS
------------------------------------------------------------------------------
-- 2-bit x 2 input adder, saturates at 3. 
--    

BEGIN

  regproc1: process (a, b, clk)

  variable isum: integer;

  --
  begin
    if (clk'event and clk = '1') then
       isum :=   to_integer(unsigned(a))
               + to_integer(unsigned(b));
       if (isum >= 3) then
         sum <= "11";
       else
         sum <= std_logic_vector(to_unsigned(isum, 2));
       end if;
    end if;
  end process;

END rtl;