parity_chk.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY parity_chk IS
   GENERIC( 
      width : integer := 120
   );
   PORT( 
      din    : IN     std_logic_vector (width-1 DOWNTO 0);
      parity : IN     std_logic;
      mask   : IN     std_logic;
      -- disable signal
      dout   : OUT    std_logic_vector (width-1 DOWNTO 0);
      perr   : OUT    std_logic
   );

-- Declarations

END parity_chk ;

-- hds interface_end
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF parity_chk IS
--------------------------------------------------------------------------------
-- Calculate the parity of incoming data and compere to received parity bit.
-- If error found, dout is zeroed and perr is set high. 
-- If mask is set high, dout and perr are held low.
--
-- NOTE: this logic is not obviously optimised for latency, but in practice
-- it has a latency as low as anything that is.


  signal iperr:     std_logic;
  signal idout:     std_logic_vector (width-1 DOWNTO 0);
--------------------------------------------------------------------------------
BEGIN



  parity_check: process (din, parity, mask)
    variable ourparity: std_logic;
  begin
    ourparity:= '1';                          -- odd parity
    for i in 0 to (width - 1) loop
      ourparity := ourparity xor din(i);
    end loop;
    iperr <= (ourparity xor parity) and not mask;
  end process;


  data_gater: process (din, iperr, mask)
  begin
    if (iperr = '0' and mask = '0') then
      idout <= din;
    else 
      idout <= (others=>'0');
    end if;
  end process;

    perr <= iperr;
    dout <= idout;

END rtl;