sources Directory Reference

Files
file	add3x4.vhd [code]
	The add4x3 module adds 4 3-bit numbers, return 3-bit result that saturates at 7.
file	adder_top_vs_cp.vhd [code]
	The top level module (adder_top) for the multiplicty adder (CMX CP). Instantiates components that perform backplane interpretation to count objects over programmable thresholds; If instantiated in the system flavor also instantiates components that perform global summing and form the data to send to CTP.
file	CMX_CP_Topo_Encoder.vhd [code]
	Purely combinational circuit. Takes data from the decoder and formats it for sending only 'real' logic is multiplexing in the send align signal.
file	CMX_flavor_package.vhd [code]
	This package defines constants specific to CP CMX and common to crate and system varieties.
file	CMX_top_Base_tb.vhd [code]
	The testbench module (CMX_top_Base_tb) which tests the CMX FW; The circuits generates the output and compares with the simulation. The error flag indicates the mismatch between the firmware and simulation.
file	compExch.vhd [code]
	Comparison and exchange; This module sorts two TOBs according to Et (descending). This logic is used by the cp_decoder.
file	cp_decoder.vhd [code]
	CMX data decoder based on sort, based on the jet decoder code. This logic implements a Bacher odd-even merge sort and takes upper 30 positions of the result to be loaded onto the Topo encoder and TX.
file	daq_collector.vhd [code]
	Readout component. This module formats the data for the readout (glink stream) for the CP CMX. The parity error is calculated and enclosed to the data stream.
file	main_crt_vs_cp.vhd [code]
	The crate module (main_crt) for the multiplicty adder (CMX CP). Interprets the backplane data to form local sums over threshold.
file	main_sys_cp.vhd [code]
	The system module (main_sys) for the multiplicty adder (CMX CP). Receives the local and remote counts and calculates the global counts.
file	parity_chk.vhd [code]
	The parity_chk module calculates the parity of incoming data and compare to received parity bit.
file	parity_gen.vhd [code]
	The parity_gen module generates the parity of incoming data. NOTE: this logic is not obviously optimised for latency, but in practice it has a latency as low as anything that is.
file	trig_sim.vhd [code]