parity_gen.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY parity_gen IS
   GENERIC( 
      width : integer := 60
   );
   PORT( 
      din    : IN     std_logic_vector (width-1 downto 0) ;
      parity : OUT    std_logic 
   );

-- Declarations

END parity_gen ;

-- renoir interface_end
ARCHITECTURE rtl OF parity_gen IS
--------------------------------------------------------------------------------
-- Calculate the (odd) parity of incoming data and output result.
--
--------------------------------------------------------------------------------
BEGIN

  parity_check: process (din)
    variable iparity: std_logic;
  begin
    iparity:= '1';                          -- odd parity
    for i in 0 to (width - 1) loop
      iparity := iparity xor din(i);
    end loop;
    parity <= iparity;
  end process;


END rtl;