adder_top_vs_cp.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;
use work.CMX_flavor_package.all;


entity adder_top is
  generic(
    ADDR_REG_RW_PIPELINE_DELAY_LENGTH  : integer :=0;
    gen_system : std_logic := '1'
    );
  port( 
    clk            : in     T_SL;                                -- clock
    thresholds     : in     arr_16(max_cps*16*4-1 downto 0);     -- thresholds
    datai          : in     arr_4Xword(max_cps-1 downto 0);      -- input data
    din_cbl        : in     T_SLV150;                            -- remote input (multiplicty)
    din_cbla_ro    : in     T_SL;                                -- remote overflow
    din_cblb_ro    : in     T_SL;                                -- remote overflow
    din_cblc_ro    : in     T_SL;                                -- remote overflow
    dout_lcl       : out    T_SLV48;                             -- local multiplicity
    dout_lcl_ro    : out    T_SL;                                -- local overflow 
    dout              : out    T_SLV62;                                  -- global output data (multiplicity), including parity
    dout_ro        : out    T_SL;                                -- global overflow
    dout_cbla_mux0 : out    std_logic_vector(33 downto 0);       -- cable output data (multiplicity), including parity
    dout_cbla_mux1 : out    std_logic_vector(33 downto 0);       -- cable output data (multiplicity), including parity
    --VME control:
    ncs            : in    std_logic;    
    rd_nwr         : in    std_logic;
    ds             : in    std_logic;
    addr_vme       : in    std_logic_vector (15 downto 0);
    data_vme_in    : in    std_logic_vector (15 downto 0);
    data_vme_out   : out   std_logic_vector (15 downto 0);
    bus_drive      : out   std_logic;   
    -- parity error and force handling
    par_err        : in    T_SLV2;                               -- parity error (input module - 0, RTM - 1)
    force          : in    T_SL;                                 -- force    
    -- counter signals
    reset          : in  T_SL;
    inhibit        : in  T_SL    
    );

-- Declarations

end adder_top ;

architecture struct of adder_top is

  -- Internal signal declarations
  signal mult_local        : T_SLV48;
  signal internal_dout     : T_SLV62;
  signal internal_dout_cnt : T_SLV48;

  
  signal cbla_mux0      : std_logic_vector(33 downto 0);
  signal cbla_mux1      : std_logic_vector(33 downto 0);  
  
  signal parity_cbla_mux0  : std_logic;
  signal parity_cbla_mux1  : std_logic;  
  
  signal dout_lcl_ro_int   : T_SL;
  
  signal bus_drive_local  : std_logic_vector(12*thresholds_num+1 downto 0);
  signal data_vme_out_local : arr_16(12*thresholds_num+1 downto 0);

  signal    cnt_mult_local       : cnt_mult_arr(thresholds_num-1 downto 0);
  signal    cnt_mult_remote      : cnt_mult_arr((3*thresholds_num)-1 downto 0);
  signal    cnt_mult_total       : cnt_mult_arr(thresholds_num-1 downto 0);

  signal    cnt_mult_local_2x16  : cnt_mult_arr_2x16((2*thresholds_num)-1 downto 0);
  signal    cnt_mult_remote_2x16 : cnt_mult_arr_2x16((3*2*thresholds_num)-1 downto 0);
  signal    cnt_mult_total_2x16  : cnt_mult_arr_2x16((2*thresholds_num)-1 downto 0);
  
  -- Component Declarations
  component main_crt
    port (  
      clk            : in     T_SL;         -- clock 
      thresholds     : in     arr_16(max_cps*16*4-1 downto 0);           -- thresholds
      datai          : in     arr_4Xword(max_cps-1 downto 0);            -- input data
      dout_lcl       : out    T_SLV48;                                             -- local output (multiplicity), excluding parity
      dout_lcl_ro    : out    T_SL;                                      -- local overflow
      par_err_lcl    : in     T_SL;                                      -- parity error local
      force          : in     T_SL;                                       -- force
      disable_overflow_mask : in std_logic_vector(15 downto 0)
      );
  end component;

  signal disable_overflow_mask : std_logic_vector(15 downto 0);
  
  component main_sys
    generic(
      ADDR_REG_RW_PIPELINE_DELAY_LENGTH   : integer := 0;
      gen_system : std_logic := '1');
    port (  
      clk             : in     T_SL;                                    -- clock
      din_cbl         : in     T_SLV150;                              -- remote input (multiplicity)
      din_cbla_ro     : in     T_SL;                                  -- remote overflow cbla
      din_cblb_ro     : in     T_SL;                                  -- remote overflow cblb
      din_cblc_ro     : in     T_SL;                                  -- remote overflow cblc
      din_lcl         : in     T_SLV48;                              -- local input  (multiplicity), excluding parity
      din_lcl_ro      : in     T_SL;                                  -- local overflow
      dout            : out    T_SLV62;                                         -- global output (mutliplicity) to CTP
      dout_ro         : out    T_SL;                                  -- global overflow
      par_err_cbl     : in     T_SL;                                  -- parity error   
      force           : in     T_SL;                                  -- force          
      --VME control:
      ncs             : in    std_logic;
      rd_nwr          : in    std_logic;
      ds              : in    std_logic;
      addr_vme        : in    std_logic_vector (15 downto 0);
      data_vme_in     : in    std_logic_vector (15 downto 0);
      data_vme_out    : out   std_logic_vector (15 downto 0);
      bus_drive       : out   std_logic
      );  
  end component;

  component parity_gen
    GENERIC(
      width : integer := 60
      );
    PORT(
      din    : IN  std_logic_vector (width-1 downto 0);
      parity : OUT std_logic
      );
  end component;

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;

  
  component adder_counter is
    generic(
      flavor         : T_SLV2 := "00";                              -- JET/CPM
      thresholds_num : integer := 25;
      width          : integer := 60
      ); 
    port( 
      clk            : in  std_logic;                                -- clock
      reset          : in  std_logic;                                -- reset  
      inhibit        : in  std_logic;                                -- inhibit
      data           : in  std_logic_vector(width-1 downto 0);       -- data
      cnt_arr        : out cnt_mult_arr(thresholds_num-1 downto 0)); -- counters 
  end component adder_counter;
  
  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;

  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;

  signal data_from_vme_REG_RW_DISABLE_OVERFLOW_MASK : std_logic_vector(15 downto 0);
  signal data_to_vme_REG_RW_DISABLE_OVERFLOW_MASK :   std_logic_vector(15 downto 0);

  
begin

  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local);
  
  I12 : main_crt
    port map (
      clk             => clk,
      thresholds      => thresholds,
      datai           => datai,
      dout_lcl        => mult_local,
      dout_lcl_ro     => dout_lcl_ro_int ,
      par_err_lcl     => par_err(0),
      force           => force,
      disable_overflow_mask  => disable_overflow_mask
      );
  
  I13 : main_sys
    generic map(
      ADDR_REG_RW_PIPELINE_DELAY_LENGTH  => ADDR_REG_RW_PIPELINE_DELAY_LENGTH,
      gen_system  => gen_system 
      )
    port map (
      clk             => clk,
      din_cbl         => din_cbl,
      din_cbla_ro     => din_cbla_ro,
      din_cblb_ro     => din_cblb_ro,
      din_cblc_ro     => din_cblc_ro,
      din_lcl         => mult_local,
      din_lcl_ro      => dout_lcl_ro_int , 
      dout            => internal_dout ,
      dout_ro         => dout_ro,
      par_err_cbl     => par_err(1),
      force            => force,    
      -- VME control:
      ncs                => ncs,         
      rd_nwr             => rd_nwr,
      ds                 => ds,         
      addr_vme           => addr_vme,   
      data_vme_in        => data_vme_in,
      data_vme_out       => data_vme_out_local(0),
      bus_drive          => bus_drive_local(0)
      );
  
  dout <= internal_dout;

  I14 : parity_gen
    generic map (
      width  => 24
      )
    port map (
      din     => internal_dout(23 downto 0),
      parity  => parity_cbla_mux0 
      );

  I15 : parity_gen
    generic map (
      width  => 25
      )
    port map (
      din     => dout_lcl_ro_int & internal_dout   (54 downto 31),
      parity  => parity_cbla_mux1 
      );


  --
  --   DAQ output:
  
  dout_lcl <= mult_local;
  dout_lcl_ro <= dout_lcl_ro_int;

  dout_cbla_mux0 <= zero & parity_cbla_mux0 & frame_8 & internal_dout(23 downto 0); 
  dout_cbla_mux1 <= zero & parity_cbla_mux1 & frame_7 & dout_lcl_ro_int & internal_dout(54 downto 31);  

-- ------------------------------------------------------------------------------------
--                                      MULT LOCAL COUNTERS - SYSTEM
-- ------------------------------------------------------------------------------------

  gen_mult_counters_system: if gen_system = '1' generate


    mult_2x16_general: for i in 0 to thresholds_num-1 generate

      cnt_mult_local_2x16(2*i) <= cnt_mult_local(i)(15 downto 0);
      cnt_mult_local_2x16(2*i+1) <= cnt_mult_local(i)(31 downto 16);

      cnt_mult_total_2x16(2*i) <= cnt_mult_total(i)(15 downto 0);
      cnt_mult_total_2x16(2*i+1) <= cnt_mult_total(i)(31 downto 16);

    end generate mult_2x16_general;

    mult_2x16_remote: for i in 0 to (3*thresholds_num)-1 generate

      cnt_mult_remote_2x16(2*i) <= cnt_mult_remote(i)(15 downto 0);
      cnt_mult_remote_2x16(2*i+1) <= cnt_mult_remote(i)(31 downto 16);

    end generate mult_2x16_remote;



--
--
--
    adder_cnt_mult_local: adder_counter 
      generic map(
        flavor           => "01",                                          
        thresholds_num   => thresholds_num,
        width            => 48
        )
      port map( 
        clk               => clk,
        reset             => reset,  
        inhibit           => inhibit,
        data              => mult_local,
        cnt_arr           => cnt_mult_local(thresholds_num-1 downto 0) 
        ); 

-- 
-- VME   
--  
    VME_CNT_MULT_LOCAL_COUNTER_i: for i in 0 to (2*thresholds_num)-1 generate
      
      VME_CNT_MULT_LOCAL_COUNTER: vme_outreg_notri_async
        generic map (
          ia_vme  => ADDR_REG_RO_MULT_LOCAL_COUNTER+(2*i),
          width   => 16)
        port map (
          addr_vme     => addr_vme,
          ncs          => ncs,
          rd_nwr       => rd_nwr ,
          ds           => ds,
          data_to_vme  => cnt_mult_local_2x16 (i),
          data_vme     => data_vme_out_local (i+1),
          bus_drive    => bus_drive_local(i+1)
          );  
      
    end generate VME_CNT_MULT_LOCAL_COUNTER_i;

-- ------------------------------------------------------------------------------------
--                                      MULT REMOTE COUNTERS
-- ------------------------------------------------------------------------------------
--
--
-- 
    adder_cnt_mult_remote: adder_counter 
      generic map(
        flavor           => "01",                                          
        thresholds_num   => thresholds_num*3 ,
        width            => 144
        )
      port map( 
        clk               => clk,
        reset             => reset,  
        inhibit           => inhibit,
        data              => din_cbl(143 downto 0),
        cnt_arr           => cnt_mult_remote((thresholds_num*3)-1 downto 0) 
        ); 


-- 
-- VME   
--  
    VME_CNT_MULT_REMOTE_COUNTER_i: for i in 0 to (3*2*thresholds_num)-1 generate
      
      VME_CNT_MULT_REMOTE_COUNTER: vme_outreg_notri_async
        generic map (
          ia_vme  => ADDR_REG_RO_MULT_REMOTE_COUNTER+(2*i),
          width   => 16)
        port map (
          addr_vme     => addr_vme,
          ncs          => ncs,
          rd_nwr       => rd_nwr ,
          ds           => ds,
          data_to_vme  => cnt_mult_remote_2x16(i),
          data_vme     => data_vme_out_local (i+1+2*thresholds_num),
          bus_drive    => bus_drive_local(i+1+2*thresholds_num)
          );  
      
    end generate VME_CNT_MULT_REMOTE_COUNTER_i;


-- ------------------------------------------------------------------------------------
--                                      MULT TOTAL COUNTERS
-- ------------------------------------------------------------------------------------
--
-- The parity excluded.
--

    internal_dout_cnt(23 downto  0) <= internal_dout(23 downto 0);  -- 3 bit mutliplicity
    internal_dout_cnt(47 downto 24) <= internal_dout(54 downto 31); -- 2 bit mutliplicity

    
    adder_cnt_mult_total: adder_counter 
      generic map(
        flavor           => "01",                                          
        thresholds_num   => thresholds_num,
        width            => 48
        )
      port map( 
        clk               => clk,
        reset             => reset,  
        inhibit           => inhibit,
        data              => internal_dout_cnt ,
        cnt_arr           => cnt_mult_total(thresholds_num-1 downto 0) 
        ); 
    
-- 
-- VME   
--  
    VME_CNT_MULT_TOTAL_COUNTER_i: for i in 0 to (2*thresholds_num)-1 generate
      
      VME_CNT_MULT_TOTAL_COUNTER: vme_outreg_notri_async
        generic map (
          ia_vme  => ADDR_REG_RO_MULT_TOTAL_COUNTER+(2*i),
          width   => 16)
        port map (
          addr_vme     => addr_vme,
          ncs          => ncs,
          rd_nwr       => rd_nwr ,
          ds           => ds,
          data_to_vme  => cnt_mult_total_2x16 (i),
          data_vme     => data_vme_out_local (i+1+2*thresholds_num+3*2*thresholds_num),
          bus_drive    => bus_drive_local(i+1+2*thresholds_num+3*2*thresholds_num)
          );  
      
    end generate VME_CNT_MULT_TOTAL_COUNTER_i;


  end generate gen_mult_counters_system;



-- ------------------------------------------------------------------------------------
--                                      MULT LOCAL COUNTERS - CRATE
-- ------------------------------------------------------------------------------------

  gen_mult_counters_crate: if gen_system = '0' generate

    mult_2x16: for i in 0 to thresholds_num-1 generate

      cnt_mult_local_2x16(2*i) <= cnt_mult_local(i)(15 downto 0);
      cnt_mult_local_2x16(2*i+1) <= cnt_mult_local(i)(31 downto 16);

    end generate mult_2x16;


    adder_cnt_mult_local: adder_counter 
      generic map(
        flavor           => "01",                                          
        thresholds_num   => thresholds_num,
        width            => 48
        )
      port map( 
        clk               => clk,
        reset             => reset,  
        inhibit           => inhibit,
        data              => mult_local,
        cnt_arr           => cnt_mult_local(thresholds_num-1 downto 0) 
        ); 

-- 
-- VME   
--  
    VME_CNT_MULT_LOCAL_COUNTER_i: for i in 0 to (2*thresholds_num)-1 generate
      
      VME_CNT_MULT_LOCAL_COUNTER: vme_outreg_notri_async
        generic map (
          ia_vme  => ADDR_REG_RO_MULT_LOCAL_COUNTER+(2*i),
          width   => 16)
        port map (
          addr_vme     => addr_vme,
          ncs          => ncs,
          rd_nwr       => rd_nwr ,
          ds           => ds,
          data_to_vme  => cnt_mult_local_2x16 (i),
          data_vme     => data_vme_out_local (i+1),
          bus_drive    => bus_drive_local(i+1)
          );  
      
    end generate VME_CNT_MULT_LOCAL_COUNTER_i;


  end generate gen_mult_counters_crate;

  

  vme_inreg_notri_async_REG_RW_DISABLE_OVERFLOW_MASK : entity work.vme_inreg_notri_async
          generic map (
            ia_vme  => ADDR_REG_RW_DISABLE_OVERFLOW_MASK,
            width   => 16)
          port map (
            ncs            => ncs,
            rd_nwr         => rd_nwr,
            ds             => ds,
            addr_vme       => addr_vme,
            data_vme_in    => data_vme_in,
            data_vme_out   => data_vme_out_local(12*thresholds_num+1),
            bus_drive      => bus_drive_local(12*thresholds_num+1),
            data_from_vme  => data_from_vme_REG_RW_DISABLE_OVERFLOW_MASK,
            data_to_vme    => data_to_vme_REG_RW_DISABLE_OVERFLOW_MASK);

  data_to_vme_REG_RW_DISABLE_OVERFLOW_MASK<=data_from_vme_REG_RW_DISABLE_OVERFLOW_MASK;
  disable_overflow_mask<=data_from_vme_REG_RW_DISABLE_OVERFLOW_MASK;
  
end struct;