add3x4.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
Library work;
--use work.CMXpackage.all;
--use work.CMX_CP_package.all;


ENTITY add3x4 IS
  PORT( 
    a      : IN     std_logic_vector (2 DOWNTO 0);
    b      : IN     std_logic_vector (2 DOWNTO 0);
    c      : IN     std_logic_vector (2 DOWNTO 0);
    d      : IN     std_logic_vector (2 DOWNTO 0);
    sum    : OUT    std_logic_vector (2 DOWNTO 0);
    clk    : IN     std_logic
    );

-- Declarations

END add3x4 ;

-- hds interface_end
--------------------------------------------------------------------------------
ARCHITECTURE rtl_abx OF add3x4 IS
--------------------------------------------------------------------------------
-- 3-bit by 2-value adder, saturates at 7
--
  ----------
  function add4 (
    a: std_logic_vector (2 downto 0);   
    b: std_logic_vector (2 downto 0);
    c: std_logic_vector (2 downto 0);
    d: std_logic_vector (2 downto 0)
    ) 
    return std_logic_vector is
    ----------
    -- add two 3-bit numbers, return 3-bit result that saturates at 7.
    -- 
    variable isum: integer range 0 to 28;
    variable vsum: std_logic_vector(4 downto 0);
  ----------
  begin
    isum :=   to_integer(unsigned(a))
              + to_integer(unsigned(b)) 
              + to_integer(unsigned(c))
              + to_integer(unsigned(d));
    vsum := std_logic_vector(to_unsigned(isum, 5));
    if (vsum(3) = '1' or vsum(4) = '1') then
      return "111";
    else
      return vsum(2 downto 0);
    end if;
  end add4;


--------------------------------------------------------------------------------
BEGIN

  clokprok: process (clk, a, b, c, d)
    --
    variable vsum: std_logic_vector(3 downto 0);
  --
  begin
    if (clk'event and clk = '1') then
      --
      sum <= add4(a, b, c, d);
    end if;
  end process;

END rtl_abx;