struct Architecture Reference

Processes
PROCESS_141	( clk )
PROCESS_175	( clk )

Components
add3x2	<Entity add3x2>
add2x2	<Entity add2x2>
parity_gen	<Entity parity_gen>
CMX_pipeline_module	<Entity CMX_pipeline_module>
add3x4	<Entity add3x4>

Signals
idout	T_SLV60
hits_dly_d	T_SLV60
parity0	std_logic
parity1	std_logic
din_lcl_spec	T_SLV61
hits_dly_d_spec	T_SLV61
din_lcl_ro_d	T_SL
par_err_cbl_d0	T_SL
dout_tmp	T_SLV62
din_cbl_a	T_SLV48
din_cbl_b	T_SLV48
din_cbl_c	T_SLV48
idout	T_SLV48
hits_dly_d	T_SLV48
din_lcl_spec	T_SLV49
hits_dly_d_spec	T_SLV49

Instantiations
pipeline_inst	CMX_pipeline_module <Entity CMX_pipeline_module>
i0	add3x2 <Entity add3x2>
i0	add2x2 <Entity add2x2>
i1_parity0	parity_gen <Entity parity_gen>
i1_parity1	parity_gen <Entity parity_gen>
pipeline_inst	CMX_pipeline_module <Entity CMX_pipeline_module>
i0	add3x4 <Entity add3x4>
i1_parity0	parity_gen <Entity parity_gen>
i1_parity1	parity_gen <Entity parity_gen>

Detailed Description

Definition at line 59 of file main_sys.vhd.

Member Function Documentation

PROCESS_141

(

clk

)

Definition at line 176 of file main_sys.vhd.

PROCESS_175

(

clk

)

Definition at line 169 of file main_sys_cp.vhd.

Member Data Documentation

add2x2

Component

Definition at line 72 of file main_sys.vhd.

add3x2

Component

Definition at line 63 of file main_sys.vhd.

add3x4

Component

Definition at line 63 of file main_sys_cp.vhd.

CMX_pipeline_module

Component

Definition at line 91 of file main_sys.vhd.

din_cbl_a T_SLV48

Signal

Definition at line 107 of file main_sys_cp.vhd.

din_cbl_b T_SLV48

Signal

Definition at line 108 of file main_sys_cp.vhd.

din_cbl_c T_SLV48

Signal

Definition at line 109 of file main_sys_cp.vhd.

din_lcl_ro_d T_SL

Signal

Definition at line 120 of file main_sys.vhd.

din_lcl_spec T_SLV49

Signal

Definition at line 115 of file main_sys_cp.vhd.

din_lcl_spec T_SLV61

Signal

Definition at line 118 of file main_sys.vhd.

dout_tmp T_SLV62

Signal

Definition at line 122 of file main_sys.vhd.

hits_dly_d T_SLV48

Signal

Definition at line 111 of file main_sys_cp.vhd.

hits_dly_d T_SLV60

Signal

Definition at line 114 of file main_sys.vhd.

hits_dly_d_spec T_SLV49

Signal

Definition at line 116 of file main_sys_cp.vhd.

hits_dly_d_spec T_SLV61

Signal

Definition at line 119 of file main_sys.vhd.

i0 add3x2

Instantiation

Definition at line 155 of file main_sys_cp.vhd.

i0 add3x4

Instantiation

Definition at line 158 of file main_sys_cp.vhd.

i0 add2x2

Instantiation

Definition at line 165 of file main_sys_cp.vhd.

i1_parity0 parity_gen

Instantiation

Definition at line 191 of file main_sys_cp.vhd.

i1_parity0 parity_gen

Instantiation

Definition at line 208 of file main_sys_cp.vhd.

i1_parity1 parity_gen

Instantiation

Definition at line 200 of file main_sys_cp.vhd.

i1_parity1 parity_gen

Instantiation

Definition at line 217 of file main_sys_cp.vhd.

idout T_SLV48

Signal

Definition at line 110 of file main_sys_cp.vhd.

idout T_SLV60

Signal

Definition at line 113 of file main_sys.vhd.

par_err_cbl_d0 T_SL

Signal

Definition at line 121 of file main_sys.vhd.

parity0 std_logic

Signal

Definition at line 115 of file main_sys.vhd.

parity1 std_logic

Signal

Definition at line 116 of file main_sys.vhd.

parity_gen

Component

Definition at line 81 of file main_sys.vhd.

pipeline_inst CMX_pipeline_module

Instantiation

Definition at line 136 of file main_sys_cp.vhd.

pipeline_inst CMX_pipeline_module

Instantiation

Definition at line 139 of file main_sys_cp.vhd.

---

The documentation for this class was generated from the following files:

• Jet/Jet_common/trunk/sources/main_sys.vhd
• CP/CP_common/trunk/sources/main_sys_cp.vhd